The 17th International Conference on Safety, Reliability and Security (SAFECOMP 98) LNCS, Heidelberg, 1998
|
|
- Brandon Wiggins
- 5 years ago
- Views:
Transcription
1 The 17th International Conference on Safety, Reliability and Security (SAFECOMP 98) LNCS, Heidelberg, 1998 Verifying Integrity of Decision Diagrams Rolf Drechsler Institute of Computer Science Albert-Ludwigs-University Freiburg im Breisgau, Germany Abstract Decision Diagrams (DDs) are the state-of-the-art data structure in CAD of integrated circuits. They are used in many safety critical applications, like verication. In this paper security aspects of implementation techniques of DDs are discussed. A recursive checksum technique is presented for on-line and o-line checks. These methods are used to verify the integrity of DDs. The correctness of the data structures can be veried by (nearly) no overhead. Experimental results are presented to demonstrate the eciency of this approach. 1 Introduction During the last decades, the complexity of Integrated Circuits (ICs) has increased exponentially. In the 1970's a typical microprocessor such as the Intel 8080 consisted of about 5,000 transistors while in 1993 Intel's state-of-the-art processor Pentium contains 3.1 million transistors. To handle the complexity of todays circuits the design engineers are totally dependent on Computer Aided Design (CAD), i.e., software tools. The capabilities and limitations of CAD tools have crucial impact on the performance and cost of the produced circuits as well as on the resources required to develop a circuit. Consequently, CAD for ICs is a very important and increasingly growing research area. In many tasks during the design process Decision Diagrams (DDs) are used: Most common synthesis tools for logic optimization (two-level and multi-level) are based on Binary Decision Diagrams (BDDs) [5] (see e.g. [8, 7, 23, 20]). Especially for the verication step many dierent DD types, i.e. extensions of BDDs, have been introduced [16, 12, 6, 11, 14]. Since ICs are nowadays used in many safety critical applications it is very important to make DD packages not only as fast and memory ecient as possible [2, 18, 17, 13], but also as secure as possible. So far the security aspect for DDs has not been considered. For \simple" data structures like linked lists and binary (search) trees good techniques are known for secure implementations [22, 1, 4].
2 The security aspect becomes even more important when current trends, like parallel implementations of DD packages [21], are considered. These implementations use complicated communication protocols and it is well-known that several of these protocols contain bugs (see e.g. [15]). Recently a Recursive Checksum Method (RCM) has been introduced in [4] for trees. Since most DD packages are based on recursive operations the RCM can directly be applied to DDs. The use of the RCM also helps during the implementation of a DD package, since many errors in the memory management can be detected very early. In this paper we consider methods for guaranteeing the integrity of DDs by on-line and o-line checks. We consider dierent fault types, like Copy Faults (CFs) and Memory Faults (MFs) [4]. We show that the RCM can also be applied successfully to graphs. The implementation is discussed, i.e. the RCM can be integrated in DD packages by (nearly) no overhead: Since most DD packages are based on recursive synthesis operations, like If-Then-Else for BDDs [5, 2], the recursive checksum computation can be incorporated with no additional cost (in contrast to other data structures [1, 4]). We give results on fault injection experiments for BDDs that show that all of the assumed errors can be detected at very low cost, i.e. our method can be implemented without any memory overhead (in clever implementations like [17]) and the runtime overhead is less than 5% on average. The paper is structured as follows: In Section 2 we briey review the denitions of DDs. In Section 3 we discuss the fault model considered in this paper. Section 4 describes our approach to handle the security aspect. Implementation aspects and experimental results are given in Section 5 and 6. Finally, the results are summarized. 2 Decision Diagrams We now introduce basics of DDs. We focuses less on a mathematical exact description, instead we want to give an informal description that helps the reader to get an impression of the underlying data structure. For more details see [10]. The best known DD type is the Binary Decision Diagram (BDD) [5]. The description in the following is mainly based on BDDs, but all results directly transfer to other DD types, e.g. DDs including edge values [16, 6, 11]. All DDs are graph-based representations, where at each (non-terminal) node labeled with a variable x i a decomposition of the function represented by this node into two subfunctions (the low-function and the high-function) is performed. Furthermore, the underlying graph is reduced and ordered, i.e. all redundant nodes are removed and the variables occur in the same order on all paths of the DD, respectively. E.g. for BDDs the following decomposition is considered: f = x i f low(v) + x i f high(v)
3 x 1 x 2 x Fig. 1. BDD for f = x 1x 2 + x 3 (f is the function represented at node v, f low(v) (f high(v) ) denotes the function represented by the low-edge (high-edge) of v. The recursion stops at terminal nodes labeled with 0 or 1. Example 1. In Fig. 1 the reduced ordered BDD for function f = x 1 x 2 + x 3 is given. For the representation of a node the pointer to the low- and high-function has to be stored. Further memory is needed for the index of the node and the reference counter. Additionally, to store edge values for DDs (where this is allowed) memory is needed. It is straightforward to integrate this in the approach that is presented in the following but we restrict ourselves w.l.o.g. to BDDs. Finally, we briey consider the typical synthesis operation on DDs: The synthesis of two DDs is carried out by performing a recursive call on subgraphs. For BDDs a sketch of the recursive If-Then-Else (ITE) algorithm from [2] is given in Fig. 2. Similar algorithms can be considered for word-level DDs [6, 11]. 3 Fault Model In this section we briey discuss some aspects of the fault model. As already pointed out in [22] there is no general agreement how to measure the robustness of a storage data structure. Simple errors that should be detected are errors in single bits or words, i.e. if the contents of a memory cell is modied by a fault. Additionally, in this paper we consider the fault model from [4]: We allow two kinds of memory errors in our model, i.e. Copy Faults (CFs) and Memory Allocation Faults (MAFs). Obviously, many other \real-world" faults are also covered by this model.
4 ite(f,g,h) f if (terminal case) return result; if (computed-table entry (F,G,H) exists) return result; let x i be the top variable of ff,g,hg; THEN = ite(f xi ; G xi ; H xi ) ; ELSE = ite(f xi ; G xi ; H xi ) ; if (THEN == ELSE) return THEN; // Find or create a new node with variable v and sons THEN and ELSE R = Find or add unique table(x i,then,else); // Store computation and result in computed table Insert computed table(ff,g,hg,r); g return R; Fig. 2. ITE-algorithm x 1 Node 1 x x Node x 3 x 3 x 3 x Fig. 3. Example for copy fault Copy faults: Copy the contents of one node into an other node. Memory allocation faults: Memory is allocated that has already been used by an other node. Example 2. An example for a CF is given in Fig. 3. For simplicity the nonreduced BDD of Example 1 is given. If the contents of Node 1 is copied into Node 2 the dotted pointers result. Obviously, the function being represented is changed.
5 Obviously, CFs can not be captured by checksum computations that do not consider the environment of the node, since the node itself is valid but has a wrong location. This fault may result from a wrong address to which data is written back. MAFs often occur during software development, since ecient implementations of DDs often overload the memory management of the operating system [2, 17]. (For more details on CFs and MAFs see [4].) 4 Security Aspects DDs are used in more and more applications were security is a very important aspect, e.g. verication. Thus, there is a need for secure data structures. The simplest idea to make data structures securer is to store each component several times. (Notice that in that way some kind of memory faults, like MAFs, can also not be detected.) The idea of multiple storing also leads to the ability of not only error detecting, but also error correcting data structures. These topics have been studied for \simpler" data structures like linked lists (see e.g. [22]). Storing the same information several times obviously results in large memory overhead. Also the access time per node would drastically increase for DDs, since several pointers have to be handled. (E.g. during sifting [19] often several thousand pointers have to be redirected.) In the following we restrict to the problem of error detection. A general method for making data structures more secure is the use of checksums, i.e. for each element a characteristic value is computed. The simplest example is the parity check. But this method has the drawback that errors that result from neighborhood relations (as e.g. MAFs) can not be detected. We now describe in more detail the Recursive Checksum Method (RCM) that we apply to DDs: For each node a checksum c is computed that results from the checksums c l and c r of the left and right son of the node and from a node internal information. Here we make use of the index of the node. (We will see in the following that for DDs methods based on recursive computations can easily be integrated in the synthesis operations, like ITE (see Section 2 and 5).) For the following we dene the RCM c of a node by c = (c l + c r + variable index) mod m; (1) where m denotes an integer number and variable index of a BDD node v is i i v is labeled with variable x i1. Obviously, the choice of m largely inuences the quality of the checksum. The larger m is chosen the more memory is used to store the information, but the more secure the DD gets. Example 3. If m = 2 then only a parity check is performed. Remark 1. For DD types allowing edge values these values have also to be incorporated in the checksum. 1 Here we choose a very simple function so that the description remains simple.
6 We now consider two main problems: We want to detect errors on-line and we want to check the integrity of a given DD by o-line tests. On-line check: The on-line check veries the correctness of the node during each access. This is done by recomputing the checksum of the successors during each access. Additionally, each information that is obtained by a look-up in the computed table is checked. Due to the recursive nature of the synthesis procedures on DDs and of the RCM the checksum computation can easily be incorporated in the program code. (For more details see Section 5.) O-line check: The check for integrity can be performed by a depth-rst-search algorithm starting from the roots of the DD. At each node (starting at the terminals) the checksum is recursively computed. Then a comparison to the checksum value stored in each node is carried out. If a comparison fails an error is detected. Using these on-line and o-line techniques also the software development can be simplied tremendously. As mentioned above many DD packages overload the memory management of the operating systems. Using the on-line check many errors can be detected very early. If (due to performance reasons) the on-line check is not desired during normal operation of the package it can easily be switched o. (This also oers the possibility to operate DD packages in a debug mode and in a normal operation mode.) One further advantage of an o-line check on DDs is that the nodes are referenced several times (in contrast to trees). Thus, there is a high probability to detect errors with only a small number of encoding bits (see experiments in Section 6). One problem that is not considered in this paper is the aspect of faulty computations, e.g. what happens, if the checksum computation is wrong? Previous work has proposed the term of safe and unsafe memory for other data structures. These results can directly be transfered to graphs and DDs. (For more details see e.g. [1, 4].) 5 Implementation We now briey discuss how the RCM of the previous section can be implemented in a DD package. (For the rest of this section we assume that the reader is familiar with basics about the implementation of DD packages.) In the following we restrict ourselves to the ITE operator used for BDDs. (For other DD packages based on recursive synthesis analogous modications can be given.) Only minor modications have to be performed to integrate the approach in a given DD package: { An additional (integer) value must be included in the description of a node. At this point also a short integer or only a few bits can be used, but with smaller number of memory the data structure becomes less secure (see Section 6). It depends on the designer of the data structure to determine the
7 optimal trade-o for his application: Is security or memory overhead more important? { During the recursive ITE calls the checksum has to be computed. Since ITE also works recursively only a constant overhead per node has to be invested. For each node that is newly created the checksum c is computed as described in the previous section. Example 4. For ITE-based BDD packages after each computation of the nodes THEN and ELSE (see Fig. 2) the checksum of these new nodes is veried. Thus also erroneous modications of bits (or even words) in a node can be detected. Additionally, after each successful lookup in the unique table the node is checked for correctness. Remark 2. In usual DD packages some bits are often unused, e.g. in the BDD package from [17] two bits per pointer have no functionality. Since in each node two pointers are stored, i.e. the pointers for the low- and high-function, four bits are unused. 6 Experimental Results In this section we present results of some fault injection experiments. All experiments have been carried out on a preliminary BDD package implementation on a SUN SPARCstation 4. An upper node limit of was used. Several symbolic simulation runs were considered for the combinational parts of the sequential benchmarks from [3]. For the ordering of the variables the initial ordering of the inputs as they occur in the benchmark description was used. In the rst set of experiments we considered the on-line check method, i.e. we check the data structure during the symbolic simulation. We inserted a fault by randomly changing the contents of one variable in a node. Thus, we not only considered bit faults, but also word faults that correspond to multi-bit faults. (Notice that this fault can also be detected by a conventional checksum approach. Recursive computation does not inuence the result.) We use Formula (1) for the recursive computation of the checksum 2. During each run one fault is inserted. In some cases this fault does not have to modify the result, e.g. if the fault occurs in a redundant part of the circuit during the symbolic simulation. But nevertheless the on-line check detects that something might be damaged. In Table 1 a 1 (0) denotes that the error was (not) detected. Each column denotes a dierent value for m. As can easily be seen only a few bits are needed to detect all errors in the package during the symbolic simulation of these benchmarks, i.e. only 3 bits are needed to encode the 5 values. We now focus on the o-line check for CFs and MAFs. In a second experiment we considered a successful symbolic simulation and started with a depth-rstsearch computation. We randomly inserted faults by the following procedure: 2 More sophisticated computation methods could obviously even improve the quality of the result.
8 name m = 2 m = 3 m = 4 m = 5 s s s s s s s s s s s s s s s s Table 1. On-line check name pointers faults m = 2 m = 3 m = 4 m = 5 s s s s s s s s s s s s s s s s Table 2. O-line check
9 During the construction we stored a pointer's address for fault insertion at about each 50th node creation (up to a maximum of 10 pointer addresses) 3. In the second and third column of Table 2 we give the information about the number of faults considered. pointers (faults) denotes the number of addresses stored (faults inserted). Again we considered dierent values for m. The results are given in the succeeding columns of Table 2. Once more it can be seen from the table that only 3 bits are needed to detect all faults. (For benchmark s01238 no faults have been inserted, since all stored pointers are not present in the representation of the outputs.) Even an encoding of 2 bits is able to detect most faults. This results from the fact that often the same node is referenced several times. Such during each access there is the possibility to detect the fault. As can be seen from our experiments only 3 bits are needed to detect all faults. Thus, following Remark 2 no memory overhead results for ecient DD package implementations from incorporating the RCM. In our implementation the runtime overhead was less than 5% on average. 7 Conclusions Security aspects of Decision Diagrams have been discussed. Since DDs are used in more and more safety critical applications there is a need to also make the implementation of the DD package as secure as possible. In this paper a rst step in this direction has been performed: Fault models for other data structures have been considered for DDs. The method of recursive checksum computation has been applied to DDs and has been integrated in online and o-line checks. It has been demonstrated by fault injection experiments that these methods are able to identify memory errors during the operation of a DD package. A check for the whole DD for integrity can also easily be performed. These methods can be integrated with only little overhead with respect to runtime and no overhead with respect to memory. If is focus of current work to extend the ideas discussed in this paper to DD packages that also allow dynamic minimization algorithms, like sifting [19, 9]. Furthermore, aspects of secure DDs will be extended to not only error detection but also error correction. Acknowledgment The author likes to thank Bernd Becker and Nicole Drechsler for their helpful comments. 3 The problem was that in this way we mostly stored enough pointers so that at least some were also present in the nal result, i.e. during a symbolic simulation many nodes are created that are not needed for the representation of the outputs. Thus, errors in these nodes could not be detected by the o-line test.
10 References 1. N.M. Amato and M.C. Loui. Checking linked data structures. In Int'l Symp. on Fault-Tolerant Comp., pages 164{173, K.S. Brace, R.L. Rudell, and R.E. Bryant. Ecient implementation of a BDD package. In Design Automation Conf., pages 40{45, F. Brglez, D. Bryan, and K. Kozminski. Combinational proles of sequential benchmark circuits. In Int'l Symp. Circ. and Systems, pages 1929{1934, J.D. Bright, G.F. Sullivan, and G.M. Masson. Checking the integrity of trees. In Int'l Symp. on Fault-Tolerant Comp., pages 402{411, R.E. Bryant. Graph - based algorithms for Boolean function manipulation. IEEE Trans. on Comp., 35(8):677{691, R.E. Bryant and Y.-A. Chen. Verication of arithmetic functions with binary moment diagrams. In Design Automation Conf., pages 535{541, O. Coudert. Two-level logic minimization: an overview. Integration the VLSI Jour., 17(2):97{140, O. Coudert, H. Fraisse, and J.C. Madre. A breakthrough in two-level logic minimization. In Int'l Workshop on Logic Synth., page P2b, R. Drechsler and B. Becker. Dynamic minimization of OKFDDs. In Int'l Conf. on Comp. Design, pages 602{607, R. Drechsler and B. Becker. Binary Decision Diagrams - Theory and Implementation. Kluwer Academic Publishers, R. Drechsler, B. Becker, and S. Ruppertz. K*BMDs: A new data structure for verication. In European Design & Test Conf., pages 2{8, R. Drechsler, A. Sarabi, M. Theobald, B. Becker, and M.A. Perkowski. Ecient representation and manipulation of switching functions based on ordered Kronecker functional decision diagrams. In Design Automation Conf., pages 415{419, S. Horeth. Implementation of a multiple-domain decision diagram package. In CHARME, Chapman & Hall, pages 185{202, S. Horeth and R. Drechsler. Dynamic minimization of word-level decision diagrams. In Design, Automation and Test Europe, pages 612{617, R.P. Kurshan. Computer-Aided Verication of Coordinating Processes. Princeton University Press, Y.-T. Lai and S. Sastry. Edge-valued binary decision diagrams for multi-level hierarchical verication. In Design Automation Conf., pages 608{613, D.E. Long. Long-Package Sun Release 4.1 Overview of C Library Functions S. Minato, N. Ishiura, and S. Yajima. Shared binary decision diagrams with attributed edges for ecient Boolean function manipulation. In Design Automation Conf., pages 52{57, R. Rudell. Dynamic variable ordering for ordered binary decision diagrams. In Int'l Conf. on CAD, pages 42{47, C. Scholl. Multi-output functional decomposition with exploitation of don't cares. In Design, Automation and Test Europe, pages 743{748, T. Stornetta and F. Brewer. Implementation of an ecient parallel BDD package. In Design Automation Conf., pages 641{644, D.J. Taylor. Error models for robust storage structures. In Int'l Symp. on Fault- Tolerant Comp., pages 416{422, B. Wurth, K. Eckl, and K. Antreich. Functional multiple-output decomposition: Theory and implicit algorithm. In Design Automation Conf., pages 54{59, 1995.
Checking Equivalence for Circuits Containing Incompletely Specified Boxes
Freiburg, Germany, September 00 Checking Equivalence for Circuits Containing Incompletely Specified Boxes Christoph Scholl Bernd Becker Institute of Computer Science Albert Ludwigs University D 79110 Freiburg
More informationAn Algorithm for the Construction of Decision Diagram by Eliminating, Merging and Rearranging the Input Cube Set
An Algorithm for the Construction of Decision Diagram by Eliminating, Merging and Rearranging the Input Cube Set Prof. Sudha H Ayatti Department of Computer Science & Engineering KLS GIT, Belagavi, Karnataka,
More informationImplementing a Multiple-Valued Decision Diagram Package
ISMVL-98 Page 1 Implementing a Multiple-Valued Decision Diagram Package D. Michael Miller Rolf Drechsler VLSI Design and Test Group Institute of Computer Science Department of Computer Science Albert-Ludwigs-University
More informationChecking Equivalence for Partial Implementations
Checking Equivalence for Partial Implementations Christoph Scholl Institute of Computer Science Albert Ludwigs University D 79110 Freiburg im Breisgau, Germany email: scholl@informatik.uni-freiburg.de
More informationWhat graphs can be efficiently represented by BDDs?
What graphs can be efficiently represented by BDDs? C. Dong P. Molitor Institute of Computer Science Martin-Luther University of Halle-Wittenberg Halle(Saale), D-62, Germany Abstract We have carried out
More informationA Data Parallel Algorithm for Boolean Function Manipulation
A Data Parallel Algorithm for Boolean Function Manipulation S. Gai, M. Rebaudengo, M. Sonza Reorda Politecnico di Torino Dipartimento di Automatica e Informatica Torino, Italy Abstract * This paper describes
More informationOn the Relation between SAT and BDDs for Equivalence Checking
On the Relation between SAT and BDDs for Equivalence Checking Sherief Reda 1 Rolf Drechsler 2 Alex Orailoglu 1 1 Computer Science & Engineering Department University of California, San Diego La Jolla,
More informationFunctional Decomposition of MVL Functions using Multi-Valued Decision Diagrams
Functional ecomposition of MVL Functions using Multi-Valued ecision iagrams Craig Files Rolf rechsler Marek A. Perkowski epartment of Electrical Engineering Institute of Computer Science Portland State
More informationBinary Decision Diagram with Minimum Expected Path Length
Binary Decision Diagram with Minimum Expected Path Length Yi-Yu Liu Kuo-Hua Wang TingTing Hwang C. L. Liu Department of Computer Science, National Tsing Hua University, Hsinchu 300, Taiwan Dept. of Computer
More informationL4: Binary Decision Diagrams. Reading material
L4: Binary Decision Diagrams de Micheli pp. 75-85 Reading material R. Bryant, Graph-ased algorithms for Boolean function manipulation, IEEE Transactions on computers, C-35, No 8, August 1986; can e downloaded
More informationTransistors NODES. Time (sec) No. of Nodes/Transistors
Binary Tree Structure for Formal Verication of Combinational ICs FATMA A. EL-LICY, and HODA S. ABDEL-ATY-ZOHDY Microelectronics System Design Laboratory Department of Electrical and Systems Engineering
More informationMathematik / Informatik
UNIVERSITAT TRIER Mathematik / Informatik Forschungsbericht Nr 98-01 Ordered Binary Decision Diagrams and Their Signicance in Computer-Aided Design of VLSI Circuits Christoph Meinel FB IV { Informatik
More informationAppears in LICS'97 2 Denition 2 A verte v in a BED denotes a Boolean function f v dened recursively as: If v is a terminal verte then f v = value(v).
Boolean Epression Diagrams (Appears in LICS'97) Henrik Reif Andersen and Henrik Hulgaard Department of Information Technology Building 344 Technical University of Denmark DK-2800 Lyngby Denmark e-mail:
More informationBoolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation. Jason Cong and Yean-Yow Hwang
Boolean Matching for Complex PLBs in LUT-based PAs with Application to Architecture Evaluation Jason Cong and Yean-Yow wang Department of Computer Science University of California, Los Angeles {cong, yeanyow}@cs.ucla.edu
More informationA Boolean Expression. Reachability Analysis or Bisimulation. Equation Solver. Boolean. equations.
A Framework for Embedded Real-time System Design? Jin-Young Choi 1, Hee-Hwan Kwak 2, and Insup Lee 2 1 Department of Computer Science and Engineering, Korea Univerity choi@formal.korea.ac.kr 2 Department
More informationSAT, SMT and QBF Solving in a Multi-Core Environment
SAT, SMT and QBF Solving in a Multi-Core Environment Bernd Becker Tobias Schubert Faculty of Engineering, Albert-Ludwigs-University Freiburg, 79110 Freiburg im Breisgau, Germany {becker schubert}@informatik.uni-freiburg.de
More informationB2 if cs < cs_max then cs := cs + 1 cs := 1 ra
Register Transfer Level VHDL Models without Clocks Matthias Mutz (MMutz@sican{bs.de) SICAN Braunschweig GmbH, Digital IC Center D{38106 Braunschweig, GERMANY Abstract Several hardware compilers on the
More informationMathematik / Informatik
.. UNIVERSITAT TRIER Mathematik / Informatik Forschungsbericht Nr. 94-03 Some Heuristics for Generating Tree-like FBDD Types Jochen Bern, Christoph Meinel, Anna Slobodova FB IV { Informatik, Universitat
More informationUnit 4: Formal Verification
Course contents Unit 4: Formal Verification Logic synthesis basics Binary-decision diagram (BDD) Verification Logic optimization Technology mapping Readings Chapter 11 Unit 4 1 Logic Synthesis & Verification
More informationDon't Cares in Multi-Level Network Optimization. Hamid Savoj. Abstract
Don't Cares in Multi-Level Network Optimization Hamid Savoj University of California Berkeley, California Department of Electrical Engineering and Computer Sciences Abstract An important factor in the
More informationBinary Decision Diagrams and Beyond: Enabling Technologies for Formal Verification
Binary Decision Diagrams and Beyond: Enabling Technologies for Formal Verification Randal E. Bryant Carnegie Mellon University Pittsburgh, PA 15213 Randy.Bryant@cs.cmu.edu http://www.cs.cmu/~bryant Abstract
More informationEfficient Hierarchical System Debugging for Property Checking
Efficient Hierarchical System Debugging for Property Checking Görschwin Fey Rolf Drechsler Institute of Computer Science, University of Bremen, 28359 Bremen, Germany {fey,drechsle}@informatik.uni-bremen.de
More informationModel Checking I Binary Decision Diagrams
/42 Model Checking I Binary Decision Diagrams Edmund M. Clarke, Jr. School of Computer Science Carnegie Mellon University Pittsburgh, PA 523 2/42 Binary Decision Diagrams Ordered binary decision diagrams
More informationInt. J. Advanced Networking and Applications 1430 Volume:03 Issue:06 Pages: (2012) ISSN :
1430 Binary Decision Diagrams and Its Variable Ordering for Disjoint Network Manoj Singhal Associate professor, Department of Information Technology, Accurate Institute of Management & Technology, Greater
More informationOutline. Computer Science 331. Information Hiding. What This Lecture is About. Data Structures, Abstract Data Types, and Their Implementations
Outline Computer Science 331 Data Structures, Abstract Data Types, and Their Implementations Mike Jacobson 1 Overview 2 ADTs as Interfaces Department of Computer Science University of Calgary Lecture #8
More informationCofactoring-Based Upper Bound Computation for Covering Problems
TR-CSE-98-06, UNIVERSITY OF MASSACHUSETTS AMHERST Cofactoring-Based Upper Bound Computation for Covering Problems Congguang Yang Maciej Ciesielski May 998 TR-CSE-98-06 Department of Electrical and Computer
More informationFormal Verification using Probabilistic Techniques
Formal Verification using Probabilistic Techniques René Krenz Elena Dubrova Department of Microelectronic and Information Technology Royal Institute of Technology Stockholm, Sweden rene,elena @ele.kth.se
More informationA Logically Complete Reasoning Maintenance System Based on a Logical Constraint Solver
A Logically Complete Reasoning Maintenance System Based on a Logical Constraint Solver J.C. Madre and O. Coudert Bull Corporate Research Center Rue Jean Jaures 78340 Les Clayes-sous-bois FRANCE Abstract
More informationK-terminal Network Reliability Evaluation Using Binary Decision Diagram
K-terminal Network Reliability Evaluation Using Binary Decision Diagram Mohammad Ghasemzadeh Computer Engineering Department Yazd University, Safa-ieh, Yazd, Iran m.ghasemzadeh@yazduni.ac.ir Christoph
More informationSymbol Tables Symbol Table: In computer science, a symbol table is a data structure used by a language translator such as a compiler or interpreter, where each identifier in a program's source code is
More informationUNIVERSITY OF DORTMUND
UNIVERSITY OF DORTMUND REIHE COMPUTATIONAL INTELLIGENCE COLLABORATIVE RESEARCH CENTER 531 Design and Management of Complex Technical Processes and Systems by means of Computational Intelligence Methods
More informationApplication of Binary Decision Diagram in digital circuit analysis.
Application of Binary Decision Diagram in digital circuit analysis. Jyoti Kukreja University of Southern California For Dr. James Ellison Abstract: Binary Decision Diagrams (BDDs) are one of the biggest
More informationGenerating All Solutions of Minesweeper Problem Using Degree Constrained Subgraph Model
356 Int'l Conf. Par. and Dist. Proc. Tech. and Appl. PDPTA'16 Generating All Solutions of Minesweeper Problem Using Degree Constrained Subgraph Model Hirofumi Suzuki, Sun Hao, and Shin-ichi Minato Graduate
More informationOrthogonal Hypergraph Drawing for Improved Visibility
Journal of Graph Algorithms and Applications http://jgaa.info/ vol. 10, no. 2, pp. 141 157 (2006) Orthogonal Hypergraph Drawing for Improved Visibility Thomas Eschbach Albert-Ludwigs-University Freiburg
More informationCompiling Bayesian Networks by Symbolic Probability Calculation Based on Zero-suppressed BDDs
Compiling Bayesian Networks by Symbolic Probability Calculation Based on Zero-suppressed BDDs Shin-ichi Minato Div. of Computer Science Hokkaido University Sapporo 6 814, Japan Ken Satoh National Institute
More informationBDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades
2762 IEICE TRANS. FUNDAMENTALS, VOL.E90 A, NO.12 DECEMBER 2007 PAPER Special Section on VLSI Design and CAD Algorithms BDD Representation for Incompletely Specified Multiple-Output Logic Functions and
More informationRobuCheck: A Robustness Checker for Digital Circuits
RobuCheck: A Robustness Checker for Digital Circuits Stefan Frehse Görschwin Fey André Sülflow Rolf Drechsler Institute of Computer Science 28359 Bremen, Germany {sfrehse,fey,suelflow,drechsle}@informatik.uni-bremen.de
More informationFUNCTIONAL DECOMPOSITION WITH APPLICATION TO FPGA SYNTHESIS
FUNCTIONAL DECOMPOSITION WITH APPLICATION TO FPGA SYNTHESIS Functional Decomposition with Application to FPGA Synthesis by Christoph Scholl Institute of Computer Science, Albert-Ludwigs-University, Freiburg
More informationAcceleration of SAT-based Iterative Property Checking
Acceleration of SAT-based Iterative Property Checking Daniel Große Rolf Drechsler Institute of Computer Science University of Bremen 28359 Bremen, Germany {grosse, drechsle}@informatik.uni-bremen.de Abstract
More informationABC basics (compilation from different articles)
1. AIG construction 2. AIG optimization 3. Technology mapping ABC basics (compilation from different articles) 1. BACKGROUND An And-Inverter Graph (AIG) is a directed acyclic graph (DAG), in which a node
More informationUsing Synthesis Techniques in SAT Solvers
1. Introduction Using Synthesis Techniques in SAT Solvers Rolf Drechsler Institute of Computer Science University of Bremen 28359 Bremen, Germany drechsle@informatik.uni-bremen.de Abstract In many application
More informationRevLib: An Online Resource for Reversible Functions and Reversible Circuits
RevLib: An Online Resource for Reversible Functions and Reversible Circuits Robert Wille 1 Daniel Große 1 Lisa Teuber 1 Gerhard W. Dueck 2 Rolf Drechsler 1 1 Institute of Computer Science, University of
More informationTradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter M. Bednara, O. Beyer, J. Teich, R. Wanka Paderborn University D-33095 Paderborn, Germany bednara,beyer,teich @date.upb.de,
More informationAbstract Relaxed balancing of search trees was introduced with the aim of speeding up the updates and allowing a high degree of concurrency. In a rela
Chromatic Search Trees Revisited Institut fur Informatik Report 9 Sabine Hanke Institut fur Informatik, Universitat Freiburg Am Flughafen 7, 79 Freiburg, Germany Email: hanke@informatik.uni-freiburg.de.
More informationPROJECTION MODELING SIMPLIFICATION MARKER EXTRACTION DECISION. Image #k Partition #k
TEMPORAL STABILITY IN SEQUENCE SEGMENTATION USING THE WATERSHED ALGORITHM FERRAN MARQU ES Dept. of Signal Theory and Communications Universitat Politecnica de Catalunya Campus Nord - Modulo D5 C/ Gran
More informationMETAPRIME, an Interactive Fault Tree Analyser
METAPRIME, an Interactive Fault Tree Analyser Olivier Coudert, Member IEEE Bull Corporate Research Center, Les Clayes-sous-bois Jean Christophe Madre, Member IEEE Bull Corporate Research Center, Les Clayes-sous-bois
More informationBinary Decision Diagrams and Symbolic Model Checking
Binary Decision Diagrams and Symbolic Model Checking Randy Bryant Ed Clarke Ken McMillan Allen Emerson CMU CMU Cadence U Texas http://www.cs.cmu.edu/~bryant Binary Decision Diagrams Restricted Form of
More informationType T1: force false. Type T2: force true. Type T3: complement. Type T4: load
Testability Insertion in Behavioral Descriptions Frank F. Hsu Elizabeth M. Rudnick Janak H. Patel Center for Reliable & High-Performance Computing University of Illinois, Urbana, IL Abstract A new synthesis-for-testability
More informationLazy Group Sifting for Efficient Symbolic State Traversal of FSMs
Lazy Group Sifting for Efficient Symbolic State Traversal of FSMs Hiroyuki Higuchi Fabio Somenzi Fujitsu Laboratories Ltd. University of Colorado Kawasaki, Japan Boulder, CO Abstract This paper proposes
More informationLecture1: Symbolic Model Checking with BDDs. Edmund M. Clarke, Jr. Computer Science Department Carnegie Mellon University Pittsburgh, PA 15213
Lecture: Symbolic Model Checking with BDDs Edmund M Clarke, Jr Computer Science Department Carnegie Mellon University Pittsburgh, PA 523 Temporal Logic Model Checking Specification Language: A propositional
More informationMotivation. CS389L: Automated Logical Reasoning. Lecture 5: Binary Decision Diagrams. Historical Context. Binary Decision Trees
Motivation CS389L: Automated Logical Reasoning Lecture 5: Binary Decision Diagrams Işıl Dillig Previous lectures: How to determine satisfiability of propositional formulas Sometimes need to efficiently
More informationBoolean Representations and Combinatorial Equivalence
Chapter 2 Boolean Representations and Combinatorial Equivalence This chapter introduces different representations of Boolean functions. It then discusses the applications of these representations for proving
More informationECE902 Virtual Machine Final Project: MIPS to CRAY-2 Binary Translation
ECE902 Virtual Machine Final Project: MIPS to CRAY-2 Binary Translation Weiping Liao, Saengrawee (Anne) Pratoomtong, and Chuan Zhang Abstract Binary translation is an important component for translating
More informationData Structure Optimization of AS_PATH in BGP
Data Structure Optimization of AS_PATH in BGP Weirong Jiang Research Institute of Information Technology, Tsinghua University, Beijing, 100084, P.R.China jwr2000@mails.tsinghua.edu.cn Abstract. With the
More informationEfficient Algorithm for Test Vector Decompression Using an Embedded Processor
Efficient Algorithm for Test Vector Decompression Using an Embedded Processor Kamran Saleem and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering University
More informationTaking One-to-one Mappings for Granted: Advanced Logic Design of Encoder Circuits
Taking One-to-one Mappings for Granted: Advanced Logic Design of Encoder Circuits Alwin Zulehner Robert Wille,2 Institute for Integrated Circuits, Johannes Kepler University, Linz, Austria 2 Cyber-Physical
More informationBinary Decision Diagrams (BDD)
Binary Decision Diagrams (BDD) Contents Motivation for Decision diagrams Binary Decision Diagrams ROBDD Effect of Variable Ordering on BDD size BDD operations Encoding state machines Reachability Analysis
More informationAn Embedded Wavelet Video Coder. Using Three-Dimensional Set. Partitioning in Hierarchical Trees. Beong-Jo Kim and William A.
An Embedded Wavelet Video Coder Using Three-Dimensional Set Partitioning in Hierarchical Trees (SPIHT) Beong-Jo Kim and William A. Pearlman Department of Electrical, Computer, and Systems Engineering Rensselaer
More informationLoughborough University Institutional Repository. IEEE Transactions on Reliability, 51(3), pp
Loughborough University Institutional Repository Choosing a heuristic for the fault tree to binary decision diagram conversion, using neural networks This item was submitted to Loughborough University's
More informationTwiddle Factor Transformation for Pipelined FFT Processing
Twiddle Factor Transformation for Pipelined FFT Processing In-Cheol Park, WonHee Son, and Ji-Hoon Kim School of EECS, Korea Advanced Institute of Science and Technology, Daejeon, Korea icpark@ee.kaist.ac.kr,
More informationFIXED POLARITY REED-MULLER MINIMIZATION OF INCOMPLETELY SPECIFIED BOOLEAN FUNCTIONS BASED ON INFORMATION ESTIMATIONS ON DECISION TREES *
Proceedings of the IAPR International Conference on Pattern Recognition and Information Processing, PRIP 99, Minsk, Belarus, 999, pp. 97-206 FIXED POLARITY REED-MULLER MINIMIZATION OF INCOMPLETELY SPECIFIED
More informationAn Embedded Wavelet Video. Set Partitioning in Hierarchical. Beong-Jo Kim and William A. Pearlman
An Embedded Wavelet Video Coder Using Three-Dimensional Set Partitioning in Hierarchical Trees (SPIHT) 1 Beong-Jo Kim and William A. Pearlman Department of Electrical, Computer, and Systems Engineering
More informationFunctional extension of structural logic optimization techniques
Functional extension of structural logic optimization techniques J. A. Espejo, L. Entrena, E. San Millán, E. Olías Universidad Carlos III de Madrid # e-mail: { ppespejo, entrena, quique, olias}@ing.uc3m.es
More informationF-Soft: Software Verification Platform
F-Soft: Software Verification Platform F. Ivančić, Z. Yang, M.K. Ganai, A. Gupta, I. Shlyakhter, and P. Ashar NEC Laboratories America, 4 Independence Way, Suite 200, Princeton, NJ 08540 fsoft@nec-labs.com
More informationDIGITAL DESIGN TECHNOLOGY & TECHNIQUES
DIGITAL DESIGN TECHNOLOGY & TECHNIQUES CAD for ASIC Design 1 INTEGRATED CIRCUITS (IC) An integrated circuit (IC) consists complex electronic circuitries and their interconnections. William Shockley et
More informationTable : IEEE Single Format ± a a 2 a 3 :::a 8 b b 2 b 3 :::b 23 If exponent bitstring a :::a 8 is Then numerical value represented is ( ) 2 = (
Floating Point Numbers in Java by Michael L. Overton Virtually all modern computers follow the IEEE 2 floating point standard in their representation of floating point numbers. The Java programming language
More informationSet Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis
Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis Amit Goel Department of ECE, Carnegie Mellon University, PA. 15213. USA. agoel@ece.cmu.edu Randal E. Bryant Computer
More informationsuch internal data dependencies can be formally specied. A possible approach to specify
Chapter 6 Specication and generation of valid data unit instantiations In this chapter, we discuss the problem of generating valid data unit instantiations. As valid data unit instantiations must adhere
More informationDefect Tolerance in VLSI Circuits
Defect Tolerance in VLSI Circuits Prof. Naga Kandasamy We will consider the following redundancy techniques to tolerate defects in VLSI circuits. Duplication with complementary logic (physical redundancy).
More informationHW/SW Co-Verification of a RISC CPU using Bounded Model Checking
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking Daniel Große Ulrich Kühne Rolf Drechsler Institute of Computer Science University of Bremen 28359 Bremen, Germany {grosse, ulrichk, drechsle}@informatik.uni-bremen.de
More informationHeap-on-Top Priority Queues. March Abstract. We introduce the heap-on-top (hot) priority queue data structure that combines the
Heap-on-Top Priority Queues Boris V. Cherkassky Central Economics and Mathematics Institute Krasikova St. 32 117418, Moscow, Russia cher@cemi.msk.su Andrew V. Goldberg NEC Research Institute 4 Independence
More informationBi-Partition of Shared Binary Decision Diagrams
Bi-Partition of Shared Binary Decision Diagrams Munehiro Matsuura, Tsutomu Sasao, on T Butler, and Yukihiro Iguchi Department of Computer Science and Electronics, Kyushu Institute of Technology Center
More informationResearch Collection. Formal background and algorithms. Other Conference Item. ETH Library. Author(s): Biere, Armin. Publication Date: 2001
Research Collection Other Conference Item Formal background and algorithms Author(s): Biere, Armin Publication Date: 2001 Permanent Link: https://doi.org/10.3929/ethz-a-004239730 Rights / License: In Copyright
More informationSequential Circuit Test Generation Using Decision Diagram Models
Sequential Circuit Test Generation Using Decision Diagram Models Jaan Raik, Raimund Ubar Department of Computer Engineering Tallinn Technical University, Estonia Abstract A novel approach to testing sequential
More informationSymbolic Manipulation of Boolean Functions Using a Graphical Representation. Abstract
Symbolic Manipulation of Boolean Functions Using a Graphical Representation Randal E. Bryant 1 Dept. of Computer Science Carnegie-Mellon University Abstract In this paper we describe a data structure for
More informationEdge detection based on single layer CNN simulator using RK6(4)
Edge detection based on single layer CNN simulator using RK64) Osama H. Abdelwahed 1, and M. El-Sayed Wahed 1 Mathematics Department, Faculty of Science, Suez Canal University, Egypt Department of Computer
More informationSEPP: a New Compact Three-Level Logic Form
SEPP: a New Compact Three-Level Logic Form Valentina Ciriani Department of Information Technologies Università degli Studi di Milano, Italy valentina.ciriani@unimi.it Anna Bernasconi Department of Computer
More informationA BIST Approach to. count for an n-input circuit under test (CUT) is 2 n (2 n 1), exhaustive TPG methods are limited to
A BIST Approach to Delay Fault Testing with Reduced Test Length Bernd Wurth Institute of Electronic Design Automation Technical University of Munich 89 Munich, Germany Karl Fuchs Siemens Mobile Radio Networks
More informationNetwork Reliability Computation by using Different Binary Decision Diagrams
Network Reliability Computation by using Different Binary Decision Diagrams Manoj Singhal 1, R. K. Chauhan 2, Girish Sharma 3 1 Asso. Prof., Deptt. Of MCA, Academy of Business and Engineering Sciences,
More informationThe Parallelization of Binary Decision Diagram operations for model checking
The Parallelization of Binary Decision Diagram operations for model checking Tom van Dijk 24 April 2012 Master s thesis Department of Computer Science Graduation committee: Prof.dr. J.C. van de Pol Dr.
More informationFormal Verification Techniques for Digital Systems
&CHAPTER 1 Formal Verification Techniques for Digital Systems MASAHIRO FUJITA, SATOSHI KOMATSU, and HIROSHI SAITO University of Tokyo, Japan 1.1 INTRODUCTION In deep submicron technology, a large and complex
More informationBinary Decision Diagrams
Binary Decision Diagrams 2-CS-626- Formal Verification Department of Computer Science University of Cincinnati Introduction Binary Decision Diagrams (BDD) [, 8] are a general, graphical representation
More informationA Bintree Representation of Generalized Binary. Digital Images
A intree Representation of Generalized inary Digital mages Hanspeter ieri gor Metz 1 inary Digital mages and Hyperimages A d-dimensional binary digital image can most easily be modelled by a d-dimensional
More informationHardware Modeling using Verilog Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Hardware Modeling using Verilog Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture 01 Introduction Welcome to the course on Hardware
More informationreasonable to store in a software implementation, it is likely to be a signicant burden in a low-cost hardware implementation. We describe in this pap
Storage-Ecient Finite Field Basis Conversion Burton S. Kaliski Jr. 1 and Yiqun Lisa Yin 2 RSA Laboratories 1 20 Crosby Drive, Bedford, MA 01730. burt@rsa.com 2 2955 Campus Drive, San Mateo, CA 94402. yiqun@rsa.com
More informationBuildingCircuitsfrom Relations
BuildingCircuitsfrom Relations James H. Kukula and Thomas R. Shiple 2 Synopsys, Inc., Beaverton, OR. kukula@synopsys.com 2 Synopsys, Inc., Mountain View, CA. shiple@synopsys.com Abstract. Given a Free
More informationA Low-Cost Correction Algorithm for Transient Data Errors
A Low-Cost Correction Algorithm for Transient Data Errors Aiguo Li, Bingrong Hong School of Computer Science and Technology Harbin Institute of Technology, Harbin 150001, China liaiguo@hit.edu.cn Introduction
More informationCarry-Free Radix-2 Subtractive Division Algorithm and Implementation of the Divider
Tamkang Journal of Science and Engineering, Vol. 3, No., pp. 29-255 (2000) 29 Carry-Free Radix-2 Subtractive Division Algorithm and Implementation of the Divider Jen-Shiun Chiang, Hung-Da Chung and Min-Show
More informationON AN OPTIMIZATION TECHNIQUE USING BINARY DECISION DIAGRAM
ON AN OPTIMIZATION TECHNIQUE USING BINARY DECISION DIAGRAM Debajit Sensarma # 1, Subhashis Banerjee #1, Krishnendu Basuli #1,Saptarshi Naskar #2, Samar Sen Sarma #3 #1 West Bengal State University, West
More informationBOOSTER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstraction
BOOSTER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstraction Peer Johannsen Siemens AG, Corporate Technology, Design Automation, CT SE 4 81730 Munich, Germany peer.johannsen@mchp.siemens.de
More informationModel Checking VHDL with CV
Model Checking VHDL with CV David Déharbe 1, Subash Shankar 2, and Edmund M. Clarke 2 1 Universidade Federal do Rio Grande do Norte, Natal, Brazil david@dimap.ufrn.br 2 Carnegie Mellon University, Pittsburgh,
More informationDesign of a Totally Self Checking Signature Analysis Checker for Finite State Machines
Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines M. Ottavi, G. C. Cardarilli, D. Cellitti, S. Pontarelli, M. Re, A. Salsano Department of Electronic Engineering University
More informationA Short Summary of Javali
A Short Summary of Javali October 15, 2015 1 Introduction Javali is a simple language based on ideas found in languages like C++ or Java. Its purpose is to serve as the source language for a simple compiler
More informationECE 637 Integrated VLSI Circuits. Introduction. Introduction EE141
ECE 637 Integrated VLSI Circuits Introduction EE141 1 Introduction Course Details Instructor Mohab Anis; manis@vlsi.uwaterloo.ca Text Digital Integrated Circuits, Jan Rabaey, Prentice Hall, 2 nd edition
More informationDiagnostic Testing of Embedded Memories Using BIST
Diagnostic Testing of Embedded Memories Using BIST Timothy J. Bergfeld Dirk Niggemeyer Elizabeth M. Rudnick Center for Reliable and High-Performance Computing, University of Illinois 1308 West Main Street,
More informationAn Adaptive Prioritized ε-preferred Evolutionary Algorithm for Approximate BDD Optimization
An Adaptive Prioritized ε-preferred Evolutionary Algorithm for Approximate BDD Optimization Saeideh Shirinzadeh 1 Mathias Soeken 2 Daniel Große 1,3 Rolf Drechsler 1,3 1 Department of Mathematics and Computer
More informationPARALLEL PERFORMANCE DIRECTED TECHNOLOGY MAPPING FOR FPGA. Laurent Lemarchand. Informatique. ea 2215, D pt. ubo University{ bp 809
PARALLEL PERFORMANCE DIRECTED TECHNOLOGY MAPPING FOR FPGA Laurent Lemarchand Informatique ubo University{ bp 809 f-29285, Brest { France lemarch@univ-brest.fr ea 2215, D pt ABSTRACT An ecient distributed
More informationBehavior models and verification Lecture 6
Behavior models and verification Lecture 6 http://d3s.mff.cuni.cz Jan Kofroň, František Plášil Model checking For a Kripke structure M = (S, I, R, L) over AP and a (state based) temporal logic formula
More informationAustralian Journal of Basic and Applied Sciences. Timing Analysis on Min-term Based Tabular Method for BDD Manipulations
AENSI Journals Australian Journal of Basic and Applied Sciences Journal home page: www.ajbasweb.com Timing Analysis on Min-term Based Tabular Method for BDD Manipulations 1 S. Deivanai, 2 Dr. K. Thanushkodi,
More informationNon-Enumerative Path Delay Fault Diagnosis
Non-Enumerative Path Delay Fault Diagnosis Saravanan Padmanaban Spyros Tragoudas Department of Electrical and Computer Engineering Southern Illinois University Carbondale, IL 6901 Abstract The first non-enumerative
More information