A Data Parallel Algorithm for Boolean Function Manipulation

Transcription

1 A Data Parallel Algorithm for Boolean Function Manipulation S. Gai, M. Rebaudengo, M. Sonza Reorda Politecnico di Torino Dipartimento di Automatica e Informatica Torino, Italy Abstract * This paper describes a data-parallel algorithm for boolean function manipulation. The algorithm adopts Binary Decision Diagrams (BDDs), which are the state-of-the-art approach for representing and handling boolean functions. The algorithm is well suited for SIMD architectures and is based on distributing BDD nodes to the available Processing Elements and traversing BDDs in a breadth-first manner. An improved version of the same algorithm is also presented, which does not use virtual processors. A prototypical package has been implemented and its behavior has been studied with two different applications. In both cases the results show that the approach exploits well the parallel hardware by effectively distributing the load; thanks to the limited CPU time required and to the great amount of memory available, it can solve problems that can not be faced with by conventional architectures. 1. Introduction Efficient techniques for boolean function manipulation are a key point in many areas, such as digital logic design and testing, artificial intelligence and combinatorics. The state-of-the-art approach to the problem is based on Binary Decision Diagrams (BDDs) [Brya92]. A number of results have been published [BRBr90], and BDDs are now used in several commercial tools. However, the size and complexity of functions sometimes carry BDDs beyond any acceptable limit in terms of memory requirements, while the CPU time for their management is also unaffordable. * This work has been partially supported by grants of CNR, the Italian National Research Council (Progetto Finalizzato Sistemi Informatici e Calcolo Parallelo). Contact address: Matteo Sonza Reorda, Dipartimento di Automatica e Informatica, Politecnico di Torino, Corso Duca degli Abruzzi 24, I Torino (Italy), sonza@polito.it The use of massively parallel SIMD architectures in this area is extremely attractive, as they provide the CPU power and the memory needed to store and manage very large BDDs. On the other side, to the best of our knowledge no methods have been proposed up to now to exploit MIMD or distributed systems for BDD handling, as they are difficult to partition among the processors, and their size prevents their transmission to be done in acceptable times. Previous works on parallel algorithms for BDDs dealt with vector [OIYa91] or shared-memory architectures [KiCl90]: in the former case the parallel environment is quite different from the one we address to, in the latter the experimental results published were still very poor. In [CGSR92] a data parallel algorithm was proposed; the results obtained with its implementation on a CM-200 were reported in [CGRS94]. Based on this experience, an improved version of the same algorithm is described in this paper. The new version introduces significant improvements as far as the algorithm and the implementation issues are considered. The performance analysis on the previous work revealed that the virtual processor mechanism supported by the Connection Machine environment was a critical problem. The new version does not exploit this mechanism, and significantly improves the efficiency thanks to an optimized processor utilization. The algorithm has been implemented on a MasPar system, and a prototypical BDD package has been written, which provides the basic procedures for boolean function manipulation. Two sample applications have been developed using it, and the results have been compared with the ones gathered on mono-processor platforms. The main advantage of the parallel package is the ability to deal with very large problems, which could not be tackled by conventional architecture due to the unacceptable memory and CPU time requirements.

2 Section 2 outlines the basic principles concerning BDDs; Section 3 presents the parallel algorithm for the Apply operation. Section 4 identifies some critical points of the previous version of the algorithm and describes the improved techniques adopted in the new version; the two sample applications and the experimental results are presented in Section 5, and Section 6 draws some conclusions. 2. BDDs Let us consider a boolean function f(x 1, x 2,..., x n ); the input variables are ordered according to their index (x 1 x 2... x n ). A binary tree can be built from f by recursively applying the Shannon [Brow90] expansion rule: f(x, x,..., x ) = x f(1, x,..., x ) n 1 2 n x f(0, x,..., x ) 1 2 n where and + are the and and or operators, respectively. According to this rule, the root node is associated with the first variable (x 1 ), and its two sons are the trees corresponding to the functions f(1, x 2,..., x n ) and f(0, x 2,..., x n ) respectively. These functions are often referred to as positive and negative cofactors of f with respect to x 1. The expansion can recursively be applied to the cofactors using x 2 as the splitting variable, and repeated for all the variables. Generally speaking, a variable is associated with each node, and its sons represent the two cofactors with respect to the variable. The leaves of the tree correspond to special nodes called terminals representing the constant values 1 and 0. The tree representing the boolean function is likely to contain identical sub-trees: for sake of efficiency, it is convenient to avoid replication by storing only one subtree and forcing all parents to point to it. Only two leaves are thus contained in any tree (corresponding to the constants 1 and 0). The result is no longer a tree, but a Directed Acyclic Graph (DAG), usually called a Binary Decision Diagram. It is often of interest to consider sets of boolean functions. Since several BDDs must be handled at a time, it is advantageous that they share common parts. The result is a DAG whose input nodes are the heads of the BDDs. Further improvements can be obtained by removing nodes whose sons are coincident. BDDs having neither identical sub-trees nor any node with coincident sons are canonical, i.e., they represent a boolean function in a unique fashion, once the ordering of input variables has been decided. They are usually referred to as Reduced Ordered BDDs (ROBDDs) [BRBr90]. Fig. 1 shows the ROBDD for the function f = acd + abc + abcd, assuming the variable ordering a < b < c < d. 0 0 d b 1 0 c a 1 c d Fig. 1: A BDD example According to [Brya92], let us call Apply the basic operation for manipulating boolean functions represented as BDDs; the Apply input parameters are two BDDs and a logical operator; the output parameter is the result BDD. The Apply procedure can be easily implemented in a recursive way by using the following expression, derived from the Shannon expansion: Apply ( f, f, op) = x Apply ( f, f, op) + x Apply ( f, f, op) f 1 2 i 1 xi = 0 2 xi = 0 i 1 xi = 1 2 xi = 1 where op is any boolean operator. To prevent the same binary operation from being computed more than once on the same couple of BDD nodes, an internal data structure records all the already computed functions, each identified by the operator and 1

3 the identifiers of the two root nodes of the operand BDDs. For each function, the pointer to the root node of the resulting BDD is stored. The structure is usually implemented as a hash table (Computed Table), because the number of different entries in the data structure is as high as n 2 m, where n is the number of BDD nodes and m is the number of operators supported by Apply. The complexity of the Apply operation is proportional to the size (in terms of number of nodes) of the resulting BDD, whose upper bound is given by the product of the sizes of the two operand ones. 3. The Parallel Algorithm This section describes the parallel algorithm implementing the Apply operation; other operations on BDDs, like Reduce, ITE, or Smooth, can be quite easily implemented following the same approach. The target architecture is a massively parallel SIMD system. Each PE is assumed to be able to access the data in its local memory, and (at a higher cost) the ones in all other local memories; the Concurrent Read - Exclusive Write (CREW) model is assumed. The basic idea behind the parallel algorithm is to distribute the data structures among the PEs and let each PE work on its local data Data Distribution The algorithm uses two data structures: the set of BDD nodes the Hash Table. The former data structure is distributed among the PEs so that each PE stores a BDD node: the case when the number of BDD nodes is greater than the number of PEs will be considered in the next Section. The Hash Table data structure is discussed in Section Activity Distribution In the mono-processor version, the Apply procedure works on a couple of nodes in the two operand BDDs; it first checks whether the corresponding function has been already computed by accessing to the Computed Table. If not, the procedure creates a new node and calls itself recursively on the two son couples. Each call is thus composed of two phases: a processing phase, in which a couple is evaluated, a search is performed in the hash table, and a new node is possibly allocated; a scheduling phase, in which up to two new couples are scheduled for being processed during the following steps. The parallel algorithm presented in [CGSR92] is based on the iteration of the same two phases. However, sets of couples are considered in parallel: the former phase processes all the scheduled couples together, and the latter schedules the couples for the following step (Fig. 2). Each couple to be processed is assigned to a PE, and the same PE will store the possible new node. For each scheduled couple the PE performs the following operations: evaluation; access to the hash table; possible allocation of a new node in the local memory of the PE; possible scheduling of new couples and choice of the PEs in charge of their processing. The process starts when a PE is charged of processing the couple corresponding to the two root nodes in the operand BDDs. schedule the root couple; while there are scheduled couples { for all the scheduled couples in parallel { evaluate the couple; check whether the corresponding function has already been evaluated; if yes make the father pointing to the existing node; else { allocate a new node; make the father pointing to the new node; schedule the two son couples; } } } Fig. 2: Pseudo-code for the parallel algorithm. 4. Improved Algorithm The data parallel algorithm described so far was implemented in C/Paris and several experiments were performed on a CM-200 to assess its effectiveness [CGRS94]. The results showed that the efficiency was greatly limited by the low parallelism obtained, in terms of average percent of active PEs with respect to their total number. This was mainly due to the fact that we used the mechanism of virtual processors supported by the CM system. A number of virtual processors equal to the maximum required number of BDD nodes was allocated; because this number was often of the

4 order of one million, a high value of VP-ratio (the ratio between the number of virtual and real processors) was obtained. As a consequence, a significant slow-down factor was imposed to the system during its whole activity, no matter how large the real parallelism was at each computational step. To overcome this problem a new version of the algorithm has been devised, which avoids the use of the virtual processor mechanism. The solutions adopted for some critical points of the algorithm will now be described Distribution of BDD nodes As the number of PEs is generally lower than the number of BDD nodes, each PE stores a subset of the BDD nodes; a vector (named BDD vector) is statically allocated in each PE and is incrementally filled with the BDD nodes when they are created. Each BDD node is univocally identified by the number of the PE in whose memory it is recorded, and by the index of the slot it occupies in the BDD vector. To optimize the use of both memory and processors, allocation of BDD nodes should be uniform among the PEs. Each new node is allocated in the local memory of the same PE that processed the couple the node derives from. Therefore, the distribution of the (possible) new nodes is actually performed when the distribution of the scheduled couples is done. When a PE is required for a couple, a random function is called, and the returned value is used to select a PE. If at least one free slot exists in its BDD vector, the couple is assigned to the PE; otherwise, the function is called again, until a PE with a free slot is found. A maximum number of allowed retries is introduced to cope with the no more available memory condition. Because every PE can process just one couple at a time, a FIFO buffer is introduced in each PE, which records the couples it must process. At each step, every PE extracts a couple from the buffer and processes it. As a consequence, all the PEs which have a non empty buffer are active at a given step. This guarantees a much larger parallelism than was achieved with the virtual processor mechanism. Note that with the previous approach, processing was based on a level-by-level strategy: all the couples scheduled during step i were processed before the couples scheduled at step i+1. With the new approach processing evolves in a more flexible manner, as at each step each PE processes a couple extracted from its buffer The parallel hash table During the couple processing, the PEs make a parallel access to the Hash Table, each looking for a node. The Hash Table is implemented in a distributed fashion, so that the stored items are recorded in the PEs memories, and the PEs are in charge of receiving and processing queries. Among the many parallel hash techniques [YeBa92], the approach which best fits with our requirements is the one known as Local Chaining: the hash function returns a value between 1 and m, being m the number of PEs. Each PE stores the items whose hash value corresponds to its index; a vector is statically allocated on each PE for this purpose. When a search must be performed, the hash function is evaluated, the selected PE scans the local vector, and possibly returns the found item: the cost of this operation thus depends on the maximum number of elements stored in a single PE. 5. Experimental Results A prototypical implementation of the algorithm has been written in the MPL language and now runs on a MasPar MP-2 with 16K PEs and a 64Kbyte RAM for each PE. The code size is about 2,000 lines. We also implemented the Reduce and Garbage procedures, which transforms a BDD into a ROBDD, and deletes the unused nodes from the data structures, respectively. Vectors of boolean functions (corresponding to BDD forests) are also supported. The whole package has been used for developing two applications for which experimental data are also available for monoprocessor systems, thus allowing a comparative evaluation of its effectiveness Computing the Output Functions of a Combinational Circuit The boolean functions implemented by the outputs of a combinational circuit are computed and represented as BDDs. A subset of the standard set of combinational [BrFu85] and sequential [BBKo89] circuits used for benchmarking in the test field is used: for the sequential circuits, the combinational part is extracted. The present version of the tool computes the output function for each gate level by level starting from the inputs: all the boolean functions implemented by the gates at the same level of the circuit are computed in parallel with a single call to the Apply procedure. The results are reported in Tab. 1, where the

5 final and maximum number of BDD nodes is reported, together with the CPU time required. Circuit CPU Time BDD Nodes [s] MAX FINAL c ,364 29,839 c ,800 71,611 c ,488 14,811 c , ,655 c ,338 19,527 c ,931,311 5,596,917 c , ,311 c ,238 75,480 s ,254,104 8,417,775 Tab. 1: Experimental results for the first application Tab. 1 shows that: the CPU times do not explode when the BDD size increases, and remain acceptable even when a very large number of nodes is considered; the CPU times required are generally much smaller than the ones reported in the literature for mono-processor architectures [BRBr90]; however, a strict comparison is difficult, because the BDD size, and thus the CPU time required, are strongly dependent on the variable ordering, which is seldom provided; some circuits can not be dealt with by monoprocessor architectures due to their limits in the memory size: to the best of our knowledge, this is the first time that the output functions for circuits C2670 and S5378 have been computed using BDDs; our package is able to handle a number of BDD nodes at least one order of magnitude greater than the serial packages do; a comparison can be done with respect to the results we obtained with the previous version of our tool when the same ordering for the input variables was used. Tab. 2 reports the CPU time required to solve the same problems on a 10 MHz CM-200 with 1 Mbit for PE and a MP-2 with 64Kbyte for PE; both machines were equipped with 16K PEs. Differences are due in part to the different characteristics of the hardware, in part to the improvements introduced in the algorithm: in particular, we experimentally verified that the average number of active PEs was much greater in the new version of the tool, which is thus able to exploit in a better way the available hardware. Circuit CPU Time [s] CM-200 MP-2 c c c c c c c c s Tab. 2: CPU time comparison between the previous versions of the tool 5.2. Computing the Maximum Clique in a Graph Many problems in Electronic CAD (especially in the synthesis and test areas) require the computation of the maximum clique in a graph. An algorithm for performing this computation using BDDs has been recently proposed in [CPSR93]. The approach is based on using characteristic functions to represent sets of subsets: we will first give a short overview of the method. Given a set of n elements Q, and being B={0,1}, any subset S Q can be easily mapped to a point in B n : each element q i Q is represented by a boolean variable x i getting values in B; each combination of values for the variables x 1,..., x n identifies the subset of Q composed by just the elements corresponding to the variables set to 1. Any set T of subsets of Q can now be represented by a characteristic function f:b n B which returns the value 1 iff its inputs x 1,..., x n represent an element of T. A boolean expression can be defined for the characteristic function f CCC of the set of all the Completely Connected Components (CCCs) of a graph V. Denoting by n the number of vertices in V, and by x 1,..., x n the boolean variables associated with the vertices, the function f CCC : B n B is defined as follows: f CCC(x 1,..., x n ) = (x i x j) where Π denotes the logical and operator extended to all the missing edges e i,j between any two nodes v i, v j

6 in the graph. The function returns the value 1 iff the input is a CCC. Once f CCC has been computed, determining the maximum clique in the graph means finding the maximum-cost satisfying assignment for f CCC, where the cost of each assignment is the number of variables set to 1 in it. As an example, let us consider the graph of Fig. 4; the function f CCC is: f = x x x x = CCC x + x x3 The maximum-cost satisfying assignment for such function is x 2 x 3 x 4 : the maximum clique in the graph is thus composed of the vertices v 2, v 3 and v 4. [CPSR93] describes a tool which implements the approach using BDDs for representing boolean functions. The tool was implemented in C and runs on a Sun 4/75. It was experimented on random graphs of different density: the limiting factor was again the memory size. The same algorithm has been implemented using the data-parallel package, and the results have been reported in Tab. 3, together with the ones reported in [CPSR93]. Only the biggest problems that can be solved on the mono-processor and parallel systems are considered Fig. 3: A graph example The results show that when a comparison is possible with the mono-processor architecture, our algorithm is able to reduce the CPU time required by a factor of about 10; on the other side, the parallel approach allowed us to solve problems that could not be tackled on standard platforms. 6. Conclusions Boolean function manipulation using BDDs requires the availability of a very large amount of memory, and is hard to implement on MIMD architectures, due to the difficulties in partitioning the data and distributing the associated work among the processors. On the other side, SIMD architectures are particularly suited, as they directly exploit the data-parallelism of the problem. The paper presents a data-parallel algorithm for boolean expression manipulation using BDDs. The approach is based on distributing the BDD nodes among the PEs; an effective technique is introduced to balance the load and guarantee that a high percentage of PEs is active. The improvements with respect to a previous version of the algorithm which used the virtual processor mechanism have been discussed. A prototypical system has been implemented on a MasPar system: two sample applications have been implemented to verify its effectiveness. The results show that the algorithm can reduce the CPU time required with respect to mono-processor systems and, more important, that it exploits the great amount of memory available on massively parallel systems. The package handles a number of BDD nodes at least 10 times greater than most serial packages do, and it is therefore able to solve problems that could not be handled otherwise. 7. Acknowledgments The authors wish to thank Flavio Bianchi for implementing the improved algorithm on the MasPar system. We are also very grateful to Prof. Roberto Vaccaro of the CNR-IRSIP, Napoli, Italy, and Dr. Jonathan Becher of MasPar Co., for access to MasPar systems existing at their institutions. 8. References [BBKo89] F. Brglez, D. Bryant, K. Kozminski: Combinational profiles of sequential benchmark circuits, IEEE Int. Symp. on Circuits And Systems, 1989, pp [BRBr90] K.S. Brace, R.L. Rudell, R.E. Bryant: Efficient Implementation of a BDD Package, 27 th ACM/IEEE Design Automation Conf., 1990, [Brya92] pp R.E. Bryant: Symbolic Boolean Manipulation with Ordered Binary-Decision Diagrams, ACM Computing Surveys, Vol. 24, No. 3, September 1992, pp [BrFu85] F. Brglez, H. Fujiwara: A neutral netlist of 10 combinational benchmark circuits and a target

7 [Brow90] [CGSR92] [CPSR93] [CGRS94] [KiCl90] [OIYa91] [YeBa92] translator in Fortran, IEEE Int. Symp. on Circuits And Systems, June 1985 F. M. Brown: Boolean Reasoning: The Logic of Boolean Equations, Kluwer, Boston (MA), USA, 1990 G. Cabodi, S. Gai, M. Sonza Reorda: Boolean Function Manipulation on Massively Computers, 4th IEEE Symposium on the Frontiers of Massively Parallel Computation, October 1992, pp F. Corno, P. Prinetto, M. Sonza Reorda: Finding the Maximum Clique in a Graph using BDDs, IEEE Int. Conf. on VLSI and CAD, November 1993, pp G. Cabodi, S. Gai, M. Rebaudengo, M. Sonza Reorda: A Data-Parallel Approach to Boolean Function Manipulation using BDDs, IEEE/Euromicro Conf. on Massively Parallel Comp. Systems, May 1994 S. Kimura, E.M. Clarke: A Parallel Algorithm for Constructing Binary Decision Diagrams, IEEE Int. Conf. on Comp. Design, 1990, pp H. Ochi, N. Ishiura, S. Yajima: Breadth-first Manipulation of SBDD of Boolean Functions for Vector Processing, 28 th ACM/IEEE Design Automation Conference, 1991, pp I-L. Yen, F. Bastani: Hash Table in Massively Parallel Systems, IPPS92: IEEE International Parallel Processing Symposium, April 1992, pp #vertices density max clique BDD nodes CPU time [s] % MAX Sun MP , ,787, ,047, ,064, ,631, ,858, ,602 1, ,131, ,127 62,729 4, ,026,730-5,280 Tab. 3: Experimental results for the second application

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