Intel PerfMon Performance Monitoring Hardware

Transcription

1 Intel PerfMon Performance Monitoring Hardware Overview

2 PerfMon Basics PerfMon is hardware throughout the silicon available through registers to tools to facilitate several system/application usages: compiler analysis workload characterization performance tuning and debug Two counting paradigms used Global/absolute count Sampling on overflow Previous incompatibility among processor families has limited its value First introduced on the Pentium processor Model-specific changes added to P6, Pentium 4, and Xeon processors Intel Core Solo processors were the first to support Architectural PerfMon Arch PerfMon ensures all base analysis capabilities across all Intel processors

3 Performance Tuning Methodology Top Down Iterative Approach is used at every level Top Down System Level Process/Memory Utilization Network Disk & IO Context Switches/Paging/System Calls Application Level Locks Heaps Parallelism / Execution Threads APIs Microarchitecture Level (PerfMon) Processor Stalls Branch Prediction Data and code alignment Glass Jaws PerfMon is hardware behind all microarchitecture level tuning/analysis vmstat APImon *Many customer & open source tools MS PerfMon Quantify xif NetMon VTune PTU

4 Intel Tools PerfMon based analysis tools methodology: prototype methodologies are released in free analysis tools followed by full production support in releases of Intel Vtune Analyzer! Prototype tools whatif.intel.com Available today PTU (Performance Tuning Utility) Much of the All New VTune Analyzer is based on PTU. xif (platform x Issue Finder microarchitecture focus) Beta is due out next week. Production is due early July internally. Production externally is due in September.

5 x Issue Finder (xif) Analyzer for Microarchitecture Tuning xif breaks down code into streams Each stream is analyzed against best case performance using Intel preset platform Issue List to prioritize tuning efforts to find: Locks & Waits Where is my program waiting, over using system calls? Front-End Issues Find the compiler opportunities Cache analysis & false sharing Memory/Data Stalling Branching issues More Code/Data Layout, 5

6 Market Leading Software Tools Optimize Multicore Performance Focus tool utilizing PerfMon Hardware

7 Intel s Piersol HE Profiler All New VTune Analyzer New User Interface Next Generation Collection Technology Integrated Threading Timeline Product Features Supported Environments Availability Intel s HE Studio Static Security Analysis, Dynamic Memory and Thread Analysis C/C++, Fortran and.net Windows, Linux, Microsoft Visual Studio 2005, 2008, 2010 Q4/2010

8 Intel s Piersol HE Profiler Performance Analysis System Windows* & Linux* GUI, Command line, Visual Studio integration No special compilers or recompile Setup Presets Simplify Setup Collect Multiple Data Collectors Analyze Multiple Views Simplify Analysis

9 Intel s Piersol HE Profiler Preset Experiments Simplify Setup Basic Presets Run these first Hotspot Where is my app spending time? Concurrency Where is my concurrency poor? Locks & Waits Where is my program waiting? Advanced Presets Get more detail Tuning Decision Tree Find the opportunities Cache analysis & false sharing Branching issues More Structural hazards, Custom Full Control All events Detailed micro-architectural analysis All parameters

10 Intel s Piersol HE Profiler Multiple Views Simplify Analysis Grid View Sort Tabular Data Display call tree and event data Color coded CPU utilization Timeline View Thread Transitions & CPU Utilization Source/Asm View See Data on Source Cross Selection & Filters Quickly find the answer you need See transitions See utilization Visualize Frames Line by line data ASM & source side by side Basic blocks Double click in grid to open source / asm Select in timeline to highlight functions in grid Select in source to highlight asm basic blocks Filter by module / process / function / frame

11 Intel s Piersol HE Profiler All New VTune Performance Analyzer What s New Presets for performance experiments Statistical call tree Threading timeline Cross-select and filter results Attach to a running process on Windows Better source/asm view w/ heat map Frame based analysis Event multiplexing Uncore support Linux* no EntireX*, no Eclipse* required Drivers not required unless using EBS Smart support for TBB & OpenMP* Much easier setup So What? Faster startup and faster run Visualize thread transitions, PMU data, Find the data you need faster Profile your app without restarting Easier navigation, skid compensation Games & graphics find the slow frame Transactions find slow transaction More data with fewer runs Processor wide metrics (e.g., bandwidth) Fewer conflicts. Lighter footprint. Root only required for driver install Display user names / source constructs

12 Compiler Professional Ed Preview Support for new and emerging OSes: Red Hat* EL 6 Ubuntu* 10 Support for new IDE versions, e.g. Microsoft Visual Studio* 2010 Eclipse* CDT 6.0 (C++ only) Support for new processors, e.g. Sandy Bridge (enhanced AVX support) Timeline Beta targeted for late May or June 2010 Product release targeted for Q Request beta access from ronald.w.green@intel.com Product names, features, and target dates subject to change

13 Intel s C++ and Fortran Compilers Performance Compilers Co Array Fortran What s New Fortran 2003 and 2008 support C++ 0x and C99 new features Latest processor support ( string instructions for SSE4.2 and AVX support) Cilk New array syntax for C/C++ Vectorization and auto parallelization improvements Loop profile Statement specific inlining pragmas Improved compile time Matrix multiply call to MKL So What? Data decomposition in Fortran syntax Support of the latest Fortran and C++ standards continues Get the best performance on the latest processors Simple keywords for task parallelism More readable/optimizable array operations Compiler can vectorize and parallelize more often giving increased performance Profile at the loop (not just function level) More control of inlining Lower cost of development Faster matrix multiplies without code change

14 Compiler Pro 12.0 New Fortran Features Support for Co-Array Fortran Shared memory support in Compiler Professional Edition Distributed & shared memory support in Cluster Tool suite Uses Intel MPI technology Can t mix with OpenMP or explicit MPI calls Other Fortran 2008 features DO CONCURRENT CONTIGUOUS I/O enhancements New constants in ISO_FORTRAN_ENV New intrinsic functions Fortran 2003 Support Complete type-bound procedures (GENERIC, OPERATOR,..) FINALization Product names, features, and target dates subject to change

15 Compiler Pro 12.0 New C++ Features More C++0x and C99 features E.g. rvalue references reduce temporary copies Maintain Microsoft Visual Studio* compatibility Optimized string intrinsics Using SSE4.2 instructions New array syntax for C/C++ More readable; Helps the compiler vectorize and parallelize Somewhat similar to Fortran90 concept <array base> [ <lower bound> : <length> [ : <stride>] ] E.g. a[0:s] += b[2:s:2] Incorporation of Cilk technology Simple keywords, especially for task parallelism Hyperobjects to facilitate thread-safe access Provide thread safe reduction operations Product names, features, and target dates subject to change 15

16 Compiler Pro Cilk Integration Feature Example Semantics Spawning a function call Synchronization statement Parallel for loop Hyperobjects x = cilk_spawn func(y); cilk_sync; cilk_for for (int i = 0; i < N; i++) { statement; } Product names, features, and target dates subject to change func executes asynchronously Wait for all children spawned inside the current function Loop iterations execute in parallel. Allow parallelization of reduction operation with minimal source changes Cilk semantics are simple and powerful * Disclaimer: Keyword spelling not finalized. 16

17 Compiler Pro 12.0 New Optimization Features Vectorization improvements, e.g. Loops with mixed data types Enhanced AVX support Vectorize or fail pragmas (pragma SIMD) Improved auto-parallelization Enhanced privatization analysis Declare functions whose calls can safely be parallelized Guided Auto-Parallelization (Advice for vectorization, parallelization and data transformation) Matrix multiply intrinsics may call into MKL More loop multi-versioning auto-parallelization memcpy generation Product names, features, and target dates subject to change 17

18 Compiler Pro 12.0 New Optimization Features Loop profile option Loop level profile data In addition to function level profile data already available profile-loop-report=2 Statement-specific inlining pragmas #pragma forceinline #pragma inline #pragma noinline 18

19 Compiler Pro 12.0 Other Features Security enhancements (Correctness HE plus compiler) Improved source checking, static memory checker Integrated with runtime checker and GUI in HE Studio (required) Math library enhancements Optional library for fast math functions, but at lower accuracy Optional library for consistent results on different processors Debugger enhancements STL object visualization AVX disassembly and register display Improved compile time 19

20 Compiler Pro 12.0 Other Features Debugger enhancements STL object visualization (including TBB debug support) AVX disassembly and register display Standardized new directory structure A generic, default fixed path to current compiler and libraries Example, Linux*: /opt/intel/compilerpro/bin No need to modify makefiles or build scripts with new versions Specific versions still installed side-by-side Generic paths use symbolic links to specific version Default is the last compiler installed (assumes versions are installed in order of release) Version-specific paths still available for explicit control of version Performance libraries follow similar scheme: Example, Linux*: /opt/intel/mkl/lib/intel64 20

21 Intel MKL Domains and Parallelism Where s the Parallelism? Domain SIMD Open MP MPI BLAS 1, 2, 3 X X FFTs X X LAPACK X X (dense LA solvers) PARDISO (sparse solver) (relies on BLAS 3) X VML/VSL X X ScaLAPACK X (cluster dense LA solvers) (hybrid) Cluster FFT Summary Statistics X X X X 21

22 Major New Features for Intel MKL in 2010 Extended AVX/Sandy Bridge support Many optimized kernels More C/C++ support CLAPACK with row major matrices Dynamic accuracy control for VML Added C-style 0-based index arrays in PARDISO New symmetric matrix-vector product BLAS routine in blocked storage Added Split Complex (real ) support for 2D/3D FFTs See Product names, features, and target dates subject to change 22

23 Major New Features for Intel MKL in 2010 cont. New SFMT19937 Random Number Generator with >=2x gain over current implementation (MT19937) Added ability for users to build custom dynamic libraries from MKL dynamic libraries Summary Statistics Library threaded analysis of multi-dimensional data sets Quantiles, moments, correlations 23

24 New Features for Intel IPP in 2010 Optimized for new processors Westmere and new AES instructions Sandy Bridge and AVX DMIP infrastructure and DMIP sample for 2D image processing CPU and multi-core JPEG-XR CODEC JPEG Sample Productization enhanced tests, testing infrastructure 24

25 New Features for Intel IPP in 2010 Windows Imaging Component (WIC) API wrapper for Image Codecs Data Compression Library support (bzip2, zlib, gzip) C String library (limited scope) DMIP DSL for Tighter Visual Studio integration Reduced IPP package size Deprecated obsolete CPU optimizations; Smart dispatcher Improved documentation 25

26 Intel Correctness and Performance Tools Beta

27 Correctness and Performance Tools Intel Cantua HE Checker Dynamic and static checking for memory and threading errors Intel Piersol HE Profiler Next generation performance analyzer Serial and parallel profilers Major changes to infrastructure of our analysis products GUI improvements Activity selection more in line with workflow More intuitive information displays Improved technology PIN replaces bistro Friendlier environment for network installs and execution Improved filtering/sorting utilities

28 Software Development Challenges Problem Statement Size and complexity of applications are greater, organizations facing higher application defects, vulnerabilities and costs Need: *CERT: U.S. Computer Emergency Readiness Team, and Carnegie Melon CyLab *NIST: National Institute of Standards & Technology : Square Project Results Reduce time, effort, and costs required to find and repair coding defects and vulnerabilities, prior to deploying software Increase developer productivity, reduce maintenance, and improve software quality Effective analysis tools to maximize code quality, reliability, and security, while minimizing cost and time Cost Factors Square Project Analysis: Reworking defects 40%-50% of total project effort* Using Software Automated Quality tools in development cycle, increases ROI by 12%-21%*

29 Solution Enterprise-class software analysis tools that can effectively find crucial code defects during the development phase Pinpoints critical memory and threading errors Enhances efficiencies, code reliability, quality, and security Improves developer productivity during the development and quality assurance phases, Reduced maintenance time, and increased ROI

30 Intel s Cantua HE Checker Standalone Correctness Tool Introducing Intel s Cantua HE Checker Memory and Thread Analysis Solution Ensures Code Quality and Reliability Enterprise-class solution Dynamic Memory Analysis Dynamic Thread Analysis Productivity Tools Beta starts week of April 5, 2010 Value At-A-Glance Built-in Dynamic tools for Serial and Parallel code Detects Memory Leaks and Memory corruption Invalid Memory Accesses Invalid Partial Memory Accesses Mismatched Memory Allocation/Deallocation Missing Allocations Uninitialized Memory Accesses & Partial Memory Accesses Detects Deadlocks and Data Races Intuitive GUI and CLI interface for a wide range of functions Dynamic Instrumentation Detailed error data analysis Time line visualization

31 Introducing Intel s HE Studio Minimizes risk, Maximizes Value Ensures Code Security, Reliability, Quality, Lowers TCO Intel s HE Studio Correctness Tool Enterprise-class Code analysis solution Dynamic Memory Analysis Dynamic Thread Analysis Static Security Analysis Detects wide range (>250) of errors and software security vulnerabilities Productivity Tools Value At A Glance Built-in Static and Dynamic tools for Serial and Parallel code Detects Memory Leaks and Memory corruption Invalid Memory Accesses Invalid Partial Memory Accesses Mismatched Memory Allocation/Deallocation Missing Allocations Uninitialized Memory Accesses & Partial Memory Accesses Detects Deadlocks and Data Races Buffer overruns Uninitialized variables and Bad pointers Unsafe library usage Arithmetic overflow OpenMP* errors, unchecked input, heap corruption, error prone usage Intuitive GUI and CLI interface for a wide range of functions Dynamic Instrumentation Detailed error data analysis and Time line visualization

32 Intel Correctness Tools Product Family Positioning Intel Thread Checker Enterprise/HPC Intel Parallel Inspector Mainstream Intel s Cantua HE Checker Enterprise/HPC Intel s HE Studio Enterprise/HPC Data race and deadlock detection C/C++ & Fortran Microsoft Visual Studio 2003, 2005, 2008 Windows XP, Vista Linux Memory Analysis - leaks and corruption Thread Analysis - data races, and deadlocks C/C++ Microsoft Visual Studio 2005, 2008, (next major release 2010) Memory analysis - leaks and corruption Thread analysis - data races, and deadlocks C/C++, Fortran and.net Windows, Linux, Microsoft Visual Studio 2005, 2008, 2010 Standalone package Static Security analysis Memory analysis - leaks and corruption Thread analysis - data races, and deadlocks C/C++, Fortran and.net Windows, Linux, Microsoft Visual Studio 2005, 2008, 2010

33 Legal Disclaimer INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO THIS INFORMATION INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, reference Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright Intel Corporation. 33

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