Simulate the Design using the XSim Simulator

Transcription

1 Simulate the Design using the XSim Simulator This tutorial guides you through the simulation flow using Xsim simulator within Vivado design environment. In this tutorial, you will simulate the workings of an example Verilog code. The example code, which is provided on the course s reference webpage, is for a 4-bit counter with set and reset options. The counter is reset (counter=0) when the reset signal is asserted; the counter is set (counter=15) when the set signal is asserted and otherwise the counter counts up on every clock cycle. To simulate the behavior of the counter, a test bench file is needed which provides the timing for all input signals to the counter (clock, set and reset). Using this test bench in the Xsim simulator, you can observe the behavior of the Verilog code for the counter. To complete this example, you will need both the counter Verilog code and test bench file. Both of these files are located on the course s reference webpage page. Here are all the steps you will need to do to simulate your design. 1. Start a new project in Vivado and use the example Verilog code for the counter. This code is provided on the reference page of the course s website. Make sure that the project synthetizes without any errors. If there are errors, try to fix them before proceeding with simulating the behavior of the module. Here is a copy of the counter module, which can also be found on the course s reference webpage.

2 2. To initiate the simulation click Add Sources under the Project Manager tasks of the Flow Navigator pane. 3. Select the Add or Create Simulation Sources option and click Next. 4. In the Add Sources form, click the Add Files button.

3 5. Browse to the directory where you have downloaded the counter_tb.v file. Select the Copy sources into project. Once you select this option, your test bench file will be copied into a directory structure that Vivado likes to organize its files. This way, you don t have to worry where exactly the test bench file should be placed. If you selected the option to create a new teste bench in the previous window then Vivado will automatically generate the necessary directory structure for simulating your design. The Add Sources should look like this. In our case, the test bench file was in the c:/users/sblair/downloads directory. 6. Click Finish. 7. Select the Sources tab and expand the Simulation Sources group. The counter_tb.v file is added under the Simulation Sources group, and counter.v is automatically placed in its hierarchy.

4 8. Double-click on the counter_tb in the Sources pane to view its contents. The test bench defines the simulation step size and the resolution in line 1. The test bench module definition begins on line 5. Lines 23 through 64 define the stimuli generation. In this simulation, we are generating a clock signal with 5 nsec duty cycle, which is not important for the simulation presented in this tutorial. Several different combinations of sets and resets are tested for different time durations. Line 66 ends the test bench.

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6 Simulate the design for 200 ns using the XSim simulator. 1. Select Simulation Settings under the Project Manager tasks of the Flow Navigator pane. A Project Settings form will appear showing the Simulation properties form. See the window below regarding this step: 2. Select the Simulation tab, and set the Simulation Run Time value to 200 ns. The window should look like the one below. Click OK.

7 3. Click on Run Simulation > Run Behavioral Simulation under the Project Manager tasks of the Flow Navigator pane. The testbench and source files will be compiled and the XSim simulator will be run (assuming no errors). You will see a simulator output similar to the one shown below. You will see four main views: (i) Scopes, where the testbench hierarchy as well as glbl instances are displayed, (ii) Objects, where top-level signals are displayed, (iii) the waveform window, and (iv) Tcl Console where the simulation activities are displayed. Notice that since the testbench used is self-checking, the results are displayed as the simulation is run. 4. Click on the Zoom Fit button located left of the waveform window to see the entire waveform.

8 Notice that the output changes when the input changes. You can also float the simulation waveform window by clicking on the Float button on the upper right-hand side of the view. This will allow you to have a wider window to view the simulation waveforms. To reintegrate the floating window back into the GUI, simply click on the Dock Window button.

9 Change display format if desired. Select count[3:0] in the waveform window, right-click, select Radix, and then select Unsigned Decimal to view the for-loop index in integer form. You can use other formats if desired in the future. This is how the new waveforms are displayed in the waveform window:

10 Add more signals to monitor lower-level signals and continue to run the simulation for 500 ns. 1. Expand the counter_tb instance, if necessary, in the Scopes window and select the counter1 instance. 2. Several signals will be displayed in the Objects window as shown above. 3. Select count_internal[3:0] and drag them into the waveform window to monitor those lower level signals. 4. On the simulator tool buttons ribbon bar, type 1 us in the time window, click on the dropdown button of the units field and select ns, and click on the Relaunch Simulation button.

11 5. The simulation will run for an additional 1 micro second 6. Click on the Zoom Fit button and observe the output. 7. Close the simulator by selecting File > Close Simulation. 8. Click OK and then click No to close it without saving the waveform.