Icarus Verilog HDL (iverilog)
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1 Icarus Verilog HDL (iverilog) It is a good idea to install a compiler / simulator on the PC. This will allow you to save your code on your computer and will allow you to do some things not possible online. Icarus is small and efficient compiler that is more than enough for learning the verilog HDL. Although Icarus is mainly tailored towards Linux, we have Windows installer available. This tutorial is based upon Windows, though you can follow it for Linux version as well. Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format. The main compiler is written by (and copyright) Stephen Williams. The Windows iverilog program can be downloaded from The latest version at the time of writing is is only 11.2 MB in size. Once you have downloaded the file named iverilog _setup.exe, double click to install it. Basically, it will extract all the files and put it in a default directory C:/iverilog. The C:/iverilog/bin subdirectory contains the executable file verilog.exe that is used to run simulator. Now create a new file called hello.v in the directory C:/iverilog/bin and edit it with notepad or any other text editor. Enter the following lines of code in hello.v module main; initial begin $display("learning Verilog is easy."); $finish ; module Go to your DOS prompt ( Start - > cmd ) and navigate to the directory C:\iverilog\bin. Then type,
2 C:\iverilog\bin> iverilog hello.v This will run iverilog and compile the file hello.v At this point it generates an output file a.out. The output can be seen by running the command vvp. C:\>iverilog\bin > vvp a.out It just gives out the output saying "Learning Verilog is easy". It just verifies that your set up is ready for running verilog code. Please not that you could also use the following commands to get the same result (It basically generates the output file hello using the command line option -o). C:\iverilog\bin> iverilog -o hello hello.v C:\iverilog\bin> vvp hello Moving on, we will write an actual real life verilog code - a comparator. But before that, we would like to point that, you may want to keep your code in a separate directory in place of C:/verilog/bin. You will need to set you path variable in the Windows, so that you are able to run your code from anywhere. If you wish to set you path variable, Go to Start -> Computer ->Properties -> Advanced System Settings -> Environment Variable -> System Variable and click on the variable named path and then click edit. Now add C:\iverilog\bin; at the and of the value so this variable. Important caution - do not delete the existing values of the variable name. Start a new DOS prompt window for the environment variable to be active (may be, you have to restart the computer). Now we have understood the concept we will compile the code and and run it in Icarus. Copy the following source codes in the directory C:\iverilog\bin. comparator.v file module comparator( input x, input y, output z ); assign z = (~x & ~y) (x & y); module simulus.v file
3 // testbench for comparator module `timescale 1ns / 1ps module stimulus; reg x; // Inputs reg y; wire z; // Output // Instantiate the Unit Under Test (UUT) comparator uut (.x(x),.y(y),.z(z) ); x = 0; y = 0; // Initialize Inputs #20 x = 1; //20 ns later, make x=1, y stays 0 #20 y = 1; //another 20 ns later, make y=1, x stays 1 #20 y = 0; //another 20 ns later, make y=0, x stays 1 #20 x = 1; //another 20 ns later, make x=1, y stays 0 #40; //wait for 40 ns $monitor("x=%d,y=%d,z=%d \n",x,y,z); //d for decimal display, b for binary display module Now go to the dos windows ( Start -> cmd) navigate to the iverilog\bin directory C:\> cd iverilog\bin Compile the program using: C:\iverilog\bin>iverilog -o comparator.vpp comparator.v stimulus.v If everything goes right, it will not produce any output. If there are any syntax errors it will show some errors. The output file is comparator.vvp To see the output of the stimulus, you may like to give the following command: C:\iverilog\bin>vvp comparator.vvp This shows the following output. x=0,y=0,z=1 x=1,y=0,z=0 x=1,y=1,z=1 x=0,y=1,z=0 C:\iverilog\bin>
4 Viewing Waveform using GTKWave So far we have been using $monitor to print our input and output values at the terminal. This is not bad as long as you make out simpler circuits. The Icarus, also comes with a decent waveform viewing tool called GTKWave. You can see the binaries in the directory C:/iverilog/gtkwave/bin. Before we wish to use the gtkwave, we may wish to add the pathname of the gtkwave in the list of the environment variables. This can be done in the same way as we did for iverilog. Go to Start -> Computer ->Properties -> Advanced System Settings -> Environment Variable -> System Variable and click on the variable named path and then click edit. Now add C:\iverilog\gtkwave\bin; We will now ext our comparator example to see how we can use the gtkwave to view waveform. You need to add the following two lines of code in the stimulus file. $dumpfile("test.vcd"); $dumpvars(0, stimulus); We are presenting the complete code again with these two lines added. comparator.v file module comparator( input x, input y, output z ); assign z = (~x & ~y) (x & y); module stimulus.v file `timescale 1ns / 1ps module stimulus; reg x; reg y; // Inputs wire z; // Output // Instantiate the Unit Under Test (UUT) comparator uut (.x(x),.y(y),.z(z) ); $dumpfile("test.vcd"); $dumpvars(0, stimulus); x = 0; y = 0; // Initialize Inputs #20 x = 1; #20 y = 1; #20 y = 0; #20 x = 1; #40 ; $monitor("t=%3d x=%d,y=%d,z=%d \n",$time,x,y,z, ); module We will now compile the program with following commands : C:/iverilog/bin/iverilog -o mydesign comparator.v stimulus.v C:/iverilog/bin/vvp mydesign
5 Navigate into the gtkwave/bin directory. Then type: C:/iverilog/gtkwave/bin/gtkwave This opens the GTKwave a new window for displaying the graphs. Open the file test.vcd created earlier at C:/iverilog/bin/ using File > Open New Tab Select the file stimulus under the SST tab. The drag and drop the waveforms that you wish to see. It will show up something like this:
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