The Problem with P6. Problem for high performance implementations
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1 CDB. CDB.V he Problem with P6 Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch Map able + Regfile value R value Head Retire Dispatch op RS 1 2 V1 FU V2 ail Dispatch Problem for high performance implementations oo much value movement (regfile/ RS regfile) Multi-input muxes, long buses complicate routing and slow clock 3/MIPSR10K Slide 1
2 CDB. Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch MIPS R10K: Alternative Implementation Map able + R old Head Retire value Dispatch op RS Arch. Map Free List ail Dispatch FU One big physical register file holds all data - no copies + Register file close to FUs small fast data path and RS on the side used only for control and tags 3/MIPSR10K Slide 2
3 Register Renaming in R10K Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch Architectural register file? Gone Physical register file holds all values #physical registers = #architectural registers + # entries Map architectural registers to physical registers Removes WAW, WAR hazards (physical registers replace RS copies) Fundamental change to map table Mappings cannot be 0 (there is no architectural register file) Free list keeps track of unallocated physical registers is responsible for returning physical registers to free list Conceptually, this is true register renaming Have already seen an example 3/MIPSR10K Slide 3
4 Register Renaming Example Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch Parameters Names:,r2,r3 Locations: p1,p2,p3,p4,p5,p6,p7 Original mapping: p1, r2 p2, r3 p3, p4 p7 are free Mapable FreeList Raw insns Renamed insns r2 r3 p1 p2 p3 p4,p5,p6,p7 add r2,r3, add p2,p3,p4 p4 p2 p3 p5,p6,p7 sub r2,,r3 sub p2,p4,p5 p4 p2 p5 p6,p7 mul r2,r3, mul p2,p5,p6 p6 p2 p5 p7 div,r3,r2 div p6,p5,p7 Question: how is the insn after div renamed? We are out of free locations (physical registers) Real question: how/when are physical registers freed? 3/MIPSR10K Slide 4
5 Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch Freeing Registers in P6 and R10K P6 No need to free storage for speculative ( in-flight ) values explicitly emporary storage comes with entry R: copy speculative value from to register file, free entry R10K Can t free physical register when insn retires No architectural register to copy value to But Can free physical register previously mapped to same logical register Why? All insns that will ever read its value have retired 3/MIPSR10K Slide 5
6 Freeing Registers in R10K Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch Mapable FreeList Raw insns Renamed insns r2 r3 p1 p2 p3 p4,p5,p6,p7 add r2,r3, add p2,p3,p4 p4 p2 p3 p5,p6,p7 sub r2,,r3 sub p2,p4,p5 p4 p2 p5 p6,p7 mul r2,r3, mul p2,p5,p6 p6 p2 p5 p7 div,r3,r2 div p6,p5,p7 When add retires, free p1 When sub retires, free p3 When mul retires, free? When div retires, free? See the pattern? 3/MIPSR10K Slide 6
7 R10K Data Structures Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch New tags (again) P6: # R10K: PR# : physical register corresponding to insn s logical output old: physical register previously mapped to insn s logical output RS, 1, 2: output, input physical registers Map able +: PR# (never empty) + ready bit Architectural Map able : PR# (never empty) Free List : PR# No values in, RS, or on CDB 3/MIPSR10K Slide 7
8 R10K Data Structures Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch ht # Insn old S X C 1 ldf X(), 2 mulf,, 3 stf,z() 4 addi,4, 5 ldf X(), 6 mulf,, 7 stf,z() Reservation Stations # FU busy op ALU no 2 LD no 3 S no 4 FP1 no 5 FP2 no Map able Reg + PR#1+ PR#2+ PR#3+ PR#4+ Free List PR#5,PR#6, PR#7,PR#8 Arch. Map Reg + CDB Notice I: no values anywhere PR#1 PR#2 PR#3 PR#4 Notice II: Mapable is never empty 3/MIPSR10K Slide 8
9 R10K Pipeline Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch R10K pipeline structure: F, D, S, X, C, R D (dispatch) Structural hazard (RS,, LSQ, physical registers)? stall Allocate RS,, LSQ entries and new physical register () Record previously mapped physical register (old) C (complete) Write destination physical register R (retire) head not complete? Stall Handle any exceptions Store write LSQ head to D$ Free, LSQ entries Free previous physical register (old) Record committed physical register () 3/MIPSR10K Slide 9
10 CDB. R10K Dispatch (D) Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch Map able + R old Head Retire value Dispatch op RS Arch. Map Free List ail Dispatch FU Read preg (physical register) tags for input registers, store in RS Read preg tag for output register, store in (old) Allocate new preg (free list) for output register, store in RS,, Map able 3/MIPSR10K Slide 10
11 CDB. R10K Complete (C) Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch Map able + R old Head Retire value Dispatch op RS Arch. Map Free List ail Dispatch FU Set insn s output register ready bit in map table Set ready bits for matching input tags in RS 3/MIPSR10K Slide 11
12 CDB. R10K Retire (R) Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch Map able + R old Head Retire value Dispatch op RS Arch. Map Free List ail Dispatch FU Return old of head to free list Record of head in architectural map table 3/MIPSR10K Slide 12
13 R10K: Cycle 1 Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch ht # Insn old S X C ht 1 ldf X(), 2 mulf,, 3 stf,z() 4 addi,4, 5 ldf X(), 6 mulf,, 7 stf,z() PR#5 PR#2 Reservation Stations # FU busy op ALU no 2 LD yes ldf PR#5 PR#4+ 3 S no 4 FP1 no 5 FP2 no Map able Reg + PR#1+ PR#5 PR#3+ PR#4+ Free List PR#5,PR#6, PR#7,PR#8 Arch. Map Reg + PR#1 PR#2 PR#3 PR#4 CDB Allocate new preg (PR#5) to Remember old preg mapped to (PR#2) in 3/MIPSR10K Slide 13
14 R10K: Cycle 2 Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch ht # Insn old S X C h 1 ldf X(), PR#5 PR#2 c2 t 2 mulf,, PR#6 PR#3 3 stf,z() 4 addi,4, 5 ldf X(), 6 mulf,, 7 stf,z() Reservation Stations # FU busy op ALU no 2 LD yes ldf PR#5 PR#4+ 3 S no 4 FP1 yes mulf PR#6 PR#1+ PR#5 5 FP2 no Map able Reg + PR#1+ PR#5 PR#6 PR#4+ Free List PR#6,PR#7, PR#8 Arch. Map Reg + PR#1 PR#2 PR#3 PR#4 CDB Allocate new preg (PR#6) to Remember old preg mapped to f3 (PR#3) in 3/MIPSR10K Slide 14
15 R10K: Cycle 3 Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch ht # Insn old S X C h 1 ldf X(), PR#5 PR#2 c2 c3 t 2 mulf,, PR#6 PR#3 3 stf,z() 4 addi,4, 5 ldf X(), 6 mulf,, 7 stf,z() Reservation Stations # FU busy op ALU no 2 LD no 3 S yes stf PR#6 PR#4+ 4 FP1 yes mulf PR#6 PR#1+ PR#5 5 FP2 no Map able Reg + PR#1+ PR#5 PR#6 PR#4+ Free List PR#7,PR#8, PR#9 Stores are not allocated pregs Free Arch. Map Reg + PR#1 PR#2 PR#3 PR#4 CDB 3/MIPSR10K Slide 15
16 R10K: Cycle 4 Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch ht # Insn old S X C h 1 ldf X(), PR#5 PR#2 c2 c3 c4 2 mulf,, PR#6 PR#3 c4 3 stf,z() t 4 addi,4, PR#7 PR#4 5 ldf X(), 6 mulf,, 7 stf,z() Reservation Stations # FU busy op ALU yes addi PR#7 PR#4+ 2 LD no 3 S yes stf PR#6 PR#4+ 4 FP1 yes mulf PR#6 PR#1+ PR#5+ 5 FP2 no Map able Reg + PR#1+ PR#5+ PR#6 PR#7 Free List PR#7,PR#8, PR#9 Arch. Map Reg + PR#1 PR#2 PR#3 PR#4 ldf completes set Mapable ready bit CDB PR#5 Match PR#5 tag from CDB & issue 3/MIPSR10K Slide 16
17 R10K: Cycle 5 Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch ht # Insn old S X C 1 ldf X(), PR#5 PR#2 c2 c3 c4 h 2 mulf,, PR#6 PR#3 c4 c5 3 stf,z() 4 addi,4, PR#7 PR#4 c5 t 5 ldf X(), PR#8 PR#5 6 mulf,, 7 stf,z() Reservation Stations # FU busy op ALU yes addi PR#7 PR#4+ 2 LD yes ldf PR#8 PR#7 3 S yes stf PR#6 PR#4+ 4 FP1 no 5 FP2 no Free Map able Reg + PR#1+ PR#8 PR#6 PR#7 Free List PR#8,PR#2, PR#9 Arch. Map Reg + PR#1 PR#5 PR#3 PR#4 CDB ldf retires Return PR#2 to free list Record PR#5 in Arch map 3/MIPSR10K Slide 17
18 Precise State in R10K Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch Problem with R10K design? Precise state is more difficult Physical registers are written out-of-order (at C) hat s OK, there is no architectural register file We can free written registers and restore old ones Do this by manipulating the Map able, Arch able, Free List, not regfile wo ways of restoring Map able and Free List Option I: serial rollback using, old fields ± Slow, but simple Option II: single-cycle restoration from some checkpoint ± Fast, but checkpoints are expensive Modern processor compromise: make common case fast Checkpoint only (low-confidence) branches (frequent rollbacks) Serial recovery for page-faults and interrupts (rare rollbacks) 3/MIPSR10K Slide 18
19 Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch R10K: Cycle 5 (with precise state) ht # Insn old S X C 1 ldf X(), PR#5 PR#2 c2 c3 c4 h 2 mulf,, PR#6 PR#3 c4 c5 3 stf,z() 4 addi,4, PR#7 PR#4 c5 t 5 ldf X(), PR#8 PR#5 6 mulf,, 7 stf,z() Reservation Stations # FU busy op ALU yes addi PR#7 PR#4+ 2 LD yes ldf PR#8 PR#7 3 S yes stf PR#6 PR#4+ 4 FP1 no 5 FP2 no Map able Reg + PR#1+ PR#8 PR#6 PR#7 Free List PR#8,PR#2, PR#9 CDB undo insns 3-5 (doesn t matter why) use serial rollback 3/MIPSR10K Slide 19
20 Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch R10K: Cycle 6 (with precise state) ht # Insn old S X C 1 ldf X(), PR#5 PR#2 c2 c3 c4 h 2 mulf,, PR#6 PR#3 c4 c5 3 stf,z() t 4 addi,4, PR#7 PR#4 c5 5 ldf X(), PR#8 PR#5 6 mulf,, 7 stf,z() Reservation Stations # FU busy op ALU yes addi PR#7 PR#4+ 2 LD no 3 S yes stf PR#6 PR#4+ 4 FP1 no 5 FP2 no Map able Reg + PR#1+ PR#5+ PR#6 PR#7 Free List PR#2,PR#8 PR#9 CDB undo ldf (#5) 1. free RS 2. free (PR#8), return to FreeList 3. restore M[] to old (PR#5) 4. free #5 insns may execute during rollback (not shown) 3/MIPSR10K Slide 20
21 Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch R10K: Cycle 7 (with precise state) ht # Insn old S X C 1 ldf X(), PR#5 PR#2 c2 c3 c4 h 2 mulf,, PR#6 PR#3 c4 c5 t 3 stf,z() 4 addi,4, PR#7 PR#4 c5 5 ldf X(), 6 mulf,, 7 stf,z() Reservation Stations # FU busy op ALU no 2 LD no 3 S yes stf PR#6 PR#4+ 4 FP1 no 5 FP2 no Map able Reg + PR#1+ PR#5+ PR#6 PR#4+ Free List PR#2,PR#8, PR#7, PR#9 CDB undo addi (#4) 1. free RS 2. free (PR#7), return to FreeList 3. restore M[] to old (PR#4) 4. free #4 3/MIPSR10K Slide 21
22 Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch R10K: Cycle 8 (with precise state) ht # Insn old S X C 1 ldf X(), PR#5 PR#2 c2 c3 c4 ht 2 mulf,, PR#6 PR#3 c4 c5 3 stf,z() 4 addi,4, 5 ldf X(), 6 mulf,, 7 stf,z() Reservation Stations # FU busy op ALU no 2 LD no 3 S no 4 FP1 no 5 FP2 no Map able Reg + PR#1+ PR#5+ PR#6 PR#4+ Free List PR#2,PR#8, PR#7, PR#9 CDB undo stf (#3) 1. free RS 2. free #3 3. no registers to restore/free 4. how is D$ write undone? 3/MIPSR10K Slide 22
23 P6 vs. R10K (Renaming) Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch Feature P6 R10K Value storage ARF,,RS PRF Register ARF/ PRF FU Register FU PRF Speculative value automatic overwriting insn Data paths ARF/ RS PRF FU RS FU FU PRF FU ARF Precise state Simple: clear everything Complex: serial/checkpoint R10K-style became popular in late 90 s, early 00 s E.g., MIPS R10K (duh), DEC Alpha 21264, Intel Pentium4 P6-style is perhaps making a comeback Why? Frequency (power) is on the retreat, simplicity is important 3/MIPSR10K Slide 23
24 Summary Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch Modern dynamic scheduling must support precise state A software sanity issue, not a performance issue Strategy: Writeback Complete (OoO) + Retire (io) wo basic designs P6: omasulo + re-order buffer, copy based register renaming ± Precise state is simple, but fast implementations are difficult R10K: implements true register renaming ± Easier fast implementations, but precise state is more complex 3/MIPSR10K Slide 24
25 Martin, Roth, Shen, Smith, Sohi, yson, Vijaykumar, Wenisch Dynamic Scheduling Summary Out-of-order execution: a performance technique Easier/more effective in hardware than software (isn t everything?) Idea: make scheduling transparent to software Feature I: Dynamic scheduling (io OoO) Performance piece: re-arrange insns into high-performance order Decode (io) dispatch (io) + issue (OoO) wo algorithms: Scoreboard, omasulo Feature II: Precise state (OoO io) Correctness piece: put insns back into program order Writeback (OoO) wo designs: P6, R10K Next: memory scheduling complete (OoO) + retire (io) 3/MIPSR10K Slide 25
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