HW/SW-Codesign Lab. Seminar 2 WS 2016/2017. chair. Vodafone Chair Mobile Communications Systems, Prof. Dr.-Ing. Dr. h.c. G.

Transcription

1 Vodafone Chair Mobile Communications Systems, Prof. Dr.-Ing. Dr. h.c. G. Fettweis HW/SW-Codesign Lab Seminar WS / TU Dresden, Slide

2 CORE FEATURES TU Dresden HW/SW-Codesign Lab Slide

3 corelx_hwswcd Xtensa LX ALU -bit MUL Load/Store Unit Basic Instr. Set Extended Instr. Set Load/Store Unit Memory Managment Unit (MMU) Processor Interface (PIF) Instr. Fetch Unit 8 System RAM System ROM 8 8 DMEM DMEM IMEM ICache TU Dresden HW/SW-Codesign Lab Slide

4 corelx_hwswcd Memories Memory Size Start address Instruction RAM (IMEM) kb xfff Data RAM (DMEM) kb xffe Data RAM (DMEM) kb xffe8 Instruction Cache (ICache) kb -- System RAM MB x System ROM 8 kb x For parallel access, place important global variables/arrays in different DMEMs, e.g.: int data_array[8] attribute ((section(.dram.data ))); or int *data_array = (*int)xffe8; Otherwise the compiler automatically places the variables in System RAM. TU Dresden HW/SW-Codesign Lab Slide

5 TIE Basic and most used TIE language constructs: Immediate Range Table State Register File Operation Schedule Instruction Format Slot Opcodes TIE Built-in Modules Function Documentation TIE-Doc.pdf TU Dresden HW/SW-Codesign Lab Slide

6 FLIX FLIX: Flexible Length Instruction Extension Combine operations into one instruction word of flexible width VLIW: Very Large Instruction Word Allowing the processor to execute several operations simultaneously Format flix_x TIE code format flix_x {slot_, slot_, slot} slot_opcodes slot_ {vsalu} slot_opcodes slot_ {vsmac} slot_opcodes slot_ {vsldst} Requirements: At least opt. level O Enable optimization alias restrict: OPT:alias=restrict TU Dresden HW/SW-Codesign Lab Slide

7 TASK : FIR FILTER TU Dresden, Slide

8 FIR Filter FIR filter: Hot-Spots Multiply/Accumulate Operation (MAC) Load input values/coefficients Store output values void fir_c(short *in, int *out, int len) { int n, i; for (n = ; n < len+; n++) { for (i = ; i < 8; i++) out[n] += in[n+-i]*coeff[i]; } } Different approaches: ) Performing MAC on one input element with one coefficient ) Performing MAC on multiple elements in parallel SIMD ) Separated instructions for Load, MAC and Store TU Dresden HW/SW-Codesign Lab Slide 8

9 Approach Performing MAC on one input element with one coefficient by applying Fusion C code: for (n = ; n < len+; n++) { for (i = ; i < 8; i++) FIR_MAC(out[n], in[n+-i], coeff[i]); } TIE code: operation FIR_MAC {inout AR acc, in AR a, in AR b} { } { wire [:] product = TIEmul(a[:], b[:], 'b); assign acc = acc + product; } FIR_MAC produces the output in one clock cycle. fused operations TU Dresden HW/SW-Codesign Lab Slide 9

10 Approach Performing MAC on multiple elements in parallel SIMD FIR_MAC_SIMD produces output of the second for-loop in one clock cycle fused and parallel operations Recommended schedule to reduce c.p. Addition is done cycle after multiplications regfile VR_fir 8 8 vrf operation FIR_MAC_SIMD {out AR acc, in VR_fir a, in VR_fir b} { } { // 8x signed multiplications wire [:] product = TIEmul(a[:], b[:], 'b); wire [:] product = TIEmul(a[:9], b[:], 'b); wire [:] product = TIEmul(a[9:8], b[:], 'b); wire [:] product = TIEmul(a[9:], b[:8], 'b); wire [:] product = TIEmul(a[:8], b[9:], 'b); wire [:] product = TIEmul(a[:], b[9:8], 'b); wire [:] product = TIEmul(a[:], b[:9], 'b); wire [:] product = TIEmul(a[:], b[:], 'b); } // addition of the 8 products assign acc = TIEaddn(product, product, product, product, product,product,product,product); schedule FIR_MAC_SIMD_SCHED {FIR_MAC_SIMD} { def acc ; } TU Dresden HW/SW-Codesign Lab Slide

11 Approach Separate Load, MAC, and Store operations into different TIE instructions Load 8 elements: FIR_LD Perform on 8 elements in parallel and store result in every clock cycle: FIR_CALC_ST Hold coefficients in Look-Up table access within clock cycle Pipelining by using Schedule or additional registers TIE code operation FIR_LD {} {out VAddr, in MemDataIn8, inout ptr_in, inout shad_in8, out in8_} { assign VAddr = ptr_in; assign ptr_in = ptr_in + ; assign shad_in8 = MemDataIn8; assign in8_ = shad_in8; } FIR_LD(); for(n=; n<((len+)>>)-; n++) { FIR_LD(); } C code TU Dresden HW/SW-Codesign Lab Slide

12 Approach operation FIR_CALC_ST {} {out VAddr, out MemDataOut, out StoreByteDisable, inout ptr_out, inout in8_, inout in8_, inout st_cnt, inout product, inout product, inout product, inout product, inout product, inout product, inout product, inout product} { assign product = TIEmul(in8_[:], coeff[], 'b); assign product = TIEmul(in8_[: 9], coeff[], 'b); assign product = TIEmul(in8_[ 9: 8], coeff[], 'b); assign product = TIEmul(in8_[ 9: ], coeff[], 'b); assign product = TIEmul(in8_[ : 8], coeff[], 'b); assign product = TIEmul(in8_[ : ], coeff[], 'b); assign product = TIEmul(in8_[ : ], coeff[], 'b); assign product = TIEmul(in8_[ : ], coeff[], 'b); assign in8_ = {in8_[:], in8_[:]}; assign in8_ = {'h, in8_[:]}; assign VAddr = ptr_out; assign ptr_out = ptr_out + ; assign ptr_out_kill = st_cnt; assign StoreByteDisable = {{st_cnt}}; assign st_cnt = 'b; 8-fold SIMD MULs Shift/Prepare next values Interface/Pointer increment } // addition of the 8 products assign MemDataOut = TIEaddn(product, product, product, product, product, product, product, product); Write to memory TU Dresden HW/SW-Codesign Lab Slide

13 TASK : FFT/IFFT TU Dresden HW/SW-Codesign Lab Slide

14 Discrete Fourier Transformation DFT FIR filter: DFT: DFT is comparable with FIR filter: Input values x Coefficients become complex: b i ee jjππkkmm NN TU Dresden HW/SW-Codesign Lab Slide

15 DFT FFT/DIT Cooley-Tukey algorithm for a Decimation in Time (DIT) radix- FFT N=n, N is power of Twiddle factor: WW mm nn = ee jjππmm nn TU Dresden HW/SW-Codesign Lab Slide

16 Butterfly Network Decimation in Time DIT Compute Node ( ) FFT compute node ( ) ( ) ( ) ( ) ( ) ( ) ( ) Bit-reverse order WW WW WW WW sets WW WW WW WW sets set WW WW WW WW even odd + + x w twiddle factor + - x w TU Dresden HW/SW-Codesign Lab Slide

17 Calculating Twiddle Factors WW nn mm = ee jjππmm nn n = WW = n = WW = WW = jj n = WW = WW = jj WW = jj WW = + jj n number of interleaved butterflies TU Dresden HW/SW-Codesign Lab Slide

18 DFT FFT/DIF Sande-Tukey algorithm for a Decimation in Frequency (DIF) radix- FFT TU Dresden HW/SW-Codesign Lab Slide 8

19 FFT DIF Even and odd indexed frequency values N=n, N is power of Twiddle factor: WW kk nn = ee jjππkk nn TU Dresden HW/SW-Codesign Lab Slide 9

20 DIT, DIF Decimation in Time Decimation in Frequency ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) Bit-reverse order sets sets set sets sets set Bit-reverse order TU Dresden HW/SW-Codesign Lab Slide

21 FFT: C code Given C code Fixed integer arithmetic ( bit real, bit imaginary part) Code for FFT/IFFT with any N with power of Data Reordering Variable scaling to prevent overflow Initialization Data Reordering Variable Scaling Stage i Calculate Twiddle Factor Compute Result of Butterfly Multiple Twiddle Factors? no yes Stage i+ TU Dresden HW/SW-Codesign Lab Slide

22 SUMMARY TU Dresden HW/SW Co-Design Lab Slide

23 Summary Tasks Introduce TIE instructions in hot-spots of FFT/IFFT Hold constants in TIE states or tables Compare DIT/DIF In the end, FFT should work with selected N with power of Parallelization MAC operation: Butterfly Compute Node SIMD: Butterflies of one stage can be computed independently FLIX: Load input data simultaneously by using the two available DMEMs of corelx_hwswcd TU Dresden HW/SW-Codesign Lab Slide