Xtensa. Andrew Mihal 290A Fall 2002

Transcription

1 Xtensa Andrew Mihal 290A Fall

2 Outline Introduction Single processor Xtensa system architecture Exporting a programming model for single processor Multiple processor system architecture Exporting a programming model for multiple processor 2

3 Introduction Configurable, extensible, synthesizable processor core Timers, Interrupts Instruction Fetch Core Register File Core ALU Designer s Register Files Designer s Function Units Data Load/Store $ $ System Bus 32/64/128 Bit Instruction RAM/ROM 32 Bit Data RAM/ROM Same as System Bus XLMI (peripherals) Same as System Bus 3

4 Configurable Interfaces: Choose endian-ness Choose data bus width Optional data/instruction memories Optional XLMI bus for peripherals Standard data/instruction cache parameters Optional timers, interrupts Core: Optional multiplier Optional FPU Vectra DSP engine TIE 4

5 Estimation Speed Power Core area Total area 5

6 Extensible TIE = Tensilica Instruction Extension Accelerate program hotspots with custom instructions Bit-level parallelism Design Flow: 1. Start with Xtensa core with no TIE 2. Profile application on core to find hotspots 3. Restructure application to isolate hotspots in functions 4. Develop TIE instructions 5. Replace hotspot functions with TIE 6. Goto 2 6

7 TIE Syntax like Verilog, perl preprocessor Byteswap: opcode BYTESWAP op2=4 b0000 CUST0 state COUNT 32 state SWAP 1 user_register CNT 0 {COUNT} user_register SWAP 1 {SWAP} iclass bs {BYTESWAP} {out arr, in ars} {inout COUNT, in SWAP} semantic bs {BYTESWAP} { wire [31:0] ars_swapped = {ars[7:0], }; assign arr = SWAP? ars_swapped : ars; assign COUNT = COUNT + SWAP; } 7

8 TIE Compiler Output Header file for: unsigned int BYTESWAP(unsigned int s); unsigned int RCNT(); void WCNT(unsigned int s); bool RSWAP(); void WSWAP(bool s); 8

9 TIE Compiler Output C function equivalents Test TIE against golden model Compile into program to make sure it still works Verilog Estimate performance and area requirements Plugins for simulator and compiler Recognize function calls as intrinsics and generate TIE assembly instructions Simulate timing and functionality when TIE instruction is executed 9

10 Simulation ISS Instruction set emulator Reasonably accurate (~100 cycles) performance estimation of pipeline and caches XTMP RTL Transaction-accurate simulator Multiple cores Memory and bus models Custom device models If you want true cycle-accuracy 10

11 Outline Introduction Single processor Xtensa system architecture Exporting a programming model for single processor Multiple processor system architecture Exporting a programming model for multiple processor 11

12 System Architecture Building on top of disciplines Discrete events A basis for modeling hardware To ensure a quality result, use a discipline on top of discrete events Sequential Logic Concept: Restrict yourself to combinational blocks and registers DE 12

13 Single Processor System Architecture Extend lattice of disciplines Node is a discipline Edge is a concept RISC Concept: Hardware reuse in time Sequential Logic DE 13

14 Concept: Reuse in time Sequential logic is too big Some computations appear frequently Make fundamental computations reusable in time 14

15 Discipline: RISC Pull out fundamental computations 15

16 Discipline: RISC Pull out fundamental computations Add memory to store data in time Memory 16

17 Discipline: RISC Pull out fundamental computations Add memory to store data in time Add control logic to manage reuse in time Extra fundamental computations in support of control logic Jump, conditionals, PC=PC+1 PC Memory Instruction Memory Support Computations 17

18 Discipline: Xtensa Xtensa RISC Concept: More sophisticated way of choosing fundamental computations Sequential Logic DE 18

19 Development/Deployment Exporting a programming model Orthogonal lattice of disciplines and concepts C Concept: Compiler Assembly RISC Concept: ISA Expose computation capabilities Expose instruction memory Expose data memory 19

20 Xtensa Programming Model Does not add anything new Fall back to RISC disciplines C Assembly Xtensa RISC 20

21 Multiple Processor System Network-on-Chip discipline Architecture Concept: PE that communicates over interconnect topology NoC Xtensa RISC 21

22 NoC Programming Model Heterogeneous MoCs PEs/Virtual Receivers C NoC Assembly RISC Xtensa 22

23 Concepts Heterogeneous MoCs Concept: Protocol stacks for communication PEs/Virtual Receivers Concept: Expose concurrent communication NoC 23

24 MoC Discipline Orthogonalize computation and communication Combine programming model disciplines Implement computation using programming models for each PE Implement communication with NoC concepts Heterogeneous MoCs PEs/Virtual Receivers C NoC Assembly RISC Xtensa 24

25 Plans Add Xtensa discipline to Teepee s Network-on-Chip design system Map application actors onto Xtensa PEs Simulate Click routers on Xtensa-based NoC systems Get real performance numbers NoC Xtensa MescalPE 25

26 Why This side is not too hard: This side is major: Heterogeneous MoCs PEs/Virtual Receivers C NoC Assembly Xtensa MescalPE 26