Putting MPSOC to Work in Multimedia

Transcription

1 Putting MPSOC to Work in Multimedia Six billion people want live multimedia entertainment and information anywhere and anytime at the lowest cost 1 1. Multimedia subsystems appear everywhere big market 2. Technical demands require new tools, architectures and business models 3. Diversity within multimedia mirrors diversity of entire MPSOC challenge

2 MPSOC Becomes Mainstream Style The Transformation of the Modern Mobile Device Key complementary processing functions of mobile devices covered by Tensilica configurable processors Mobile WiFi Camera Image Processing User Authentication HD Radio Satellite Radio Bluetooth Audio Codec Video Codec Noise Cancellation DTV Reception Baseband DSP GPS 2

3 Software Rules Network of Partners and Customers Defines Strength Audio Complete The designer never has Multimedia to manually add these instructio Video Imaging Solutions 3 Concept Embedded Systems PnpNetwork Technologies Mobile Media Receiver AFA TECHNOLOGY NUFRONT

4 Design Teams Need Different Entry Points Key Question: Who Specifies Processor? Data Processing Needs Hard-wired logic HiFi2 Audio DSP μcontroller 108 Mini Low-power Controller 385VDO Video Decode 381 VDO Video Decode 545CK High-end DSP 330HiFi Audio Xtensa LX 388VDO Video Codec 383VDO Video Codec 212GP Mid-range Controller/ DSP 570T High-end CPU Xtensa 232L Linux CPU RISC CPU Xtensa configurable processors widely used in multimedia Standard cores introduced February 2006: Broad line of compatible controller, CPU and DSP cores High performance generalpurpose DSP Complete low-power HiFi2 audio solution Video spans wide range of mobile media needs Complex Computing Needs 4

5 5 Capability gcc GNU tools Automation Enables Broad Product Line xcc C/C++ Code Development XTMP System Simulation API Xtensa Xtensa Xtensa Xtensa II III IV V Xtensa Xtensa Xplorer Development Environment Seamless Xtensa LX XPRES Compiler CoWare Xtensa 6 Xtensa Xplorer Development Environment XTSC SystemC Simulation TurboXim Xtensa LX2 Xtensa 7 Energy Modeling Video DSP Audio Ctrlrs Next Xtensa Xplorer Next Modeling MP SW tools Processor Synthesis - next Xtensa LX-next next Video next next Audio DSP Xtensa next Ctrlr - next Software development environment Processor and system modeling Automatic processor synthesis High-performance extensible processors Applicationspecific DSPs Mainstream extensible processors Standard controllers time

6 Multimedia Design is Energy-Based Design Example: Xenergy Energy Explorer Processor Description Base CPU Apps Datapaths Cache Extended Registers OCD Timer FPU Application Code int main( ) { int i; i; short c[100]; for (i=0;i<n/2;i++) { Xtensa xcc C/C++ compiler Xenergy Energy Estimator 6 Tune processor instruction set and memories Complete Dynamic Energy/Power Profile Processor + Memory Tune software algorithms and coding

7 Application-Specific Processors Example: HiFi 2 Audio Engine Pre-configured VLIW audio DSP with dual 24-bit MACs for higher quality audio Already in use in dozens of chip designs, licensed by many top semiconductor suppliers Available 2 ways: Xtensa HiFi 2 Audio Engine for further customization Standard 330HiFi audio core Delivers both low power and scalability <75K gates for full-feature processor Example: MP3 decode at 5.7 MHz (core + memory <0.75mW in 65nm) Emerging trend: multiple instances of HiFi2 on same chip, tuned for different mw vs. MHz Extended Fetch/ Decode SLOT 1 SLOT 0 I-RAM I-Cache Queue I/F Audio Reg File Audio ALU Audio MAC 24b Misc. Audio Functions Reg File ALU Branch Unit VLC Accel. External I/F Bridge (opt.) Load/Store D-CACHE D-RAM 1 D-RAM 2 7

8 Sample of HiFi2 Audio Software 8 Currently available: MP3 decode MP3 encode WMA decode WMA encode AAC-LC decode AAC-LC encode aacplus v2 decode aacplus v2 encode aacplus v1 decode aacplus v1 encode Ogg Vorbis Decoder Dolby AC ch decode Dolby AC-3 2 ch encode Dolby Digital Plus 5.1 ch decode Dolby Digital Plus 7.1 ch decode AM3D Diesel 3D AM3D Zirene effects QSound microq MIDI, 3D, effects SONiVOX AudioiNSIDE MIDI SRS WOW XT audio expansion SRS Xspace 3D SRS TruSurround HD AMR NB codec AMR WB codec Schedule for release: BSAC decoder Dolby TrueHD Dolby Digital Prologic II / IIx Dolby Digital Consumer Encoder 2 channel encoder Dolby Digital Compatible Output 5.1 channel encoder aacplus 5.1/7.1 channel decode SBC Bluetooth stereo codec AMR-WB+G.711 codec G codec G.726 codec DTMF aacplus 5.1/7.1 channel decode Dolby TrueHD Dolby Digital Prologic II / IIx G.167 (AEC) G.168 (LEC) WMA 10 Pro Decoder

9 Growth in Video Resolution and Complexity Computational Complexity of Digital Video 1000 HD 1080p HD 720p D1 (576i) CIF Relative Compute Cycles (MPEG-2 CIF = 1) MPEG-2 MPEG-4 Video Standard H Source: A Performance Characterization of High Definition Digital Video Decoding using H.264/AVC, scaled for CIF

10 VDO Design Goals Video encode & decode up to 720 x fps (NTSC) 720 x fps (PAL) Support multiple coding main profile H.264 main L3 decoder MPEG-4 ASP [no L5 decoder MPEG-2 ML decoder WMV9/VC1 main profile decoder MPEG-4 ASP encoder Programmable solution Less than 100MB/s memory decode bandwidth requirement Operating frequency <200Mhz Can be implemented in 130nm G technology Compatible subsets for decode only and Base Profile only 10

11 Top Level Block Diagram 11

12 VDO Product Family Tensilica Engine Decoders Encoder 381VDO 383VDO Baseline Profiles D1 H.264 Baseline Profile MPEG-4 Simple Profile VC-1/WMV9 Simple Profile MPEG-2 Main Profile H.264 Baseline Profile MPEG-4 Simple Profile VC-1/WMV9 Simple Profile MPEG-2 Main Profile None Main / Advanced Profiles D1 MPEG-4 Simple Profile Standard H.264 Main Profile Decode MPEG-4 Advanced Simple Profile Decode VC-1/WMV9 Main Profile Decode Resolution D1 D1 D1 Frames -per- Second Max. Required Clock Rate 172 MHz 156 MHz 189 MHz VDO 388VDO H.264 Main Profile MPEG-4 Advanced Simple Profile VC-1/WMV9 Main Profile MPEG-2 Main Profile H.264 Main Profile MPEG-4 Advanced Simple Profile VC-1/WMV9 Main Profile MPEG-2 Main Profile None MPEG-4 Advanced Simple Profile MPEG-2 Main Profile Decode MPEG-4 Advanced Simple Profile Encode D1 D MHz 185 MHz

13 Optimizing Energy ISA Extension Example: CABAC Context-adaptive binary arithmetic coding (CABAC) achieves higher compression in H.264 Required for Main Profile H.264 decoding Our solution: Xtensa ISA extensions Peak decode performance is one bin per cycle CABAC decode cycles Millions of cycles per second in unaugmented core 710 Millions of cycles per second in ISA extended core 13 Area cost: 20K gates for CABAC ISA extensions Energy for 1 second 164mJ 5mJ Unaugmented core assumes base core plus 16b MUL, LOOP ops, debug, PIF at max MHz 13

14 Optimizing Energy Example: Motion Estimation for MPEG4 Encode 16x16 SAD Half Pel 8pt SAD Control Motion Estimation Millions of cycles required on unaugmented core Millions of cycles required on ISA extended core Area Cost: Less than 40Kgates for all Motion Estimation extensions Energy for 1 second 988mJ 29mJ Unaugmented core assumes base core plus 16b MUL, LOOP ops, debug, PIF at max MHz 14

15 System Issues in Mobile Video Example: Decode Memory Bandwidth Drives Power 15 Off-chip power is a major 100 component of solution power 80 Early, accurate modeling gives 60 insight and enables novel 40 optimization 20 Non-trivial interactions: 0 Core power increases with bit stream data rate Memory power decreases with bit stream data rate Design of video architecture, DMA 120 and software reduces bandwidth 100 by about one-third (saves 30mW) Additional power savings in onchip interconnect and memory controller Memory Bandwidth (MB/s) Mobile DDR power (mw) 120 Memory Bandwidth Needs H.264 MP bitstream (Mbps) Memory Bandwidth Power Cost Delivered MB/s Estimated power for Micron MT46H16M16LF Mobile DDR at 133MHz: 50% 16B block read, 50% 16B writes

16 Move Up to Fully Programmable HD Approach: five small video task engines + audio ~32B bitstream data 16 Bitstream GP scalar with CABAC/CAVLC accel Inst Cache Inst Cache Processor InterFace (PIF) connect Data RAM Hifi2 Audio Engine Data Cache Data RAM Optional Audio motion vectors Bitstream addr Block data Residual data on 6-8 macroblocks 2-4KB Motion Vector GP FLIX Inst Cache Data Cache RAM Data 1K motion vectors Boundary strength data on 5-7 macroblocks Pixel positions: 3-5 macroblocks Intraframe addr 3KB Intraframe data Off-chip DRAM controller Off-chip DDR Prediction Pixel SIMD Inst Cache Data RAM 3-4 computed macroblocks: <1.5KB Residual Small SIMD Inst Cache computed residuals <100B Data Cache Bridge to legacy system bus Deblocking Pixel SIMD Inst Cache Data RAM Result address & data AHB, AXI, OCP, CoreConnect etc.

17 Baseband DSP Needs Extensible Processors 17 Optimized baseband architecture with DSP-optimized task-engines Explosion of standards and multiple radios dictates agile-but-efficient baseband design Each processor extensible to handle specific algorithm kernels with RTL-like power and throughput Easy composition of engines into efficient pipeline Unified hardware and software development model Baseband Processing Engine MAC processor Encrypt encode processor Modulation Demodulation processor Analog I/F Analog I/F Analog I/F Domain Modulation (e.g. OFDM) Error Coding LDPC Security 3-DES AES SSL Upper layer processing Streaming I/O Interfaces Kernel Accel Package Function FIR FFT Viterbi Turbo decoding Kernel Accel Package Special Function Memories Kernel Accel Package Kernel Accel Package Xtensa DSP Foundation Versus TI C64x TI C64x TI C64x TI C62x TI C64x RISC RISC RISC RISC Efficiency (cycle reduction) 4x 3x 3x 18x ~100x 43x 300x 4x 2x

18 System Level Design Matters Example: Audio System Optimization System-level design tools make a big difference Tensilica supports wealth of system modeling: ISS, TurboXim, XTMP C modeling, XTSC System C modeling, CoWare, Seamless Tensilica Xenergy Energy Estimator provides rapid, accurate configuration-specific application power analysis Example: Audio system organization analysis: Relative power PLLs & clock trees Inst cache Other subsystems HiFi2 core PIF Data cache On-chip SRAM DDR/Flash controller Mobile DDR (32M x 16b) Audio DACs System Organization 90G 90G high-vt Power includes dynamic and static at 4K/8K DM + DDR minimum WMA decode MHz Power includes HiFi2 core, I cache, D 4K/8K DM + 192K on-chip cache, On-chip SRAM, DDR (no 16K/32K DM + DDR refresh) I/O through queues 16K/32K DM + 192K on-chip K/32K + 128K on-chip + DDR

19 MPSOC System Design is Collaborative Example: Xtensa in CoWare Platform Architect Configured subsystems with rich interfaces: AMBA bus Local memories Caches Special lookup memories Input queues Output queues Input wires Exported state wires Interrupts 19 Wrapper automatically generated from processor configuration

20 SLOT 1 SLOT 0 Putting It Together The principles Multimedia SOC is not rocket science : hundreds of designs underway around the world Pay attention to best practices: 1.Leverage existing design standards, tools, interconnect and subsystem IP 2.Model early and often. Cost, performance, power largely set in architectural phase 3.Application standards explode. Build in programmability everywhere 4.Look at total bandwidth and total power, especially in offchip communications Differentiation, time-to-market and high efficiency are compatible! Memory controller I/O interfaces Video On-chip interconnect System CPU Fetch/Decode Reg File ALU Branch Unit MAC 16 DSP Load/Store MMU I-Cache External I/F 32 PIF D-Cache MMU Bridge (opt.) 32 AMBA AHB lite MAC processor Queue I/F DSP Encrypt/encode processor Audio Exten ded Fetch/ Decode Modulation processor I-RAM I-Cache Audio Reg Reg File File Audio AL ALU U Audio Bra MAC nch Misc. 24b Unit VL Audio C Functio Acc ns el. D-CACHE D-RAM 1 Load/Store D-RAM 2 External I/F Bridge (opt.) Audio DAC RF 20

21 21 Thank you!