CHAPTER 5. Software Implementation of FFT Using the SC3850 Core

Transcription

1 CHAPTER 5 Software Implementation of FFT Using the SC3850 Core 1

2 Fast Fourier Transform (FFT) Discrete Fourier Transform (DFT) is defined by: 1 nk X k x n W, k 0,1,, 1, W e n0 Theoretical arithmetic complexity: 2 complex multiplications and (-1) complex additions. Real numbers computation 2 real multiplications and 2-2 real additions. 2 j 2

3 Fast Fourier Transform (FFT) There are fast algorithms that compute a DFT with a smaller number of operations. = R M This are called Radix-R algorithms. Radix-2 FFT reduces the complexity to (/2)log 2 complex multiplications log 2 complex additions Radix- FFT 75% reduced multiplications (3/)log = (3/8)log 2 complex multiplications 8(/)log = log 2 complex additions 3

4 Transmitter and Receiver Structure of SC-FDMA and OFDMA Systems

5 DFT: Fast Fourier Transform (FFT) 1 nk, 0,1,, 1, n0 X k x n W k W e Twiddle factors properties: 2 j Periodicity property: 2 j k k k W W e W k k k j k Symmetry property: 2 2 W W W W e W Base change: nk 2 k j n W e W n k

6 Radix- FFT = M Decimation-In-Time (DIT) algorithm: n n1n2, n1 0,1,, 1, n2 0,1, 01 2,3; k k1 k2, k1 01 0,1,, 1, k2 0,1, 0123; 2,3; Decimation-In-Frequency (DIF) algorithm: n n1 n2, n1 01 0,1,, 1, n2 0,1, 0123; 2,3; k k 1 k 2, k 1 0,1,, 1, k 2 0,1,2,3;

7 Radix- DIT FFT 1 3 n n k k X k X k1 k2 xn1n2w n 0 n 0 n2 0,1, 2, nk 1 1 nk 2 1 nk 2 2 xn1n2w W W n10 n nk 1 1 k1 k xn1 W W nk W xn1 1W n 0 1 n k W 1 2k nk 1 1 3k nk x n 2 W W 2 W 3k2 x n 3 W W 1 1 n1 0 n1 0 X k k 1 1 1

8 x(n 1 ) x(n 1 +1) x(n 1 +2) x(n 1 +3) Radix- DIT FFT TFD 0 TFD / TFD / k 1 / 1 0 k 1 / / 1 TFD 0 / k 1 / 1 TFD 0 k / 1 k 1 W 2k 1 W 3k W 1 / 1 0 k 1 TFD / 1 1 TFD k =0 2 X(k( 1 ) 1 X(k 1 +/) 2 X(k 1 +/2) 3 X(k( 1 +3/)

9 Radix- DIT Butterfly Computation complexity 3 complex multiplications 8 complex additions Real computations 12 real multiplications 22 real additions k 1 W j j 1 k 2 =0 X(k 1 ) k 2 =1 X(k( 1 +/) 2k 1 W 1 1 k 2 =2 X(k 1 +/2) 3k 1 W X(k 1 +3/) j 1 k 2 =3 X(k 1 +3/) j

10 Radix- DIT Butterfly Ar = Ar + (Cr Wcr Ci Wci) + (Br Wbr Bi Wbi) + (Dr Wdr Di Wdi) Ai = Ai + (Cr Wci+ Ci Wcr) + (Br Wbi + Bi Wbr) + (Dr Wdi + Di Wdr) Br = Ar (Cr Wcr Ci Wci) + (Br Wbi + Bi Wbr) (Dr Wdi + Di Wdr) Bi = Ai (Cr Wci + Ci Wcr) (Br Wbr Bi Wbi) + (Dr Wdr Di Wdi) Cr = Ar +(Cr Wcr Ci Wci) (Br Wbr Bi Wbi) (Dr Wdr Di Wdi) Ci = Ai + (Cr Wci + Ci Wcr) (Br Wbi + Bi Wbr) (Dr Wdi + Di Wdr) Dr = Ar (Cr Wcr Ci Wci) (Br Wbi + Bi Wbr) + (Dr Wdi + Di Wdr) Di = Ai (Cr Wci + Ci Wcr) + (Br Wbr Bi Wbi) (Dr Wdr Di Wdi) 10

11 Radix- DIF FFT X k X k k n n k k x n1 n2 W n 0n xn n W W W nk 1 1 nk 1 2 n2k2 1 2 n10n20 x n1 W xn1 W xn1 W xn1 3 W W n 2 k2 2k2 3k2 nk 1 1 nk j n k nk nk 2 2 W e 2 2 j k k k nk nk 1 0 x n1 j x n1 1 x n1 j x n1 3 W W n

12 Radix- DIF FFT

13 Radix- DIF Butterfly Ar = Ar + Br + Cr + Dr = (Ar + Br) + (Cr + Dr) Ai = Ai + Bi + Ci + Di = (Ai + Ci) + (Bi + Di) Br =(Ar + Bi Cr Di) Wbr (Ai Br Ci + Dr) Wbi = ((Ar Cr) + (Bi Di)) Wbr ((Ai Ci) (Br Dr)) Wbi Bi = (Ai Br Ci + Dr) Wbr + (Ar + Bi Cr Di) Wbi = ((Ai Ci ) (Br Dr)) Wbr + ((Ar Cr) + (Bi Di)) Wbi 13

14 Radix- DIF Butterfly Cr = (Ar Br + Cr Dr) Wcr (Ai Bi + Ci Di) Wci = ((Ar + Cr) (Br + Dr)) Wcr ((Ai + Ci) (Bi + Di)) Wci Ci = (Ai Bi + Ci Di) Wcr + (Ar Br + Cr Dr) Wci = ((Ai + Ci) (Bi + Di)) Wcr + ((Ar + Cr) (Br + Dr)) Wci Dr =(Ar Bi Cr + Di) Wdr (Ai + Br Ci Dr) Wdi = ((Ar Cr) (Bi Di)) Wdr ((Ai Ci) + (Br Dr)) Wdi Di = (Ai + Br Ci Dr) Wdr + (Ar Bi Cr + Di) Wdi = ((Ai Ci ) + (Br Dr)) Wdr + ((Ar Cr) (Bi Di)) Wdi 1

15 Radix- DIF Butterfly 15

16 16-point Radix- DIF FFT 16

17 Digital Reversed Order of a 16-point Radix- FFT Index Digital pattern Digital reversed Digital reversed pattern index

18 Bit-Reversed Order Index Bit Pattern Bit Reversed Pattern Bit Reversed Index

19 Bit-Reversed Addressing 19

20 20

21 Two Registers in Bit-Reversed Addressing Mode Index Digital- Bit-Reversed Index Bit-Reversed Index Reversed Index with One Address with Two Address Register Registers R0, R (r0) 1 8 (r0) (r1) (r1) (r0) (r0) (r1) (r1) (r0) (r0) (r1) (r1) (r0) (r0) (r1) (r1) 21

22 Scaling The real and imaginary parts of the butterfly can have a growth to. The fixed-scaling method scales down by a fixed factor of at each stage. If an FFT consists of M stages, the output is scaled down by M (M = log ), where is the length of the FFT. 22

23 SIMD Instruction Data Types 23

24 Instruction Description ADD2 Packed addition SUB2 Packed subtraction EG2 Two Words egate IMACSU2 Two integer multiply accumulate signed by unsigned PACK.2W Packs two words PACK.2F Packs two fractional words ADD.W Add 16-bit or 20-bit value ABS2 Two Words Absolute Value ASL2 Arithmetic Shift Left by One of Two Word Operands ASLL2 Multiple-Bit Arithmetic Shift Left of Two Word Operands ASRR2 Multiple-Bit Arithmetic Shift Right of Two Word Operands LSLL2 Multiple-Bit Bitwise Shift Left of Two Word Operands LSR2 Bitwise i Shift Right One Bit of Two Word Operands LSRR2 Multiple-Bit Bitwise Shift Right of Two Word Operands SOD2ffcc Sum Or Difference of Two 16-Bit Values, function & cross MI2 Transfer two 16-bit minimum signed values MAX2 Transfer two 16-bit maximum signed values SUB.W Subtract 16-bit or 20-bit value MPY2 Multiply 2 pairs of 16-bit data. MPY2R Multiply 2 pairs of 16-bit data and round the lower 16 bits of the result. MAC2 Multiply 2 pairs of 16-bit data, clip the lower 16 bits of each result into 16-bit wordand accumulate it with 20-bit accumulator input MAC2R Multiply 2 pairs of 16-bit data, round the lower 16 bits of each result into 16-bit word and accumulate it with 20-bit accumulator input. CLIP20 Clip two 20-bit toperands. SATU20.B Saturate two unsigned bytes. MAC2ffggR Multiply 2 pairs of 16-bit data, add or subtract them from each portion MAC2ffggI -specific format used for FFT calculation. 2

25 Complex Arithmetic Addition of a+jb and c+jd to form e+jf e=a+c; f=b+d; Multiplication li of a+jb and c+jd to form e+jf e=ac-bd; f=j(bc+ad); 25

26 Instructions for Complex Arithmetic Syntax Description SOD2FFCC Da,Db,Dn Sum or Difference of Two Word Values Function and Cross Performs two separate 16-bit additions or subtractions between the high and low portions of two source data registers and stores the results in the two portions of the destination data register. The value of FF and CC determine the behavior. FF:A for addition and S for subtraction CC: XX for crossed and II for not crossed This instruction enables the use of the adder for smaller precision values and therefore increases the number of operations that can be performed simultaneously. MPYRE Assuming the complex type is stored in the register as 16-bit real, 16-bit imaginary, this computes the real part of the complex multiplication. (Da.H* Db.H) - (Da.L * Db.L) -> Dn MPYIM Assuming the complex type is stored in the register as 16-bit real, 16-bit imaginary, this computes the imaginary part of the complex multiplication. (Da.L * Db.H) + (Da.H * Db.L) -> Dn MPYCIM Assuming the complex type is stored in the register as 16-bit real, 16-bit imaginary, this computes the conjugate imaginary part of the complex multiplication. (Da.L * Db.H) - (Da.H * Db.L) -> Dn MACRE Performs MPYRE with accumulation MACIM Performs MPYIM with accumulation MACCIM Performs MPYCIM with accumulation 26