Returning from an Exception. ARM Exception(Interrupt) Processing. Exception Vector Table (Assembly code) Exception Handlers (and Vectors) in C code

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ARM Exception(Interrupt) Processing Returning from an Exception main: instruction instruction instruction instruction Exception The ARM processor automatically: 1. Saves CPSR into banked SPSR 2.

1 ARM Exception(Interrupt) Processing Returning from an Exception main: instruction instruction instruction instruction Exception The ARM processor automatically: 1. Saves CPSR into banked SPSR 2. Saves return address into banked LR 3. Changes CPSR to reflect the Exception Mode 4. Fetches instruction from exception vector table The LR is related to the return address: Processor mode Data Abort IRQ, FIQ, pre-fetch Abort SVC instruction Undefined instruction Return address LR-8 LR-4 LR LR Example: SUBS PC, LR, #4 // returns from IRQ handler Note: SUBS with destination PC means return from exception. It causes SPSR to be restored back into CPSR! Exception Vector Table (Assembly code).section.vectors, ax B _start // reset vector B SERVICE_UND // undefined instruction vector B SERVICE_SVC // software interrrupt vector B SERVICE_ABT_INST // aborted prefetch vector B SERVICE_ABT_DATA // aborted data vector.word 0 // unused vector B SERVICE_IRQ // IRQ interrupt vector B SERVICE_FIQ // FIQ interrupt vector.text Main: SERVICE_IRQ: // code for handling the IRQ exception goes here SUBS PC, LR, #4 // return from IRQ mode Exception Handlers (and Vectors) in C code // Define the IRQ exception handlers void attribute ((interrupt)) cs3_reset (void) void attribute ((interrupt)) cs3_isr_undef (void) void attribute ((interrupt)) cs3_isr_swi (void) void attribute ((interrupt)) cs3_isr_pabort (void) void attribute ((interrupt)) cs3_isr_dabort (void) void attribute ((interrupt)) cs3_isr_irq (void) code for handling the IRQ exception goes here void attribute ((interrupt)) cs3_isr_fiq (void) The C compiler and linker will automatically make the exception vector table 83 84

2 ARM Interrupt Architecture Generic Interrupt Controller (GIC) A9 Core A9 Core IRQ IRQ Peripheral IRQ Peripheral IRQ Peripheral IRQ Generic Interrupt Controller (GIC) Various peripherals, MMU, etc. GIC: handles up to 255 interrupt sources; sends IRQ to either/both A9 Cores 85 PPI: private peripheral interrupt (IRQ for a specific processor) SPI: share peripheral interrupt (IRQ for either processor) SGI: software generated interrupt (IRQ caused by writing to a special register in the GIC 86 Interrupt IDs GIC Example Each peripheral is assigned an interrupt ID DE1-SoC Computer Interrupt IDs: Pushbutton KEY IRQ 73 (ID 73) KEY interrupt signal is received by Distributor. If ID 73 is enabled for CPU 0, send to CPU Interface 0, which can send to A9 core 87 88

3 Summary of Interrupt-driven Code Exercise: Handling Interrupts 1. Set up vector table 2. Main program initializes SP for IRQ mode, initializes GIC for each interrupt ID, initializes peripherals (like KEY port), enables interrupts on A9 processor (CPSR bit I = 0), then loops 3. Exception handler for IRQ Queries GIC to find the interrupt ID Calls the appropriate interrupt service routine (ISR) Returns from exception (SUBS PC, LR, #4) 4. Interrupt Service Routine (ISR) Clears interrupt source Performs interrupt function We will look at the code required for handling interrupts generated by the FPGA s pushbutton keys 1. Assembly code 2. C code Handling Interrupts: Assembly Code Handling Interrupts: Assembly Code Step 1: Set up vector table.include "address_map_arm.s".include "defines.s".include "interrupt_id.s.section.vectors, "ax" B _start // reset vector B SERVICE_UND // undefined instruction vector B SERVICE_SVC // software interrrupt vector B SERVICE_ABT_INST // aborted prefetch vector B SERVICE_ABT_DATA // aborted data vector.word 0 // unused vector B SERVICE_IRQ // IRQ interrupt vector B SERVICE_FIQ // FIQ interrupt vector a : allocatable section (when loading) x : executable Step 2: Set stack pointers.text.global _start: _start: /* Set up stack pointers for IRQ and SVC processor modes */ MOV R1, #INT_DISABLE IRQ_MODE MSR CPSR_c, R1 // change to IRQ mode LDR SP, =A9_ONCHIP_END - 3 // set IRQ stack to top of A9 onchip memory /* Change to SVC (supervisor) mode with interrupts disabled */ MOV R1, #INT_DISABLE SVC_MODE MSR CPSR, R1 // change to supervisor mode LDR SP, =DDR_END - 3 // set SVC stack to top of DDR3 memory... define.s.equ IRQ_MODE, 0b10010.equ SVC_MODE, 0b equ INT_ENABLE, 0b equ INT_DISABLE, 0b text : executable by default 92

Handling Interrupts: Assembly Code Step 3: Enable interrupts BL CONFIG_GIC // configure the ARM generic interrupt controller // write to the pushbutton KEY interrupt mask register LDR R0, =KEY_BASE

#INT_ENABLE SVC_MODE // IRQ unmasked, MODE = SVC MSR CPSR_c, R0 IDLE: B IDLE Handling Interrupts: Assembly Code config_gic.s /* To configure the FPGA KEYS interrupt (ID 73): * 1.

4 Handling Interrupts: Assembly Code Step 3: Enable interrupts BL CONFIG_GIC // configure the ARM generic interrupt controller // write to the pushbutton KEY interrupt mask register LDR R0, =KEY_BASE // pushbutton key base address MOV R1, #0xF // enable interrupts from all four KEYs STR R1, [R0, #0x8] // interrupt mask register is (base + 8) // enable IRQ interrupts in the processor MOV R0, #INT_ENABLE SVC_MODE // IRQ unmasked, MODE = SVC MSR CPSR_c, R0 IDLE: B IDLE Handling Interrupts: Assembly Code config_gic.s /* To configure the FPGA KEYS interrupt (ID 73): * 1. set the target to cpu0 in the ICDIPTRn register (addr 0xFFFED848) * 2. enable the interrupt in the ICDISERn register (addr 0xFFFED108) */ CONFIG_GIC: LDR R0, =0xFFFED848 // ICDIPTRn: processor targets register LDR R1, =0x // set targets to cpu0 STR R1, [R0] LDR R0, =0xFFFED108 // ICDISERn: set enable register LDR R1, =0x // set interrupt enable STR R1, [R0]... (next slide) ICDIPTRn byte/id offset = interrupt ID ID 73 (0x49) offset 0x48, byte 1 ICDISERn offset ID (bit/id) 0x100 : x104 : x108 : /* configure the GIC CPU interface */ LDR R0, =MPCORE_GIC_CPUIF // base address of CPU interface /* Set Interrupt Priority Mask Register (ICCPMR) */ LDR R1, =0xFFFF // 0xFFFF enables interrupts of all priorities levels STR R1, [R0, #ICCPMR] /* Set the enable bit in the CPU Interface Control Register (ICCICR). * This bit allows interrupts to be forwarded to the CPU(s) */ MOV R1, #0x1 STR R1, [R0, #ICCICR] GIC distributor registers /* Set the enable bit in the Distributor Control Register (ICDDCR). This bit * allows the distributor to forward interrupts to the CPU interface(s) */ LDR R0, =MPCORE_GIC_DIST STR R1, [R0, #ICDDCR] BX LR 95 96

Handling Interrupts: Assembly Code CPU interface registers Step 4: Exception Handler SERVICE_IRQ: PUSH R0-R7, LR /* Read the ICCIAR from the CPU interface */ LDR R4, =MPCORE_GIC_CPUIF LDR R5, [R4,

5 Handling Interrupts: Assembly Code CPU interface registers Step 4: Exception Handler SERVICE_IRQ: PUSH R0-R7, LR /* Read the ICCIAR from the CPU interface */ LDR R4, =MPCORE_GIC_CPUIF LDR R5, [R4, #ICCIAR] // read the interrupt ID FPGA_IRQ1_HANDLER: CMP R5, #FPGA_IRQ1 UNEXPECTED: BNE UNEXPECTED // if not recognized, stop here BL KEY_ISR EXIT_IRQ: /* Write to the End of Interrupt Register (ICCEOIR) */ STR R5, [R4, #ICCEOIR] POP R0-R7, LR SUBS PC, LR, # Handling Interrupts: Assembly Code Step 5: Interrupt Service Routine (ISR) KEY_ISR: LDR R0, =KEY_BASE // base address of pushbutton KEY parallel port LDR R1, [R0, #0xC] // read edge capture register STR R1, [R0, #0xC] // clear the interrupt LDR R0, =KEY_HOLD // base address of pushbutton KEY parallel port LDR R2, [R0] // read global variable EOR R1, R2, R1 // toggle the bits of the global STR R1, [R0] // write to the global variable... (next slides).global KEY_HOLD KEY_HOLD:.word 0b0000 // remembers which KEY is pressed/not LDR R0, =HEX3_HEX0_BASE // based address of HEX display MOV R2, #0 // blank the display by default CHECK_KEY0: MOV R3, #KEY0 // KEY0=0b0001 ANDS R3, R3, R1 // check for KEY0 (bit 0) BEQ CHECK_KEY1 MOV R2, #0b // 0x3F (0) CHECK_KEY1: MOV R3, #KEY1 ANDS R3, R3, R1 // check for KEY1 (bit 1) BEQ CHECK_KEY2 MOV R3, #0b // 0x06 (1) ORR R2, R2, R3, LSL #8 CHECK_KEY2: MOV R3, #KEY2 ANDS R3, R3, R1 // check for KEY2 (bit 2) BEQ CHECK_KEY3 MOV R3, #0b // 0x5B (2) ORR R2, R2, R3, LSL #

Step 1-3: Create a New Project CHECK_KEY3: MOV R3, #KEY3 ANDS R3, R3, R1 // check for KEY3 (bit 3) BEQ END_KEY_ISR MOV R3, #0b01001111 // 0x4F (3) ORR R2, R2, R3, LSL #24 Create a new project Select

6 Step 1-3: Create a New Project CHECK_KEY3: MOV R3, #KEY3 ANDS R3, R3, R1 // check for KEY3 (bit 3) BEQ END_KEY_ISR MOV R3, #0b // 0x4F (3) ORR R2, R2, R3, LSL #24 Create a new project Select a system : DE1-SoC computer Program type : assembly program Files : multiple files END_KEY_ISR: STR R2, [R0] // display BX LR // Return BX : branch exchange instruction - branch 주소의 LSB 값에따라서다음명령어의동작모드결정 (0: ARM 모드, 1: Thumb 모드 ) Download the system Compile and Load Step 4: Notice the Starting Address Step 5: Look at the Vector Table

7 Step 6: Look at the Exception Handler Step 7: Look at the Interrupt Service Routine Step 8: Set a Breakpoint at the Beginning of the ISR Step 9: Single Step and Notice the Change of Mode

8 Step 10: Single Step and Notice the new Stack Pointer Step 11: Single Step and Notice the Change of Mode Step 12: Single Step and Notice the new Stack Pointer Step 13: Run the Program

Step 14: Single Step Through the ISR Step 15: See the value of the Edge Capture Register 113 114 Handling Interrupts: C Language Code Step 1: Set up vector table ( exception.

9 Step 14: Single Step Through the ISR Step 15: See the value of the Edge Capture Register Handling Interrupts: C Language Code Step 1: Set up vector table ( exception.c ) // Define the remaining exception handlers void attribute ((interrupt)) cs3_reset (void) while(1); Handling Interrupts: C Language Code Step 2: Set stack pointers inline assembly void set_a0_irq_stack(void) asm(instr : =out : in : clobbers); int stack, mode; // top of A9 onchip memory, aligned to 8 bytes stack = A9_ONCHIP_END - 7; void attribute ((interrupt)) cs3_isr_undef (void) while(1); void attribute ((interrupt)) cs3_isr_irq (void)... later /* change processor to IRQ mode with interrupts disabled */ mode = INT_DISABLE IRQ_MODE; asm("msr cpsr, %[ps]" : : [ps] "r" (mode)); /* set banked stack pointer */ asm("mov sp, %[ps]" : : [ps] "r" (stack)); /* go back to SVC mode before executing subroutine return! */ mode = INT_DISABLE SVC_MODE; asm("msr cpsr, %[ps]" : : [ps] "r" (mode));

10 Handling Interrupts: C Language Code Handling Interrupts: C Language Code Step 2: Enable interrupts void config_gic(void) int address; /* configure the FPGA KEYs interrupts */ *((int *) 0xFFFED848) = 0x ; *((int *) 0xFFFED108) = 0x ; // Set Interrupt Priority Mask Register(ICCPMR). address = MPCORE_GIC_CPUIF + ICCPMR; *(int *) address = 0xFFFF; // Enable interrupts of all priorities // Set CPU Interface Control Register (ICCICR). address = MPCORE_GIC_CPUIF + ICCICR; *(int *) address = 1; // Enable signaling of interrupts // Configure the Distributor Control Register (ICDDCR) to send // pending interrupts to CPUs address = MPCORE_GIC_DIST + ICDDCR; *(int *) address = 1; 117 Step 3: Exception Handler void attribute ((interrupt)) cs3_isr_irq (void) // Read the ICCIAR from the processor interface int address = MPCORE_GIC_CPUIF + ICCIAR; int int_id = *((int *) address); if (int_id == KEYS_IRQ) // check if interrupt is from the KEYs pushbutton_isr (); else while (1); // if unexpected, then stay here // Write to the End of Interrupt Register (ICCEOIR) address = MPCORE_GIC_CPUIF + ICCEOIR; *((int *) address) = int_id; return; 118 Handling Interrupts: C Language Code Handling Interrupts: C Language Code Step 4: Interrupt Service Routine (ISR) void pushbutton_isr( void ) volatile int * KEY_ptr = (int *) KEY_BASE; volatile int * HEX3_HEX0_ptr = (int *) HEX3_HEX0_BASE; int press, HEX_bits; pushbutton_isr.c main program #include "address_map_arm.h" void set_a9_irq_stack (void); void config_gic (void); void config_keys (void); void enable_a9_interrupts (void); press = *(KEY_ptr + 3); *(KEY_ptr + 3) = press; press ^= KEY_hold; KEY_hold = press; // read the pushbutton interrupt register // Clear the interrupt // toggle the bits using KEY_hold // save for next time a KEY is pressed int main(void) set_a9_irq_stack (); config_gic (); config_keys (); // initialize the stack pointer for IRQ mode // configure the general interrupt controller // configure pushbutton KEYs to generate interrupts HEX_bits = 0; // display "blank" by default if (press & KEY0) HEX_bits = 0b ; if (press & KEY1) HEX_bits = 0b << 8; if (press & KEY2) HEX_bits = 0b << 16; if (press & KEY3) HEX_bits = 0b << 24; *HEX3_HEX0_ptr = HEX_bits; return; enable_a9_interrupts (); // enable interrupts in the A9 processor while (1) // wait for an interrupt ;

11 Step: Choose the Exceptions Memory Settings /* setup the KEY interrupts in the FPGA */ void config_keys() volatile int * KEY_ptr = (int *) KEY_BASE; *(KEY_ptr + 2) = 0xF; // enable interrupts for all four KEYs Step 4: Look at the Exception Handler Step 5: Set a Breakpoint at the Interrupt Service Routine

12 Step 6: Set a Breakpoint and Run to the Main Function Step 7: Single Step through Setting the Stack Pointers Step 8: Run the Program 127

DE1-SoC Computer System with ARM Cortex-A9. 1 Introduction. 2 DE1-SoC Computer Contents. 2.1 Hard Processor System. For Quartus Prime 16.

DE1-SoC Computer System with ARM Cortex-A9 For Quartus Prime 16.1 1 Introduction This document describes a computer system that can be implemented on the Intel DE1-SoC development and education board.