Embedded Seminar in Shenzhen

Transcription

1 in Shenzhen 1

2 hello world PC HELLO WORLD IDE Simulator - C 2 2

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4 Architecture 6 Halfword and signed halfword / byte support System mode Thumb instruction set 4 4T Improved /Thumb Interworking CLZ Saturated arithmetic 5TE DSP multiply-accumulate instructions 5TEJ SIMD Instructions Multi-processing V6 Memory architecture (VMSA) Unaligned data support 6T2 Thumb-2 instruction set 7A Applications profile 7R Real-Time profile Jazelle Java bytecode execution 6Z 7M TrustZone AOS extensions(v6k) Microcontroller profile 4 4

5 32. : Byte Halfword Word 8 bits 16 bits (2 bytes) 32 bits (4 bytes) core 32-bit Thumb 16-bit Jazelle cores Java byte 5 5

6 Privileged modes Aborts Interrupts Reset OS S/W Interrupt (SWI) Undefined Instruction User mode Application code xyz Memory Instructions & Data 6 6

7 7 : User : FIQ : IRQ : fast) normal) Un-privileged Privileged Supervisor : Abort : (memory access violations) Undef : System : User 7 7

8 37 32-Bits. 1 PC (program counter) 1 CPSR (current program status register) 5 SPSR (saved program status registers) 30. r0-r12 r13 (the stack pointer, sp) and r14 (the link register, lr) r15 (the program counter, pc) CPSR (current program status register, cpsr) ( system ) SPSR (saved program status register) 8 8

9 User mode IRQ FIQ Undef Abort SVC r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) Note: System mode uses the User mode register set. r13 (sp) r14 (lr) r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) cpsr spsr spsr spsr spsr spsr Current mode Banked out registers 9 9

10 NZ C V Q IT[1:0] IT[7:2] J GE[3:0] E A I F T mode f s x c Q N = Negative result from ALU Z = Zero result from ALU C = ALU operation Carried out V = ALU operation overflowed 5TE/J I = 1: F = 1: T Bit xt T = 0: T = 1: IRQ. FIQ. Thumb J 5TE/J J = 1: Jazelle Mode v6 GE[3:0: ]: SIMD E: endian A: Abort IF[7:0]: Thumb-2 IT v6 undefined

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12 ROM or RAM at 0x0? 0x0 0x18000 ROM at 0x0 ROM/RAM Remapping 0x18000 RAM ROM 0x x10000 Reset Handler 0x4000 0x4000 ROM 0x0000 Reset Handler Vectors Aliased RAM ROM 0x0000 Reset Handler Vectors RESET HANDLER 12 12

13 -GCC _start main { } gccmain() C 13 13

14 - C Library User Code main copy code and data zero uninitialized data rt_entry set up application stack and heap initialize library functions call top-level constructors (C++) main( ) causes the linker to pull in library initialization code Exit from application 14 14

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16 0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00 FIQ IRQ (Reserved) Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset Vector Table Vector table can be at 0xFFFF0000 on 720T and on 9/10 family devices 16 16

17 The Vector Table AREA Vectors, CODE, READONLY IMPORT Reset_Handler ; import other exception handlers ; ENTRY B Reset_Handler B Undefined_Handler B SWI_Handler B Prefetch_Handler B Data_Handler NOP B ; Reserved vector IRQ_Handler ; FIQ_Handler will follow directly END ENTRY scatterloading+first 0X0 0xFFFF

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20 char short int long float double pointer long long bool wchar_t 8 bit byte 16 bit half-word 32 bit word 32 bit integer 32 bit IEEE 64 bit IEEE 32 bits 64 bit integer 8 bit byte 32 bit word char pointer 20 20

21 C PC 21 21

22 model) stack heap (one-region (two-region model) Stack SB Heap heap is checked against heap limit HL HB Heap One region model heap is checked against stack pointer HB Stack Two region model SB (SL) -apcs /swst ( two-region ) use_two_region_memory 22 22

23 -- 0x8000 Stack heap Heap (malloc,alloc) Startup Code ulator => from configuration file (peripherals.ami) default = 0x C Multi-ICE => from debugger internal variable $top_of_memory default = 0x80000 ZI RW RO 0x

24 --GCC.TEXT.DATA.BSS RAM/DRAM/SDRAM.STACK.BSS.DATA.DATA RO.RODATA.TEXT 24 24

25 CODE DATA RO RW RW ZI CODE DATA :, LINK eg: armlink file1.o file2.o ZI RW RO RO -DATA RO -CODE B A section A from file2.o section A from file1.o 25 25

26 Scatter Loading 0x8000 eg: armlink program.o -scatter scatter.scf -o program.axf 26 26

27 0x18000 RAM Load View Fill with zeros Execute View ZI 0x18000 RAM 0x10000 RW 0x x4000 Copy 0x4000 ROM RW ROM 0x0000 RO RO 0x0000 ROM C ( main) : ROM RW RAM RAM ZI 27 27

28 0x Peripherals 0x Flash 0x x bit RAM 0x x4000 Fast 32 bit RAM 0x0000 RO Reset Handler Heap RW & ZI Stack Exception Handlers Vector Table FLASH 16 RAM HEAP RAM 28 28

29 IMPORT Image$$RO$$Base IMPORT Image$$STACK$$ZI$$Base IMPORT Image$$RW$$Base IMPORT Image$$RW$$Limit code_base DCD Image$$RO$$Base stack_base DCD Image$$STACK$$ZI$$Base data_base DCD Image$$RW$$Base data_limit DCD Image$$RW$$Limit.extern Image_RO_Base.extern Image_RO_Limit.extern Image_RW_Base.extern Image_ZI_Base.extern Image_ZI_Limit.equ code_base,image_ro_base.equ stack_base, Image_ZI_Limit.equ data_base, Image_RW_Base.equ data_limit, Image_ZI_Limit ldr ldr r1,=code_base r3,=data_limit 29 29

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31 reset handler reset handler IMPORT main B main C caches 31 31

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33 Main( ) Rtos_Init( ) MyRoot( ) 33 33

34 Bootloader 1-2 BSP (Board Support Package) BIOS 34 34

35 C Library main copy code and data zero uninitialized data User Code reset handler initialize stack pointers configure MMU/MPU setup cache/enable TCM Image Entry Point rt_entry initialize library functions call top-level constructors (C++) Exit from application user_initial_stackheap( ) set up stack & heap $Sub$$main( ) enable caches & interrupts main( ) tells linker to link in library initialization code 35 35

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