CS 310 Embedded Computer Systems CPUS. Seungryoul Maeng

Transcription

1 1 EMBEDDED SYSTEM HW CPUS Seungryoul Maeng

2 2 CPUs Types of Processors CPU Performance Instruction Sets Processors used in ES

3 3 Processors used in ES

4 4 Processors used in Embedded Systems RISC type ARM Architecture, Intel XScale Architecture, IBM PowerPc Architecture Super scalar implementation CISC type Intel x86 architecture Super scalar implementation VLIW TI TMS320C6x (DSP) Single Purpose Processors discussed in the previous section

5 ARM Architecture Advanced RISC Machines(1990) (ACORN and Apple Computer)

6 ARM Architecture 6 ARM Processors 32-bit embedded RISC processors Wide range of processors Embedded processors Embedded d real-time systems for storage, automobile, industry and networking applications Application processors Devices running open operating systems including Linux, Symbian OS, and Windows CE in many applications Secure applications Smart cards, SIM cards and payment terminals

7 7 ARM Processor Instruction Set Architecture t ARM architecture has been extended over several versions

8 8 Evolution of the ARM architecture versions ARMv4 Implementations ARM7 processor family and Intel StrongARM processors ARMv4T 16-bit Thumb instruction set is added for compact code generation (memory saving of up to 35% over the equivalent 32-bit code) ARMv5TE ARM Enhanced DSP instruction set extensions Up to 70% performance improvement for audio DSP applications VFP- vector floating point coprocessor Implementations ARM9, ARM10 processors

9 9 Evolution of the ARM architecture versions ARMv5TEJ Jaxelle technology extension to support Java acceleration technology ARMv6 SIMD ARM1136 processor in 2002, ARM1156T2,.. ARMv7 Thumb-2 technology NEON technology DSP and medial processing Implementations Cortex family ARM Cortex-A8 processor ARM s first superscalar processor

10 Evolution of the ARM architecture 10 ARM11

11 Introduction to ARM ISA 11 To allow very small, yet high-performance implementations RISC Large uniform register file Load/store architecture Simple addressing modes Uniform and fixed-length instr fields Auto-increment and auto-decrement addr modes Conditional execution of all instructions

12 Extension of the RISC rules 12 High code density, low power, and small die size Variable cycle execution Multiple load and store Improve code density, reduce Ifs, and reduces overall power consumption Inline barrel shifter Conditional execution 16-bit Thumb instruction set Enhance DSP instructions 16X16 multiply, arithmetic saturation DSP-specific routines

13 ARM assembly language 13 Fairly standard assembly language: label LDR r0,[r8] ; a comment ADD r4,r0,r1 r0 r1

14 Programming Model

15 ARM data types 15 Bt Byte : Halfword : 16 bits Must be aligned to two-byte boundaries Word : 32 bits Must be aligned to four-byte boundaries ARM addresses can be 32 bits long. Address refers to byte. Address 4 starts at byte 4. Can be configured at power-up as either little- or bit-endian mode.

16 Processor modes 16 User: usr Normal program execution modes FIQ: fiq Supports a high-speed data transfer or channel process IRQ: irq Used for general-purpose interrupt handling Supervisor: svc A protected mode for OS Abort: abt Implements VM and/or memory protection Undefined: und Supports software emulation of HW coprocessors System: sys Runs privileged OS tasks fiq, irq, svc, abt, und exception modes

17 Registers 17 r0 r1 r2 r3 r4 r5 r6 r7 unbanked registers r8 r9 r10 r11 CPSR r12 r13 r14 N Z C V r15 (PC) banked registers 31 0 Link register

18 18

19 Endianness 19 Relationship between bit and byte/word ordering defines endianness: bit 31 bit 0 bit 0 bit 31 byte 3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte 3 little-endian big-endian

20 ARM status bits 20 Every arithmetic, logical, or shifting operation may set CPSR (current program statues register) bits: N (negative), Z (zero), C (carry), V (overflow). Examples: = 0: NZCV = = : NZCV = 1001.

21 21 ARM data processing operand addressing Instruction syntax <opcode>{<cond>}{s} } <Rd>, <Rn>, <shifter-operand> <shifter-operand> has 11 options

22 Condition field 22 Almost all ARM instrs. conditionally executed

23 23 ARM data processing operand addressing Data processing immediate shift cond 000 opcode S Rn Rd shift amount shift 0 Rm Data processing register shift cond 000 opcode S Rn Rd Rs 0 shift 1 Rm Data processing 32-bit immediate cond 001 opcode S Rn Rd rotate immediate-8

24 Shifter operand 24 Immediate 8-bit constant and a 4-bit rotate (0,2,4,8,,30) mov r0, #0 add r9, r9,#1 Register operand mov r2, r0 Shifted register operand ASR, LSL, LSR, ROR, RRX (by one bit) mov r2, r0, LSL #2 ; shift r0 left by 2, write to r2 (r2=r0x4) sub r10,r9,r8, LSR #4 ; r10 = r9 - r8/16 sov r10,r9,r8, ROR r3 ; r10 = r9 - (r8 rotated by value of r3)

25 ARM data-processing 25 AND TST : update flags after Rn EOR AND shifter operand SUB : Rd:= Rn - shifter TEQ operand CMP RSB : Rd:= shifter operand - Rn ADD ADC (with carry) SBC RSC (reverse SBC) CMN: copmare negated ORR (logical OR) MOV BIC MVN (mov not)

26 ARM data-processing 26 Shift, Rotate? shifter-operand LSL, LSR : logical shift left/right ASR : arithmetic shift left/right ROR : rotate right RRX : rotate right extended with C

27 Data operation varieties 27 Logical shift: fills with zeroes. Arithmetic shift: fills with sign extension RRX performs 33-bit rotate, including C bit from CPSR above sign bit.

28 Load and Store instructions 28 Two types 32-bit word or an 8-bit unsigned byte Load and store halfword and load signed byte Addressing modes Base register Any one of GPR (including the PC) Offset Three format

29 Addressing modes 29 Offset Immediate: unsigned number (12 bits or 8 bits) Register: GPR (not the PC) Scaled register: shifted by an immediate value LSL, LSR, ASR, ROR, RRX Three ways to form the memory address EA := Base register + or Offset Offset Pre-indexed Post-indexed

30 Addressing modes 30 Base-plus-offset addressing: LDR r0,[r1,#16] Loads from location r1+16 Pre-indexing increments base register: LDR r0,[r1,#16]! Post-indexing fetches, then does offset: LDR r0,[r1],#16 Loads r0 from r1, then adds 16 to r1.

31 Load and store 31 LDR STR LDRB STRB LDRH STRH LDRSB (signed byte) LDRSH (signed halfw)

32 Examples 32 LDR R1, [R0] ; load R1 from the address in R0 LDR R8, [R3, #4] ; EA = [R3] + 4 LDR R8, [R3, #-4]; EA = [R3] 4 STRB R10, [R7, -R4] ; EA = [R7] [R4] LDR R11, [R3, R5, LSL #2] ; EA = [R3] + ([R5]x4) LDR R3, [R9], #4 ; EA = [R9], R9 = [R9] +4 post-indexed LDR R1, [R0, #2]! ; EA = [R0]+2, R0=[R0]+2 pre-indexed LDR R0, [PC, #40] ; load R0 from PC+0x40 (= address of the ; instruction x40)

33 Load and store multiple 33 Addressing modes IA : increment after IB : increment before DA: decrement after DB: decrement before

34 Load and store multiple 34 LDM STM Examples LDMIA r0,,{r5 r8} ; load multiple r5-r8 from ; the address in r0 STMDA r1!, {r2, r5, r7 r9, r11} ; update r1

35 Branch instructions 35 Conditional branch forwards or backwards up to 32 MB Sign-extending the 24-bit imm_data to 32 bits Shifting the result left two bits Adding this to the PC (the addr of branch +8) Approximately ± 32MB B, BL

36 Examples 36 B label l BCC label ; branch if carry flag is clear BEQ label ; if zero flag is set MOV PC, #0 ; branch to location zero BL func ; subroutine call MOV PC,LR ; return MOV LR, PC LDR PC, =func ;

37 ARM ADR pseudo-opop 37 Cannot refer to an address directly in an instruction. Generate value by performing arithmetic on PC. ADR pseudo-opop generates instruction required to calculate address: ADR r1,foo

38 Examples 38 start t MOV r0, #10 ADR r4, start; => SUB r4,pc,#0xc start = pc = pc - 12 = pc - 0xc

39 Summary 39 Load/store architecture Most instructions are RISCy, operate in single cycle. Some multi-register operations take longer. All instructions can be executed conditionally.

40 Intel XScale Architecture Designed to optimize low-power consumption and high performance (Core: ARMv5TE)

41 RISC XScale Microarchitecture coac tectuefeatures es 41 Modified Harvard Architecture instruction cache and data cache (2 caches) 32KB Instruction Cache 32KB Data Cache Intel Media Processing Technology Instruction and Data Memory Management Unit Branch Target Buffer Debug Capability via JTAG Port Implementations: PXA250, PXA255 processors 0.35μm 3 Layer metal CMOS, 2.6 million transistor 256 PBGA package (17 x 17mm) Intel s Xscale PXA mobile processor line was sold to Marvell Technology on Nov

42 42 RISC XScale System Integration Features Memory controller Power management controller Normal, idle, sleep mode support USB client Multi channel DMA controller LCD controller AC97 codec Multimedia card: serial interface to standard d memory card, FIFO FIR communication Synchronous serial protocol port I 2 C

43 Internal Structure 43

44 Design example 44 Palm size device - Example

45 45 Intel Atom Processor Low-power Intel IA-32 micro- architecture specially designed for the new class of Mobile Internet Devices

46 Features 46 Intel Atom processor N GHz core speed 2.5 Watts 45nm process technology SIMD extensions

47 47 Intel Integrated Processors Complete SOC for security, communications, storage and embedded designs

48 Features 48 SOC processors Integrated memory controller, I/O controller, three Ethernet interfaces, two CANs, and so on

49 49 TI TMS320C62x DSP TMS320C62x DSP: fixed-point DSP TMS320C64x DSP: floating-point DSP Multiprocessor DSPs

50 Overview 50 High performance Up to 8000 MIPS An efficient i C compiler Ease of use Applications Modems Wireless local loop base stations GPS Remote medical diagnostics 3-D graphics Audio Imaging g

51 Features 51 VLIW architecture t Up to 8 32-bit instructions 32 GP 32-bit registers and 8 functional units Two multipliers Six ALUs Instruction Packing Gives code size equivalence for 8 instructions executed serially or in parallel l Reduces code size, program fetches, and power consumption Conditional execution of all instructions Reduce costly branching

52 Architecture 52 Program Memory/Cache 256-bit (8x32) Data Memory 8-, 16-, 32-bit data Two ports memory CPU Program fetch unit Instruction Dispatch unit Decode unit Two data paths bit registers Power down logic Reduced clocking to reduce power consumption

53 TMS320C62x CPU Data Paths 53

54 54 Functional Units and Operations Performed

55 Basic Format of a Fetch Packet 55 Fetched 8 words at a time Aligned on 256-bit(8-word) boundaries If p=1, instruction i+1 is to be executed in parallel If p=0, instruction i+1 is executed in the cycle after instruction I Last p-bit is always cleared to 0

56 Example of Execution Pattern 56

57 For more detailed information 57 ARM architectures Intel architectures p p =subhdr+prod_proc sprocessors/ htm TI DSP