Boot Loader of Creator S3C4510 張大緯 CSIE, NCKU

Transcription

1 Boot Loader of Creator S3C4510 張大緯 CSIE, NCKU

2 What s a Boot Loader? Booting Process on a PC Power on > BIOS > boot loader in MBR (Master Boot Record) > Operating System > User Applications Booting Process on an Embedded Device Power on > [ROM startup code >] boot loader in ROM [ > Operating System ] > User Applications Load the OS or the User Applications

3 The Jobs of a Boot Loader Hardware Initialization Load OS/Applications Jump to OS/Applications

4 Hardware Initialization Memory System Interrupt Vectors Stacks

5 Memory System Initialization When Reset, only the first bank (bank0) of the ROM is enabled

6 Memory System Initialization The system manager registers (see next slide) have to be set up before accessing RAM. Setup the Target Memory Map E.g., 0 32M DRAM 64M 66M ROM 68M 69M system registers 127M 128M IO

7 The System Manager Registers

8 System Configuration Register

9 Setup of SYSCFG.equ CACHE_DISABLE, 0.equ CACHE_ENABLE, Define constants.equ fields.equ SYS_CE,CACHE_DISABLE.equ SYS_WE,0.equ SYS_CM, 0 Kbyte SRAM, 8 Kbyte cache.equ SYS_SRAM_SADDR, Internal SRAM Start Address = 0x3FE0000.equ SYS_SFR_SADDR, SFR Start Address = 0x3FF0000.equ SYS_PD_ID, KS32C50100.equ SYS_SDM, 1 = Sync. DRAM interface for 4 DRAM banks

10 Clock Control Register (CLKCON)

11 Setup of CLKCON.equ CLK_DIVIDING, division.equ CLK_R5WAIT, Disable.equ CLK_R5MUX, Normal operation.equ CLK_TAC, 1 MCLK Refer to the datasheet

12 External IO Access Control Registers (EXTACON 0/1)

13 A Timing Example

14 Setup of EXTACON 0/1.equ IO0_TCOS, 2.equ IO0_TACS, 2.equ IO0_TCOH, 2.equ IO0_TACC, 5.equ IO1_TCOS, 7.equ IO1_TACS, 7.equ IO1_TCOH, 7.equ IO1_TACC,7.equ IO2_TCOS,7.equ IO2_TACS, 7.equ IO2_TCOH, 7.equ IO2_TACC,7.equ IO3_TCOS,7.equ IO3_TACS,7.equ IO3_TCOH,7.equ IO3_TACC,7

15 Data Bus Width Register (EXTDBWTH) ROM /FLASH /SRAM Bus width for each bank DRAM EXTIO

16 Setup of EXTDBWTH.equ BUS_DISABLE, Definition.equ DW8, 8 bits.equ DW16, bits.equ DW32, bits.equ R0_BWSCON, (DW16).equ R1_BWSCON, (BUS_DISABLE).equ R2_BWSCON,(BUS_DISABLE).equ R3_BWSCON,(BUS_DISABLE).equ R4_BWSCON, (DW32).equ R5_BWSCON,(DW32).equ DR0_BWSCON,(DW32).equ DR1_BWSCON,(BUS_DISABLE).equ DR2_BWSCON, (BUS_DISABLE).equ DR3_BWSCON, (BUS_DISABLE).equ IO0_BWSCON, (DW16).equ IO1_BWSCON, (DW16).equ IO2_BWSCON,(DW16).equ WIDTH

17 ROM/SRAM/FLASH Control Register (ROMCON)

18 Setup of ROMCON0 : 0x after R0_PMC, 0.equ R0_TPA,0.equ R0_TACC,4.equ R0_SADDR, 0x180.equ R0_NSADDR, Normal 5 5 Start Address = End Address = 0x01A00000 ROMCON1 : 0x after R1_PMC, Normal R.equ R1_TPA, 5 cycles.equ R1_TACC, 7 cycles.equ R1_SADDR, Start Address = 0.equ R1_NSADDR, Next R ~5 have the same settings as ROMCON1

19 DRAM Control Register (DRAMCON)

20 Setup of DRAMCON0 : 0x after Reset.equ DR0_EDO, EDO.equ DR0_TCS, 1 cycle.equ DR0_TCP, 1 cycle.equ DR0_TRC, 1 cycle.equ DR0_TRP, 4 cycles.equ Start Address = 0x equ DR0_NSADDR, End Address = 0x DRAMCON1 : 0x after Reset.equ DR1_EDO, DR1_TCS, DR1_TCP, DR1_TRC, DR1_TRP, DR1_SADDR, DR1_NSADDR, DRAMCON2~3 have the same settings as DRAMCON1

21 DRAM Refresh and External IO Control Register (REFEXTCON)

22 Setup of REFEXTCON.equ REF_SADDR, 0x3F0.equ Accessible to memory bank.equ Enable DRAM refresh.equ 5 cycles (CAS hold time).equ 1 cycles (CAS setup time).equ REF_CNT, Refresh count value

23 Interrupt Initialization Two kinds of interrupts IRQ(normal interrupt request) FIQ(fast interrupt request) 21 interrupt sources are supported by S3C4510B Interrupt related registers mode, priority, mask, pending registers

24 Interrupt Sources and FIQ/IRQ Modes

25 Stack Initialization ARM has 6 modes Each mode can have its own stack Usually, we set up stacks for the following four modes USR SVC IRQ FIQ

26 Introduction to the Boot Loader Code

27 Addresses of System Manager Registers #define BASE_ADDR #define SYSCFG #define CLKCON #define EXTACON0 #define EXTACON1 #define EXTDBWTH #define ROMCON0 #define ROMCON1 #define ROMCON2 #define ROMCON3 #define ROMCON4 #define ROMCON5 #define DRAMCON0 #define DRAMCON1 #define DRAMCON2 #define DRAMCON3 #define REFEXTCON 0x3FF0000 (BASE_ADDR+0x0000) (BASE_ADDR+0x3000) (BASE_ADDR+0x3008) (BASE_ADDR+0x300C) (BASE_ADDR+0x3010) (BASE_ADDR+0x3014) (BASE_ADDR+0x3018) (BASE_ADDR+0x301C) (BASE_ADDR+0x3020) (BASE_ADDR+0x3024) (BASE_ADDR+0x3028) (BASE_ADDR+0x302C) (BASE_ADDR+0x3030) (BASE_ADDR+0x3034) (BASE_ADDR+0x3038) (BASE_ADDR+0x303C) You can find the definitions in 4510addr.h, but there is a more clear definition in gnu/config.h

28 Data for System Manager Registers (1/3) SMRDATA:.long ((SYS_SDM<<31)+(SYS_PD_ID<<26)+(SYS_S FR_SADDR<<16)+(SYS_SRAM_SADDR<<6) +(SYS_CM<<4)+(SYS_WE<<2)+(SYS_CE<<1) +(SYS_SE)).long ((CLK_TAC<<18)+(CLK_R5MUX<<17)+(CL K_R5WAIT<<16)+(CLK_DIVIDING)) For SYSCFG and CLKCFG

29 Data for System Manager Registers (2/3) SMRDATA1:.long ((IO1_TACC<<25)+(IO1_TCOH<<22)+(IO1_TACS<<19) +(IO1_TCOS<<16)+(IO0_TACC<<9)+(IO0_TCOH<<6)+( IO0_TACS<<3)+(IO0_TCOS)).long ((IO3_TACC<<25)+(IO3_TCOH<<22)+(IO3_TACS<<19) +(IO3_TCOS<<16)+(IO1_TACC<<9)+(IO1_TCOH<<6)+( IO1_TACS<<3)+(IO1_TCOS)).long ((IO3_BWSCON<<26)+(IO2_BWSCON<<24)+(IO1_BW SCON<<22)+(IO0_BWSCON<<20)+(DR3_BWSCON<<1 8)+(DR2_BWSCON<<16)+(DR1_BWSCON<<14)+(DR0_ BWSCON<<12)+(R5_BWSCON<<10)+(R4_BWSCON<< 8)+(R3_BWSCON<<6)+(R2_BWSCON<<4)+(R1_BWSC ON<<2)+(R0_BWSCON)) For EXTACON 0,1 and EXTDBWTH

30 Data for System Manager Registers (3/3) SMRDATA2:.long ((R0_NSADDR<<20)+(R0_SADDR<<10)+(R0_TACC<<4)+(R0_TPA<<2)+R0_PMC).long ((R1_NSADDR<<20)+(R1_SADDR<<10)+(R1_TACC<<4)+(R1_TPA<<2)+R1_PMC).long ((R2_NSADDR<<20)+(R2_SADDR<<10)+(R2_TACC<<4)+(R2_TPA<<2)+R2_PMC).long ((R3_NSADDR<<20)+(R3_SADDR<<10)+(R3_TACC<<4)+(R3_TPA<<2)+R3_PMC).long ((R4_NSADDR<<20)+(R4_SADDR<<10)+(R4_TACC<<4)+(R4_TPA<<2)+R4_PMC).long ((R5_NSADDR<<20)+(R5_SADDR<<10)+(R5_TACC<<4)+(R5_TPA<<2)+R5_PMC).long ((DR0_NSADDR<<20)+(DR0_SADDR<<10)+(DR0_TRP<<8)+(DR0_TRC<<7)+(DR0_TCP<<3)+( DR0_TCS<<1)+DR0_EDO).long ((DR1_NSADDR<<20)+(DR1_SADDR<<10)+(DR1_TRP<<8)+(DR1_TRC<<7)+(DR0_TCP<<3)+( DR1_TCS<<1)+DR1_EDO).long ((DR2_NSADDR<<20)+(DR2_SADDR<<10)+(DR2_TRP<<8)+(DR2_TRC<<7)+(DR0_TCP<<3)+( DR2_TCS<<1)+DR2_EDO).long ((DR3_NSADDR<<20)+(DR3_SADDR<<10)+(DR3_TRP<<8)+(DR3_TRC<<7)+(DR0_TCP<<3)+( DR3_TCS<<1)+DR3_EDO).long ((REF_CNT<<21)+(REF_TCSR<<20)+(REF_TCHR<<17)+(REF_REN<<16)+(REF_VSF<<15)+REF _SADDR) For ROMCON, DRAMCON, and REFEXTCON

31 So, we introduce the code now

32 The Exception Vectors <= The Entry Point LDR PC, Addr_Reset LDR PC, Addr_Undefined LDR PC, Addr_Swi LDR PC, Addr_Prefetch LDR PC, Addr_Dabort LDR PC, Addr_IRQ LDR PC, Addr_FIQ

33 Go to the Reset Handler Addr_Reset:.long ResetHandler all the interrupts LDR of the intmsk LDR interrupt disable STR r1,[r0]

34 The Interrupt Mask Register 1: disabled, 0 : enabled G: the global bit

35 Apply SMDATA and memory control registers LDR r0,=smrdata LDR Address LDR r3, [r0], the value, inc the addr STR r3, [r1], the value to the reg LDR Address LDR r3, [r0], #4 STR r3, [r1], #0 LDR R0,=SMRDATA1 LDMIA R0,{R1 R3} LDR R0,=EXTACON0 STMIA R0,{R1 R3}

36 .ifdef LOADER Copy Data from ROM to RAM if Needed LDR R0,=LOADER_MAP LDMIA R0,{R1 R11} LDR R0,=ROMCON0 STMIA R0,{R1 vs. 0~ about ~ 2ff0000 LDR LDR is about 2M LDR : Relocate: LDR R3,[R0],#4 STR R3,[R2],#4 SUBS R1,R1,#4 BNE Relocate.endif

37 Setup the Target Memory Map LDR R0,=SMRDATA2 LDMIA R0,{R1 R11} LDR R0,=ROMCON0 STMIA R0,{R1 R11}

38 Clear the BSS Section /* Clear BSS */ 1: ldr r3, =_sbss ldr r1, =_ebss mov r2, #0 2: cmp r3, r1 strcc r2, [r3], #4 /* unsigned lower */ bcc 2b /* branch when unsigned lower */

39 Setup Exception Handlers In current implementation, only the following 2 handlers are used (except the Reset Handler) IRQ Handler SWI Handler Handlers are surrounded by Macros

40 Macros A little bit like Functions Macros Text Replacement Macro Invocation vs. Function Invocation

41 Exception Handler Macro.macro HANDLER HandleLabel SUB sp, sp, #4 STMFD sp!,{r0} ; save R0 LDR r0,=\handlelabel LDR r0,[r0] STR r0,[sp,#4] ; push ISR addr LDMFD sp!,{r0,pc} ; restore R0 and jump to ISR.endm Others.. SP Handler addr r0

42 Others.. SP Others.. Handler addr Others.. SP r0 SP Others.. Others.. SP r0 SP

43 Macro Invocation HandlerIRQ: HANDLER pisr_irq HandlerIRQ: SUB sp,sp,#4 STMFD sp!,{r0} ; save R0 LDR r0,=pisr_irq LDR r0,[r0] STR r0,[sp,#4] ; push ISR addr LDMFD sp!,{r0,pc} ; restore R0 and jmp to ISR So, we should put the REAL address of the IRQ handler on pisr_irq!!!

44 Setup the Two Exception Setup IRQ handler LDR r0,=pisr_irq LDR r1,=isrirq STR Setup SWI handler LDR r0,=pisr_swi LDR r1,=isrswi STR IRQ handler SWI handler function

45 Setup Stacks for Privileged Modes Setup the stacks for IRQ and FIQ Idea: change to that mode and set register SP see next 2 slides MRS cpsr to r0 BIC the mode bits ORR r1,r0,#irq_mode IRQ mode and clear IRQ/FIQ MSR to IRQMode LDR the stack of IRQmode But, where are the IRQ_STACK and FIQ_STACK?

46 ARM Program Status Register For NOINT

47 The Mode Bits.equ USER_MODE,.equ FIQ_MODE,.equ IRQ_MODE,.equ SVC_MODE,.equ ABORT_MODE,.equ UNDEF_MODE,.equ MODE_MASK,0x1f 0x10 0x11 0x12 0x13 0x17 5 bits for modes.equ interrupts

48 Part of the Linker Script.stack 0x : { /* stack base (the highest address) : 16M */ _USR_STACK =.; /* User STACK */ _IRQ_STACK =. - 0x1000; / * IRQ stack shares with FIQ stack */ _FIQ_STACK =. - 0x1000; } stack_limit =. - 0x1000;

49 Change to SVC Mode mrs r0, cpsr bic r0, r0, defined in config.h (= MODE_MASK) orr r0, r0, = SVC_MODE bic IRQ and FIQ msr cpsr, to SVC mode ldr sp, mode also uses _USR_STACK

50 Load OS/Application If the OS/Applications are linked with the boot loader, it is not necessary to load them again Otherwise, they should be loaded and may be decompressed checked.

51 Jump to OS/Application Branches to the entry point of the OS Or, the entry point of the application Usually, the main() function

52 Branch to the C main Function One Approach 3: /*An embedded system should never return, if it does return then run it again*/ bl main /* should never return */ b 3b Another Approach 3: /*Halt if it does return */ bl main /* should never return */ 4: b 4b

53 The Main Function int main(void) { //USER PROGRAM INTERFACE //... //... Usually, there is a infinite loop // here } return(0);