How to implement an EtherCAT Slave Device

Transcription

1 How to implement an EtherCAT Slave Device

2 Agenda 1. Overview 2. Slave Overview 3. First Steps: 4. Hardware Design 5. Software Development 6. Testing 7. and how to avoid them 8. 2

3 Overview EtherCAT Master EtherCAT Network Information File (ENI) EtherCAT Configuration Tool *.xml Information File (ESI) *.xml Information File (ESI) *.xml Information File (ESI) *.xml NW Interface NW Interface NW Interface 3

4 Overview EtherCAT Master EtherCAT Network Information File (ENI) *.xml Device Application / Application Layer EtherCAT LEDs ESC / Data Link Layer RJ45 Magnetic Network Interface / Physical Layer µc or dig. I/O Interface Controller (ESC) PHY EtherCAT Configuration Tool Data Interface (PDI) PHY I 2 C Magnetic Individual HW/SW EEPROM (ESC config. Data) RJ45 Information Files (ESI) *.xml *.xml µc / I/O ESC 4

5 Slave ETG Support Device Requirements NW Interface ETG Membership 1) ETG Vendor ID 1) Development Toolkit EtherCAT Training + Workshops 2) EtherCAT Feature Configuration / ESC Hardware Development EEPROM µc & PDI Synchronization HW / SW Aspects Communication Protocols Software Development Device Profiles CTT License 1) Lab Wiring with µc ETG.2200 Guide 1) mandatory step for selling EtherCAT Devices 2) optional, but recommended 5

6 First: Define / Select: 1. Fully integrated Design or Interfacing Device 2. Hardware 1. NW Interface Hardware 2. ESC, EEPROM 3. µc, PDI 3. Device Profile 4. Parameter + Data 5. Synchronization and Time Stamping Requirements 6

7 Fully Integrated or Interfacing Device? Fully integrated PRO: Lower hardware costs Most flexible solution Full control of all features CONTRA: Higher development costs PRO: Interfacing device Lower development costs Time to market Less network know-how required CONTRA: Higher hardware costs Form factor restrictions 7

8 Hardware Fully integrated Design*: Application Layer Data Link Layer Physical Layer Device Application ESC EtherCAT LEDs RJ45 Magnetic Network Interface µc or dig. I/O Interface Controller (ESC) PHY Data Interface (PDI) PHY I 2 C Magnetic EEPROM (ESC config. Data) * Interfacing Device Hardware : No generic rules due to the diverse architectures of the various solutions RJ45 8

9 Hardware Simple (digital I/O) Devices do not require a µc Tasks of Host µc in more complex devices: data Exchange with the Application Object Dictionary Handling Handling of Application Parameter (Communication Parameter are handled by ESC) TCP/IP Stack Handling if required Host Controller Performance is determined by Device Application, not by EtherCAT In many cases an 8bit µc is sufficient 9

10 EtherCAT Host Controller Interface? The host controller may determine the interface to internal DPRAM of the Controller Example: Beckhoff ASICs: 8/16 Bit µc Interface Demultiplexed Intel Signal Types Polarity configurable (BUSY, INT) Typical µc: ARM, Infineon 80C16x, Hitachi SH1, ST10, TI TMS320 Series, Serial Interface (SPI) Up to 10 MBaud µc is SPI Master Typical µc: Microchip PIC, DSPic, Intel 80C51, Atmel AVR µc ESC RJ45 Magnetic User Application Software Data Service Data Application Mapping PHY es Data Interface Mailbox Data Data ESC & EtherCAT Dual Port Memory Configuration FMMU, Sync Manager PHY Registers Magnetic RJ45 10

11 Criteria Controller Number (and type) of ports Typical: 2-port devices, for line and ring topologies 3+4-port devices cater for topology options 2 Ports 3 Ports 2 Ports 2 Ports 2 Ports 4 Ports 3 Ports 2 Ports 2 Ports 2 Ports 11

12 Criteria Controller Size of DPRAM and no. of Sync Manager entities (SM) Controller Parameter Data (acyclic) Data (cyclic) Data Link Layer Configuration Registers Mailbox Out Mailbox In Output Data Input Data Buffer 1 Buffer 2 Buffer 3 Buffer 1 Buffer 2 Buffer 3 DPRAM SM 0 SM 1 SM 2 SM 3 0x0 4KByte 0x0FFF 0x KByte 0xFFFF 12

13 Criteria Controller Size of DPRAM and no. of Sync Manager entities (SM) Controller Parameter Data (acyclic) Data (cyclic) Data Link Layer Configuration Registers Mailbox Out Mailbox In Output Data Input Data Buffer Output 1Data Buffer Output 2Data Buffer Output 3Data Buffer Input Data 1 Buffer Input Data 2 Buffer Input Data 3 DPRAM SM 0 SM 1 SM 2 SM 3 0x0 4KByte 0x0FFF 0x KByte 0xFFFF 13

14 Criteria Controller No. of Fieldbus Memory Management Units (FMMU) FMMUs copy process data from EtherCAT datagrams to DPRAM and ensure data consistency Mechanism for further optimization of resources (bandwidth, CPU power) EtherCAT Master ECAT Slave 1 Dig. I/O ESC ECAT Slave 2 µc ESC 3 ESC (DPRAM) Dig. I/O FMMU1 (Outputs) Address: Adr Logical +Offset D1 Length: OUT3 Length FMMU2 (Inputs) Address: Adr Logical +Offset D1 Length: IN3 Length ECAT Slave 4 µc ESC Ethernet HDR ECAT HDR Command Adr Logical Length OUT1IN1 IN3OUT3 FCS Offset D1 Shared Command Data in Shared Datagram EtherCAT Data 14

15 Criteria Controller No. of Fieldbus Memory Management Units (FMMU) FMMUs copy process data from EtherCAT datagrams to DPRAM and ensure data consistency Mechanism for further optimization of resources (bandwidth, CPU power) Typical requirement: minimum of 3. FMMU Number Usage 1 Output Data 2 Input Data 3 Status check of Mailbox Response 15

16 Criteria Controller Price? Local Support? Housing? Size? Integrated PHYs? Hilscher netx, Renesas R-IN Integrated CPU? TI Sitara, Hilscher netx, Renesas R-IN FPGA solutions (optional: softcore) Multi Protocol Support Hilscher netx FPGA solutions TI Sitara Renesas R-IN Dedicated for EtherCAT Beckhoff ET1100, ET

17 Controller Timeline Hilscher netx 100/500 ESC10/20: Altera Cyclone -I Beckhoff ET1200 IP-Core for Altera Cyclone -II Beckhoff ET1100 IP-Core Xilinx Spartan -3 Hilscher netx 50 IP-Core for Altera Cyclone -III IP-Core for Altera Stratix -IV IP-Core for Xilinx Spartan -6 IP-Core for Altera Cyclone -IV TI's Sitara µp family Hilscher netx 51/52/6 IP-Core for FPGA of Intel Atom E6x5C IP-Core for Altera Cyclone -V IP-Core for Xilinx Kintex -7 IP-Core for Altera Stratix -V Renesas R-IN32M3-EC Anybus NP40 IP-Core for Xilinx Artix -7 + Zync Innovasic Fido5000 Oct March

18 Physical Layer, Network Interface? EtherCAT Physical Layer is 100BASE-TX or FX* EtherCAT PHYs have to support Full Duplex Communication Auto-Negotiation, MDI/MDI-X auto-crossover MII with MII management interface PHY link loss reaction time (link loss to link signal/led output change) shorter than 15µs (for short redundancy switchover) For further details see the ESC Datasheets or the corresponding PHY Guide * + LVDS for modular devices, supported by Beckhoff ASICs only 18

19 Device Profile? Which device profile shall be supported? Drives: The CiA402 (CANopen) & Sercos Profiles are mapped to EtherCAT IEC Specification IEC Interface Definition IEC Profile Specifications IEC Mapping of Profiles to Network Technologies Annex A Mapping to CiA402 IEC Profile CiA402 IEC IEC Generic Interface and Use of Profiles for Power Drive Systems Annex B Mapping to CIP IEC Profile CIP Motion IEC CANopen** EPL EtherCAT Annex C Mapping to PROFIdrive IEC Profile PROFIdrive IEC Annex D Mapping to SERCOS* IEC Profile SERCOS IEC SERCOS I/II SERCOS III EtherCAT If the device can be described as hardware modules or as logical modules: Modular Device Description recommended Modular Device Profile (ETG.5001) 19

20 Parameter + Data? Device Profile determines Parameters and Data setup But: Decision if the Data Layout shall be: Fixed: cannot be changed by user. Example: simple I/O device. Selectable: user can select between several predefined process data layouts. Example: drive where process data layout depends on the selected drive operation mode Determined by module combination (Dynamic): determined at device bootup by actual hardware modules; Example: bus coupler with modular I/O. 20

21 Synchronization and Time Stamping? What level of Synchronization is required? 1. Freerun: local timer controls application, no synchronization with network 2. Synchronized with network cycle: local application triggered by reception of process data ( SM-event ). Jitter mainly depends on master accuracy. 3. Synchronized by Distributed Clocks: local application triggered by high precision and fully synchronized hardware interrupt generated by local clock; accuracy in the order of nanoseconds 21

22 Hardware Design HW / SW Aspects Lab Wiring with µc ETG Support Hardware Development Electronics Physics Software Development ESI Local Application Integration Debugging with Wireshark + CTT HW/SW Integration Integrated Interoperability Tests, Plug Fests, Network System Tests, Pilot Applications In-house Test with CTT 1) according to ETG Test Record Official EtherCAT Test ETG.2200 Guide Product Release 1) mandatory step for selling EtherCAT Devices 22

23 Hardware Design Device Application / Application Layer EtherCAT LEDs ESC / Data Link Layer RJ45 Magnetic PHY Bus Interface / Physical Layer µc or dig. I/O Interface Controller (ESC) Application / Host Controller According to Application Requirements Data Interface (PDI) PHY I 2 C Magnetic Individual HW/SW EEPROM (ESC config. Data) Controller According to ESC Criteria RJ45 Network Interface / Physical Layer Standard Ethernet Interface, Requirements according to PHY Guide / ESC Datasheet 23

24 Software Development HW / SW Aspects Lab Wiring with µc ETG Support Hardware Development Electronics Physics Software Development ESI Local Application Integration Debugging with Wireshark + CTT HW/SW Integration Integrated Interoperability Tests, Plug Fests, Network System Tests, Pilot Applications In-house Test with CTT 1) according to ETG Test Record Official EtherCAT Test ETG.2200 Guide Product Release 1) mandatory step for selling EtherCAT Devices 24

25 Device Description: ESI File Each device is described by an Information (ESI) File in XML Format The ESI Format is defined in the ETG.2000 spec Of course there are also schemas, example files etc. on the EtherCAT website The ESI also supports the description of modular devices Information Files (ESI) *.xml *.xml 25

26 Software Development Typical Software-Structure: Applications-Program/Firmware Communication-Stack with following elements: EtherCAT State Machine Verification of configuration settings Handling of synchronization + configuration errors Mailbox-Protocol Handling Most common protocol: CoE Error Handling (e.g. Parameter cannot be read or written) Access to ESC memory (DPRAM) Synchronization The listed functionality is supported by most available stacks, such as Beckhoff Slave Stack Code (free of charge for ETG members) Hilscher Stack 26

27 Software Development Example: Structure of Beckhoffs Slave Stack Code Device Application / Application Layer µc Slave Sample Code ESC / DataLink Layer RJ45 CoE SoE EoE Mailbox FoE AoE Network Interface / Physical Layer User Application Software Local Communication Application Data Handler ESC Memory Interface ESC PDI EtherCAT State Machine RJ45 27

28 : Plug Fests Plug Fests are Developer Interoperability Meetings Most helpful and well attended: 2/y in Europe, 1-2/y in Asia, 1/y in North America 28

29 Testing HW / SW Aspects Lab Wiring with µc ETG Support Hardware Development Electronics Physics Software Development ESI Local Application Integration Debugging with Wireshark + CTT HW/SW Integration Integrated Interoperability Tests, Plug Fests, Network System Tests, Pilot Applications In-house Test with CTT 1) according to ETG Test Record Official EtherCAT Test ETG.2200 Guide Product Release 1) mandatory step for selling EtherCAT Devices 29

30 Testing The EtherCAT Test Tool (CTT) is helpful throughout the implementation and afterwards Having the CTT and testing with it is a requirement Recommended Procedure (see Guide): If not yet ETG member: Join ETG (free of charge) Obtain EtherCAT Vendor ID (free of charge) Subscribe to Test Tool Test Record (ETG ) is Test Guideline Test with CTT Test of the LED behavior (ETG.1300) Marking and Trademark Hints (ETG.9001) Further tests Test at official EtherCAT Test Center (and Certification) is optional, but highly recommended 30

31 and how to avoid them! The 5 Killers for passing the conformance test: 1. Logo: Neither on the device nor in the documentation the EtherCAT logo is shown 2. Trademark: Trademark hint is missing in the documentation 3. Indicator and Port Marking: Marking is missing or misleading 4. Watchdog Behavior: If sending of process data is stopped the device does not show the required behavior 5. DC-Signal Monitoring: If the interrupt for the synchronization is disabled the device does not show the required behavior IN/OUT? 31

32 1. Implementing EtherCAT is relatively simple: the demanding parts are embedded in the EtherCAT Slave Controller chip 2. ETG (and its members) provide all the information and support for the implementation of EtherCAT 3. Tools, Stacks, Support Documents, Guidelines, Developers Forum etc. are all in place - and well proven. 4. EtherCAT is a stable technology, that has been successfully implemented by a large number of vendors 5. See also: Guideline 32