On the Phase Coupling Problem between Data Memory Layout Generation and Address Pointer Assignment

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1 On the Phase Coupling Problem between Data Memory Layout Generation and Address Pointer Assignment Bernhard Wess and Thomas Zeitlhofer Institute of Communications and Radio-Frequency Engineering INSTITUT FÜR NACHRICHTENTECHNIK UND HOCHFREQUENZTECHNIK

2 Outline Introduction Simple offset assignment (SOA) General offset assignment (GOA) Quadratic Assignment Problem (QAP) Optimum address pointer assignment (APA) Iterative GOA Example Experimental results Conclusions B. Wess, T. Zeitlhofer, August 5, 4 p.

3 Simple Offset Assignment (SOA) Memory layout generation for a given data access stream. for a given access stream... Memory Layout a Data Access Stream d c c d b e a f b c d e f single address pointer, [, +] B. Wess, T. Zeitlhofer, August 5, 4 p. 3

4 General Offset Assignment (GOA) Address pointer assignment and memory layout generation for a given data access stream. Memory Layout a Data Access Stream d c c d b e a f b c d e f two address pointers, [, +] B. Wess, T. Zeitlhofer, August 5, 4 p. 3

5 Optimization Problem Memory layout generation and address pointer assignment for a given data access stream Parameters Number of address pointers, auto-modify range, linear/modulo addressing Objective Minimization of data address computation overhead Complexity Number of solution space points: K M N! for data access stream length M, N program variables and K address pointers. B. Wess, T. Zeitlhofer, August 5, 4 p. 4

6 Some Definitions Let V be a set of program variables. Each variable v i V is identified by index i {,,..., N} with N = V. A data access stream S = v s(), v s(),..., v s(m) is defined by a function s : {,,..., M} {,,..., N} where M = S denotes the stream length and N M. The image s(l) of any l {,,..., M} defines the program variable v s(l) on position l in the data access stream S. B. Wess, T. Zeitlhofer, August 5, 4 p. 5

7 Memory Layout A memory layout is a permutation π : {,,..., N} {,,..., N} that assigns addresses to all program variables which appear in the access stream S. Let us assume that an address register points to v i and it should be used for accessing v j. To this end, the address pointer has to be modified by address offset π(j) π(i). AGUs of DSPs support zero-cost address pointer updates for a limited set of offset values. Obviously, costs can be minimized by memory layout optimization. B. Wess, T. Zeitlhofer, August 5, 4 p. 6

8 Quadratic Assignment Problem Let c ij with i, j {,,..., N} be a cost value for redirecting an address pointer from address i to the new address j. Additionally, let t S ij specify how often address j is accessed right after address i in S. For a single address pointer, the address computation costs can be expressed by C = N N c ij t S π(i)π(j). i= j= Modifying π such that C becomes a minimum is a quadratic assignment problem (QAP). B. Wess, T. Zeitlhofer, August 5, 4 p. 7

9 QAP Example Access Stream: S = e, a, f, d, c, h, g, b, h, b, a, b, h, e, f Auto-Modify Range: [, ] d c f a e b h g v πa (i) d c f ae b h g h b e a f d c g v πb (i) h b e a f d c g linear addressing modulo addressing B. Wess, T. Zeitlhofer, August 5, 4 p.

10 Access Graph We define an undirected graph G = (V, E) to represent the access transitions between program variables in S and call G the access graph of S. Each node in the graph corresponds to a unique program variable. There is an undirected edge e = (v i, v j ) E in G with weight w(e) if the program variables v i and v j are adjacent w(e) times in S. Note that G is always a connected graph. B. Wess, T. Zeitlhofer, August 5, 4 p.

11 SOA in the Access Graph AGUs with auto-modify range [, ] and single address pointer. SOA is equivalent to searching for maximum-weighted Hamiltonian paths in the access graph. Example: S = a, b, c, d, e, f, a, d, a, d, a, c, d, f, a, d Access Graph a b e c 5 f d Memory Layout b c d a f e path weight: addressing costs: C = 4 B. Wess, T. Zeitlhofer, August 5, 4 p. 3

12 Auto-Modify Range [ r, r] Example: S = a, b, c, d, e, f, a, d, a, d, a, c, d, f, a, d, [, ] Access Graph a b e c 5 f d Memory Layout path weight: 9 addressing costs: C = Optimum layout does not correspond to a maximum-weighted Hamiltonian path b c a d f e B. Wess, T. Zeitlhofer, August 5, 4 p. 5

13 GOA Some Definitions Both memory layout and address pointer assignment are optimized. Assigning address pointers can be regarded as K-coloring the access stream S. A coloring of S is a partition that decomposes {,,..., M} into K disjoint subsets. Each subset defines an access stream with S k = v sk (), v sk (),..., v sk (M k ) s k : {,,..., M k } {,,..., M} and K k= M k = M. For each S k, all elements appear in the same relative order as in S. B. Wess, T. Zeitlhofer, August 5, 4 p. 6

14 Multiple Index Registers Separate transition matrix for each color k GOA minimizes C K = K k= N i= N j= c ij t S k π(i)π(j) Example: K =, modulo addressing with auto-modify range [, ] S = b, f, e, j, e, a, h, d, g, a, f, h, e, b, a, j, c, i, c, j e f b a j g c i h d v π(i) e f b a j g ci h d e f b a j g c i h d v π(i) e f b a j g ci h d red transition matrix blue transition matrix B. Wess, T. Zeitlhofer, August 5, 4 p. 7

15 Optimization Space memory layout data access stream pointer assignment B. Wess, T. Zeitlhofer, August 5, 4 p. 8

16 Optimum Address Pointer Assignment Assumptions: Fixed memory layout, homogeneous address pointer set Address pointer assignment by coloring the access stream of length M K M colorings exist ( K... number of pointers) Search space pruning by identifying equivalent substream colorings complexity is reduced to O(M N K ) for N M program variables Equivalent substream colorings are identified by investigation of pointer positions B. Wess, T. Zeitlhofer, August 5, 4 p. 9

17 APA Example Data access stream S = d c c d b e a f Address pointers p and p Fixed memory layout a b 3 c 4 d 5 e 6 f Initialization: p points to variable d B. Wess, T. Zeitlhofer, August 5, 4 p.

18 Example Coloring Tree for K = Sequence: dccdbeaf d Layout: abcbef c c d b e a f Initialization Costs I: add for each new pointer Total Costs: C = I + (K + )C K = B. Wess, T. Zeitlhofer, August 5, 4 p.

19 Example Computing Cost Values Access Stream: dccdbeaf d Layout: abcbdef c c d b e a f Initialization Costs I: add for each new pointer Total Costs: C = I + (K + )C K = B. Wess, T. Zeitlhofer, August 5, 4 p.

20 APA Complexity Analysis 8 7 search space complexity K K M M N K ( ) N + K M K K address pointers, N program variables, M accesses optimum solutions feasible M N =.5 N = 5 B. Wess, T. Zeitlhofer, August 5, 4 p. 3

21 APA Experimental Results N M opt. W = W = C C time [s] C time [s] < 87 < 6 3 < < < < Most complex OffsetStone examples, K = 3, heuristically pruned search tree width W B. Wess, T. Zeitlhofer, August 5, 4 p. 4

22 Bandwidth OA is related to the bandwidth minimization problem (BMP) of graphs. The bandwidth bw of π is defined as the maximum distance between the images under π of any two nodes that are connected by an edge, bw(π) = max { π(i) π(j) (v i, v j ) E}. The bandwidth BW of G is defined as the least possible bandwidth for any layout of G, BW (G) = min {bw(π) π is a layout of G}. B. Wess, T. Zeitlhofer, August 5, 4 p. 5

23 Maximum Bandwidth-r Graphs Assuming a symmetric offset range we introduce the maximum bandwidth-r graph Ĝ(V, Ê, r) where Ê = max{ (v i, v j ) V V BW (Ĝ) = r}. This graph defines all zero-cost transitions for a given range r and layout π. The structure of Ĝ for r = : B. Wess, T. Zeitlhofer, August 5, 4 p. 6

24 GOA Minimizing C K for symmetric update ranges may also be interpreted as mapping the access graph G onto the maximum bandwidth-r graph Ĝ subject to the cost function C K = e Ẽ w(e) with Ẽ = {(v i, v j ) E (v i, v j ) / Ê}. An optimized mapping may be generated by. permutation of vertices, which corresponds to memory layout (π) modifications and/or. adding/removing edges to/from the access graph G, which corresponds to pointer assignment (s k ) modifications. B. Wess, T. Zeitlhofer, August 5, 4 p. 7

25 Iterative GOA data access stream G highly optimized GOA solution OA APA. Data access stream initial access graph. Memory layout generation 3. Optimum APA modified access graph 4. Repeat steps and 3 until no further cost reduction B. Wess, T. Zeitlhofer, August 5, 4 p. 8

26 Iterative GOA Example Cont d Data Access Stream: S =,,, 3,, 4,, 5, 3, 6, 7,, 8,, 9, 3, Initial access graph G and memory layout π B. Wess, T. Zeitlhofer, August 5, 4 p. 9

27 Iterative GOA Example Cont d Data Access Stream: S =,,, 3,, 4,, 5, 3, 6, 7,, 8,, 9, 3, APA for π new access graph G B. Wess, T. Zeitlhofer, August 5, 4 p. 3

28 Iterative GOA Example Cont d Data Access Stream: S =,,, 3,, 4,, 5, 3, 6, 7,, 8,, 9, 3, G new memory layout π B. Wess, T. Zeitlhofer, August 5, 4 p. 3

29 Iterative GOA Example Cont d Data Access Stream: S =,,, 3,, 4,, 5, 3, 6, 7,, 8,, 9, 3, APA for π new access graph G B. Wess, T. Zeitlhofer, August 5, 4 p. 3

30 Iterative GOA Example Cont d Data Access Stream: S =,,, 3,, 4,, 5, 3, 6, 7,, 8,, 9, 3, G new memory layout π B. Wess, T. Zeitlhofer, August 5, 4 p. 33

31 Iterative GOA Experimental Results M N IG IG SA Number of required address pointer reloads for K =, M access sequence length, N number of program variables, IG iterative GOA with optimized initial memory layout, IG iterative GOA with first appearance initial memory layout, SA simulated annealing B. Wess, T. Zeitlhofer, August 5, 4 p. 34

32 Iterative GOA Experimental Results Cont d 79 access streams from the OffsetStone benchmark suite with length up to, r = and two address pointers. relative frequency [%] cost reduction Cost value reduction for iterative GOA. B. Wess, T. Zeitlhofer, August 5, 4 p. 35

33 Conclusions Address pointer assignment (APA) and memory layout generation are highly interdependent phases in general offset assignment (GOA). Optimized GOA solutions can be generated by iteratively applying efficient algorithms for APA and memory layout generation. Compared to simulated annealing approaches, equivalent solutions can be generated typically in less time. B. Wess, T. Zeitlhofer, August 5, 4 p. 36

How to efficiently use the address register? Address register = contains the address of the operand to fetch from memory.

Lesson 13 Storage Assignment Optimizations Sequence of accesses is very important Simple Offset Assignment This lesson will focus on: Code size and data segment size How to efficiently use the address