Department of Electrical and Computer Engineering The University of Texas at Austin

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1 Department of Electrical and Computer Engineering The University of Texas at Austin EE N Spring 7 Y. N. Patt, Instructor Chirag Sakhuja, Sarbartha Banerjee, Jonathan Dahm, Arjun Teh, TAs Exam March, 7 Name: Problem (5 points): Problem ( points): Problem (5 points): Problem (5 points): Problem 5 (5 points): Total ( points): Note: Please be sure that your answers to all questions (and all supporting work that is required) are contained in the space provided. Note: Please be sure your name is recorded on each sheet of the exam. Please sign the following. I have not given nor received any unauthorized help on this exam. Signature: GOOD LUCK!

2 Problem (5 points): Answer any five of the six. Draw a line through the one you do not want graded. Part a (5 points): A load-store ISA does not allow what? Part b (5 points): Unaligned accesses. Part of the ISA or part of the microarchitecture? Explain. Part c (5 points): Interleaving. Part of the ISA or part of the microarchitecture? Explain. Part d (5 points): J.E.Smith s branch predictor introduced the use of saturating -bit counters. What does the word saturating mean in this context, and why is it necessary? Part e (5 points): McFarling modified my GAs predictor, creating g-share. What was his purpose for doing so? Part f (5 points): Do processes having higher priority get increased privilege? If yes, explain why. If no, explain why not.

3 Problem ( points): An Aggie hates the LC-b, so he cuts the wires labeled A and B on the data path, and grounds the wire labeled C in the microsequencer so the LC-b can not function properly. (The data path, showing wires A and B is shown on the next page.) Part a ( points): If the wires A are cut, which instruction(s) are impossible to function? Explain. Instruction(s) Explanation Part b ( points): If the wires B are cut, which instruction(s) are impossible to function? Explain. Instruction(s) Explanation Part c ( points): If wire C is grounded, which instruction(s) are impossible to function? Explain. Instruction(s) Explanation COND COND BEN I[] J[5] J[] J[] J[] J[] J[] C,,I[5:] ID Address of Next State

4 MEMOY OUTPUT INPUT KBD ADD. CTL. MD INMUX MA L MA[] MA[] DATA.SIZE DATA.SIZE LD.MD D.MA KBS MEM.EN.W MIO.EN GatePC GateMAMUX LD.CC SMUX [8:] [:] [5:] PC LD.PC [7:] LSHF [:] GateALU SHF GateSHF I[5:] GateMD N Z P S OUT S OUT EG FILE MAMUX ADDMUX ZEXT & LSHF ALU ALUK A B ADDMUX PCMUX S D S LD.EG I LD.I DD DS MIO.EN SIZE DATA. WEWE [] WE CONTOL A B

5 Problem (5 points): In this problem we add an SAg -level branch predictor to the LC-b. ecall that the S means the branches are partitioned into sets, where all branches in a set share the same BH. In our case, we have 8 sets, and therefore 8 BHs. Bits,, and 7 of a branch s address determine which set a branch belongs to. For example, a branch at address x9e8 uses BH because bit is, and bits and 7 are. The current state of the BHs are shown below. The direction (taken =, not taken = ) of the most recent branch is the right-most bit of its respective BH. 5 7 BHs (before) BHs (after) PHT (before) PHT (after) Part a (5 points): The PC contains xe, and the instruction fetched is a branch. Does the branch predictor predict taken or not taken? On what information is your answer based? Please be specific. Part b (5 points): The branch at xe is taken. Compute the new BHs and PHT in the figure above after this branch completes execution. It is only necessary to show the after entries that have changed. POBLEM CONTINUTED ON NEXT PAGE 5

6 Part c (5 points): Execution of the program results in four more branches (for a total of five) being executed. They are at locations xcc8, xd8, x8, and x97. Each of the five branches retires before the next branch is fetched. The table below shows the prediction and direction for each of these five branches. Your job: complete the table below. Do not make any changes to the figures on the previous page. Branch at address Prediction Actual xe (Answer in part a) Taken xcc8 xd8 x8 x97 Taken Taken Not Taken Not Taken

7 Problem (5 points): An out-of-order processor executes its instructions according to the Tomasulo algorithm. The ISA specifies 8 registers, to 7. The microarchitecture contains one pipelined adder and one pipelined multiplier. Pipelining allows an add (or multiply) instruction to initiate execution each clock cycle. Fetch and Decode take one cycle each. ADD execution takes cycles MUL execution takes 5 cycles. For ADD and MUL, if two instructions are ready to dispatch to the same functional unit in the same cycle, the older instruction is dispatched and the younger instruction waits. For ADD and MUL, one cycle is needed to write the result to a destination register. Only one result can be written in a single clock cycle. If two instructions want to write results in the same clock cycle, the older instruction writes, and the younger is stored in a buffer and is available for writing in the following cycle. Data forwarding is not implemented. The adder and multiplier each have -entry reservation stations. Note: if an instruction is of the form ADD x, y, z or MUL x, y, z, and y contains valid data 7 and z contains valid data 7, the reservation station entry has the form: V TAG VALUE V TAG VALUE 7 7 The reservation stations are initially empty and are filled from top to bottom. Each instruction remains in the reservation station until the end of the cycle in which it writes its result to a register. The table below contains a program of seven instructions that are executed. I ADD I I I I5 I I7 ADD 5 POBLEM CONTINUTED ON NEXT PAGE 7

8 Three snapshots of the machine are shown: (a) before execution, (b) after clock cycle 5, and (c) after clock cycle 9. Note that some information in the program (shown on the previous page), in the register file, and in the reservation stations are missing. V TAG VALUE V TAG VALUE V TAG VALUE γ δ β 7 β (a) Beginning (b) After cycle 5 (c) After cycle 9 α β γ V TAG VALUE V TAG VALUE V TAG VALUE V TAG VALUE α δ σ φ (b) After cycle 5 α β γ V TAG VALUE V TAG VALUE V TAG VALUE V TAG VALUE β δ σ φ (c) After cycle 9 Part a ( points): Your job: Fill in the missing information in the program (shown on the previous page), and in the bolded boxes in the register file and reservation stations at each of the snapshots. Part b (5 points): The figure below shows, for each clock cycle, which phase of the instruction cycle each of the seven instructions are in. Complete the figure. We have provided clock cycles. Only use what you need I F D I F D I F D I F D I5 F D I F D I7 F D 8

9 Problem 5 (5 points): Suppose we have a -way interleaved DAM memory, with bits[:] designating the bank. All address bits are as shown. Note, the question marks below; in part b, you are going to have to determine how many row bits and how many column bits. 5?? ank ow Column Bank Byte on Bus ecall that a single memory bank has the following form: Memory Bank Y Chip Chip ow Buffer ow Buffer X 8 8 A row access takes cycles, and a subsequent column access takes cycles. We store sequentially in this memory, starting at location x8, an array of English words, each containing 7 letters. Each word is stored in 8 consecutive locations, one location each for the corresponding ASCII code, and one location for a null terminator (x). For example the word Compute would be stored as: POBLEM CONTINUTED ON NEXT PAGE x xf xd x7 x75 x7 x5 x 9

10 Part a ( points): Suppose we were to load the contents of location x8. After the load completes, A, B, C, and D are bytes of data in the row buffer. What are the addresses of the locations containing those bytes of data? Memory Bank Address containing A: Y Chip Chip Address containing B: X ow Buffer... ow A B... Buffer C D Address containing C: Address containing D: x8 8 8 Part b (9 points): We wish to determine how many of the English words end in the letter e with a minimum number of memory accesses. Part b (7 points): If we end up having to load 8 rows into the row buffer, how many bits must have been used to specify the row, and how many bits must have been used to specify the column? ow bits: Column bits: Part b ( points): How many clock cycles are necessary to access this information from memory, assuming memory accesses are sent to DAM in order of increasing addresses? (Note: Your answer will depend on how much you can use interleaving.) Clock cycles: Part b ( points): Suppose we interchange the column bits and the bank bits. Now how many clock cycles are necessary to access this information from memory, assuming memory accesses are sent to DAM in order of increasing addresses? Clock cycles:

11 ADD ADD D S S D S imm5 AND AND D S S D S imm5 B n z p PCoffset9 JMP Base JS PCoffset JS Base LDB D Base boffset LDW D Base offset LEA NOT D D S PCoffset9 ET TI LSHF SHFL SHFA D S amount D S amount D S amount STB S Base boffset STW S Base offset TAP trapvect8 XO XO D S D S S imm5 not used not used Figure : LC-b Instruction Encodings

12 Table : Data path control signals Signal Name Signal Values LD.MA/: NO(), LOAD() LD.MD/: NO(), LOAD() LD.I/: NO(), LOAD() LD.BEN/: NO(), LOAD() LD.EG/: NO(), LOAD() LD.CC/: NO(), LOAD() LD.PC/: NO(), LOAD() GatePC/: GateMD/: GateALU/: GateMAMUX/: GateSHF/: NO(), YES() NO(), YES() NO(), YES() NO(), YES() NO(), YES() PCMUX/: PC() ;select pc BUS() ;select value from bus ADDE() ;select output of address adder DMUX/:.9() ;destination I[:9] 7() ;destination 7 SMUX/:.9() ;source I[:9] 8.() ;source I[8:] ADDMUX/: PC(), Base() ADDMUX/: ZEO() ;select the value zero offset() ;select [I[5:]] PCoffset9() ;select [I[8:]] PCoffset() ;select [I[:]] MAMUX/: 7.() ;select LSHF(ZEXT[I[7:]],) ADDE() ;select output of address adder ALUK/: MIO.EN/:.W/: DATA.SIZE/: LSHF/: ADD(), AND(), XO(), PASSA() NO(), YES() D(), W() BYTE(), WOD() NO(), YES() Table : Microsequencer control signals Signal Name Signal Values J/: COND/: COND ;Unconditional COND ;Memory eady COND ;Branch COND ;Addressing Mode ID/: NO, YES

13 MA < PC PC < PC 8, 9 MD < M I < MD 5 To 8 TI ADD BEN< I[] & N I[] & Z I[9] & P [I[5:]] B To To To 8 D< SOP* set CC D< S&OP* set CC 5 AND XO TAP SHF LEA LDB LDW STW STB JS JMP [BEN] PC< PCLSHF(off9,) To 8 9 D< S XO OP* set CC PC< Base To 8 To 8 MA< LSHF(ZEXT[I[7:]],) 5 [I[]] To 8 8 MD< M[MA] 7< PC PC< MD 7< PC PC< Base 7< PC To 8 PC< PCLSHF(off,) To 8 D< SHF(S,A,D,amt) set CC To 8 To 8 D< PCLSHF(off9, ) set CC MA< Boff MA< BLSHF(off,) 7 MA< BLSHF(off,) MA< Boff To NOTES Boff : Base [offset] PCoff9 : PC [offset9] *OP may be S or [imm5] ** [5:8] or [7:] depending on MA[] MD< M[MA[5:] ] D< [BYTE.DATA] set CC MD< M[MA] 7 D< MD set CC MD< S M[MA]< MD MD< S[7:] 7 M[MA]< MD** To 8 To 8 To 8 To 9 Figure : A state machine for the LC-b

14 GateMAMUX GatePC LD.PC PC ZEXT & LSHF MAMUX LSHF PCMUX ADDMUX LD.EG S S OUT EG FILE S OUT D S [7:] ADDMUX [:] [8:] SMUX [5:] [:] CONTOL LD.I I LD.CC N Z P B A ALUK ALU SHF I[5:] GateALU GateSHF GateMD MA LD. MA DATA.SIZE MA[] WE WE WE MEMOY [].W DATA. SIZE ADD. CTL. MIO.EN INPUT KBD KBS DD OUTPUT DS MD LD. MD MEM.EN MIO.EN DATA.SIZE MA[] INMUX Figure : The LC-b data path

15 COND COND BEN I[] Branch eady Addr. Mode J[5] J[] J[] J[] J[] J[],,I[5:] ID Address of Next State Figure : The microsequencer of the LC-b base machine 5