CIS 371 Spring 2016 Computer Organization and Design 17 March 2016 Midterm Exam Answer Key

Transcription

1 CIS 371 Spring 2016 Midterm 1 CIS 371 Spring 2016 Computer Organization and Design 17 March 2016 Midterm Exam Answer Key 0.) The Easy One (1 point total) Check cover sheet for name, recitation #, PennKey, and signature. 1.) Wallace and Gromit (4 points total) Gromit wants to count the holes in the block of cheese he s prepared for Wallace s breakfast. Since the holes are laid out in a nice grid pattern and dogs are bad at arithmetic, he s designed a carry-save adder tree multiplier (a Wallace Tree ) to multiply two 6-bit values without overflowing. The last stage is a ripple-carry adder. 1.1) (1 point) How many carry-save adders are there in the tree? 4 ( ) 1.2) (1 point) How many bits wide are the submodules, assuming they are all the same width? 12 bits 1.3) (1 point) What is the total gate delay of the circuit? 30 (3 * 2 for the CSA levels + 24 for the RC) 1.4) (1 point) Gromit is considering replacing the ripple-carry adder at the end with a carry lookahead ahead (CLA). What is the delay of an N-bit CLA, as a function of N? (a) N (b) 2N (c) N 2 (d) N(N+1) 2 (e) None of the above (it s actually log N)

2 CIS 371 Spring 2016 Midterm 2 2.) Performing to Expectation (7 points total) Your boss Shrek asks you to work on a tiny processor (version A) that is not pipelined and takes multiple cycles for most instructions. The program has the following instruction type breakdown and latencies: Type Breakdown Latency load 10% 7 cycles store 15% 10 branch 15% 4 add 55% 4 divide 5% 5 One day Shrek comes to you with two new ideas for possible improvements to the processor that don t affect the cycle time. He wants you to choose between: (a) No change from the table above; (b) A version that triples the load latency but cuts the store latency in half; (c) A version that leaves the load latencies unchanged and adds 50% to the store latency, but cuts the divide latency to just 2 cycles. 2.1) (2 points) Which version is fastest: (a), (b), or (c)? (a) 2.2) (3 points) What is the speedup of the fastest version over the other two (in the form, (X) is 1.s times faster than (Y) and 1.t times faster than (Z). ). Round your answer to two decimal places (and take advantage of that rounding to compute the speedups quickly without a calculator!). (a) is 1.12x faster than (b) and 1.11x faster than (c). 2.3) (2 points) Shrek, being an ogre, grumbles that your numbers are all wrong because version (a) s branch predictor is only 70% accurate, whereas versions (b) and (c) have branch predictors that are 90% accurate. Moreover, there is a 4 cycle mispredict penalty in all versions due to the cache prefetching architecture. With this additional information, which processor version would be best, and what is its CPI? Your answer: (a), which is 5.43 CPI

3 CIS 371 Spring 2016 Midterm 3 3.) The Complex Number Complex (10 points total) Each short answer must be 30 words or less, but you do not have to write complete sentences. Shrek wants you to add CADD, CSUB, and CMUL instructions to your LC4 datapath to support complex numbers, because, being an imaginary beast, he does all his arithmetic with imaginary numbers. These instructions should work just like their real number counterparts, but with complex numbers. 3.1) (1 point) Your first idea is to store each complex number in a pair of registers one for the real part, and the other for the imaginary part and let the programmer/compiler pick any two registers for this purpose. Why won t this work? There are not enough bits in an instruction to encode four source and two destination registers. 3.2) (5 points) Your next idea is to store the real and imaginary parts in consecutive registers. So, if the real part is stored in register k, then the imaginary part must be stored in register k + 1. Aside from changes to the decoder and control signals to support the new instructions, what architectural changes are necessary to support these instructions in your pipelined datapath from lab 3? Four read ports and two write ports on regfile; extra adders and multipliers in ALU, twice as many bypasses. 3.3) (4 points) You conclude that storing complex numbers in a pair of registers is impractical. Instead you decide to limit complex numbers to 8-bits each for the real and imaginary parts, which you stuff into a single 16-bit register. (You justify this by pointing out to Shrek that the wildly successful Motorola was a 32-bit architecture that only supported 16-bit multiplies to avoid overflow problems and save on hardware. Your proposal is very similar in spirit.) What change can you make to the existing adder to support CADD with only a trivial number of extra gates? Force the carry-in to bit 8 to 0 for the CADD instruction. Note that a similar trick works for CSUB and CMUL, although you still need additional multiply hardware to perform 4 8-bit multiplies in parallel.

4 CIS 371 Spring 2016 Midterm 4 4.) Pipelines (12 points total) Each short answer must be 30 words or less, but you do not have to write complete sentences. 4.1) (3 points) A common mistake on Lab 3 (Pipelined Datapath) is putting a decoder module in every stage of the pipeline rather than decoding once and passing the control signals from stage to stage. Why is this bad design? It defeats the point of the decoder stage which handles the time cost of decoding. or It makes every stage slower than necessary. 4.2) (2 points) Why does pipelining improve instruction throughput but not instruction latency? More instructions in pipeline per unit time, but at least as long for each instruction to complete. or Next instruction starts before current one has completed, but at least as long for each instruction to complete. 4.3) (3 points) Shrek wants to execute a program with a store instruction that overwrites the instruction immediately following it. This is an insidious case of dynamic code generation, but Shrek is an ogre after all. To keep the pipeline fast, he wants to add a bypass from X to D for the fetched instruction itself. Assume each stage takes the entire cycle to compute its results. Explain why this will or will not work. Will not work: store address available at end of cycle, but decode needs it at beginning. 4.4) (4 points) List four instances where you need to bypass information from one stage to another in Lab 3 (Pipelined Datapath). For each one, list the stage in which the data is produced (From), the stage in which it is consumed (To), the type of data being forwarded (or a reasonable name for the wire that carries it), and an LC4 (pseudo-)assembly example illustrating when it is necessary. We will grade the example based on whether the reason for bypassing is clear, correct, and concise, not on whether your LC4 assembly has perfect syntax. From To Data/Wire Name Code Example M X rs/rt add r0 rx rx; add rx rx r0; W X rs/rt add r0 rx rx; -----; add rx rx r0; W M data to store in memory ldr r0 rx #x; str r0 rx #x; W D rs/rt add r0 rx rx; -----; -----; add rx rx r0; M X nzp add rx rx rx; BRn; W X nzp ldr rx rx #x; BRz;

5 CIS 371 Spring 2016 Midterm 5 5.) An Olive Branch (7 points total) 5.1) (4 points) List three branch prediction prediction approaches, ordered from least accurate (a) to most accurate (c) for a typical workload. If you need to correct the order after you give the answer, clearly write (a) next to your least accurate method, (b) next to the middle method, and (c) next to the most accurate method. (a) Static predictor (always taken or always not taken) (b) 1-bit predictor (1-bit branch history table) (c) 2-bit saturating counter (d) Correlated predictor (branch history register) (e) Hybrid predictor 5.2) (3 points) State what each of the following acronyms stand for, and, in 15 words or less, describe it. If the acronym has nothing to do with branch prediction, just write unrelated (stating what unrelated acronyms stand for is optional). (a) BBB Better Business Bureau, unrelated (b) BBS Bulletin Board System, unrelated (c) BHT Branch History Table, stores last branch outcome for PC (d) BTB Branch Target Buffer, stores last branch target for PC (e) RAS Return Address Stack, to predict targets of RTI instructions (f) RSA Rivest-Shamir-Adelman, unrelated

6 CIS 371 Spring 2016 Midterm 6 6.) Not an Olive Branch (10 points total) Fill in the following branch prediction table. For the 2-bit saturating counter, assume all branch instructions share a single PC. Assume the previous three outcomes were taken, taken, not taken. The initial states of the predictors have been filled in for you on the first row, but you need to add the predictions. Branch Outcome 2-bit counter (states are T, t, n, N) 3-bit correlated predictor (history of last three branches) State Prediction State Prediction NNN NNT NTN NTT TNN TNT TTN TTT T t T N T N T N T N T N N T T N T N T N T T T T N t T N T N T N N T T N N n N N T N T N N T T N T N N N T N T N N T T N T n N T T N T N N T T T N t T T T N T N N T T T N n N T T N N N N T T T T N N T T N N N N N T N T n N T T N N T N N T T N t T T T N N T N N T N