Department of Electrical and Computer Engineering The University of Texas at Austin

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1 Department of Electrical and Computer Engineering The University of Texas at Austin EE 46N Fall Y. N. Patt, Instructor Siavash Zangeneh, Ali Fakhrzadehgan, Steven Flolid, Matthew Normyle TAs Exam 1 October 5, Name: Problem 1 ( points): Problem (15 points): Problem (15 points): Problem 4 (5 points): Problem 5 (5 points): Total (1 points): Note: Please be sure that your answers to all questions (and all supporting work that is required) are contained in the space provided. Note: Please be sure your name is recorded on each sheet of the exam. Please sign the following. I have not given nor received any unauthorized help on this exam. Signature: GOOD LUCK!

2 Problem 1 ( points): Please answer any four of the following five parts. Please draw a line through the box of the part you choose not to answer. Part a (5 points): A zero-address machine explicitly specifies NONE of the three relevant addresses (two source operands, one destination operand) of an operate instruction. How does the microarchitecture know where to get the sources and where to store the result? Part b (5 points): The Alpha 14 chip had a 96KB L cache. 96 is not a power of. Why did the designers implement such an unusual size cache? Part c (5 points): An important tradeoff exists in the decision as to whether or not to use condition codes. The positive of using condition codes is that it gives you an extra piece of information without requiring an extra instruction to get that piece of information. The negative is: Part d (5 points): We would like to fetch a full packet of useful instructions from the on-chip instruction storage each cycle. Three things can prevent that from happening. They are: Part e (5 points): A recent term in the vocabulary of microarchitects is Dark Silicon. What does it refer to, and how can it be a feature, rather than a bug?

3 Problem (15 points) An array of x1 -bit s-complement integers are stored in contiguous memory locations, starting at address x5. The following program sums the positive integers contained in the array (ignores the negative integers) and stores the sum in..oig x4 LEA 5, DATA LOCATION LDW, 5, # ; r <- M[DATA LOCATION] LEA 5, LENGTH LDW 1, 5, # ; r1 <- M[LENGTH] AND,, # LOOP LDW,, # ; get the next integer Bnz SKIP ADD,, SKIP ADD,, # ; increment the pointer ADD 1, 1, #-1 ; decrement the iteration count Bp LOOP ; go to next iteration HALT DATA LOCATION LENGTH.FILL x5.fill x1.end The program is executed on a computer whose microarchitecture supports: (a) virtual memory, (b) a 1 stage pipeline, (c) a per-branch last time taken branch predictor, and (d) 8-way interleaved physical memory. Memory accesses take 5 cycles. If the s-complement integers in the array are sorted, the program takes approximately 1 nanoseconds to execute. If the integers are unsorted (i.e., stored in random locations within the array), the program takes approximately nanoseconds to execute. Part a ( points): Is this performance difference explained by the ISA or the microarchitecture? Part b (1 points): Considering the 5 possibilities (i.e., the ISA and the four microarchitecture structures a to d above), explain your best guess as to what is causing the enormous difference (1 nanoseconds vs nanoseconds) in execution time.

4 Problem (15 points): We wish to use one of the unused opcodes to define a new instruction, which we will call INIT. INIT initializes a region of up to 6 memory words with a specific value in each location. The instruction format for INIT is: INIT 1 1 S Base Amount6 where, the starting address of the region is specified in Base, the number of words is specified in Amount6, and the value to be written to each location is specified in S. For example, if =x5, 1=x, execution of INIT 1,, #5 would produce the result shown below. x5 x5 x5 1 x5 x54 x54 x56 6 x56 x58 4 x58 x5a x5a x5c 4 x5c 4 x5e x5e Your job: Implement INIT on the LC-b by making the required changes to both the state machine and data path, shown on the next two pages. (We will save the microsequencer changes for another day). 4

5 Problem continued: Part a (9 points): Fill in all boxes to complete the state machine for the path 11. Note: we have not asked you to specify which states (A, B, C, D) will be used. That is a microsequencer problem which we will save for another day. From State 5 BEN < I[11] & N I[1] & Z I[9] & P ADD AND... [I[15:1]] INIT... JMP B 1 BUS < CT A B [Z] Z Z C To state 18 D 5

6 Problem continued: Part b (4 points): The data path changes can be accomplished within the two dashed boxes shown. We have made the changes for one of them. Your job: the other. GateMAMUX GatePC LD.PC PC MAMUX PCMUX LD.EG EG FILE D ZEXT & LSHF1 LSHF1 ADD1MUX S S S1 OUT OUT S1 [:] ADDMUX [1:] [8:] [5:] [4:] CONTOL SMUX I[5:] N Z P LD.CC LD.I I ALUK B ALU A SHF 6 I[5:] GateALU GateSHF CT LD.CT MA LD.MA To Memory Module Part c ( points): The instruction just before INIT sets the condition codes. Can the instruction after INIT use those condition codes? Why or why not? Explain; 6

7 Problem 4 (5 points) Shown on the next page is a non-interleaved memory module containing a single byte addressable memory chip, and the logic to control the memory. Address space is bits. As Faruk described in class the address is broken into row bits (bits[15:8]) and column bits (bits[:]). A memory location is accessed in two stages. The first stage takes 8 cycles. In the first cycle, the row bits are loaded into the row address register, accompanied by the load control signal AS (row address strobe). The following seven cycles are needed to load the row buffer with the contents of all locations in the row. Then, the column bits are used to extract the desired byte from the row buffer. This takes one cycle. That is, a memory access takes 9 cycles total in general. However, if the next memory access is to the same row, we do not need to load the row buffer (since it is already loaded). We can immediately extract the byte from the row buffer in one cycle. In that case, a memory access takes only one cycle. Note the -bit counter (CT) which is useful in controlling the memory. It is initially set to zero. When COUNTUP is asserted, CT is incremented. Part a ( points): What is the purpose of the register TMP? Part b ( points): What does X=1 indicate? Part c ( points): What does Y=1 indicate? Part d ( points): Complete the output functions of the truth table. Note that some entries (labeled x) are don t cares. eaden X Y Z AS CAS LD.TMP COUNTUP x x x x 1 1 x x

8 Problem 4 continued: MA [15:8] [:] 1 8 Addr ow Addr TMP = X LD.TMP... ow Buffer... eaden = = Y Z AS CAS COUNTUP 8 CT eady MD 8

9 Problem 5 (5 points) The following program sums the contents of all memory locations in an array..oig x LEA 5, DATA LOCATION LDW, 5, # ; <- M[DATA LOCATION]:x6FFE LEA 5, LENGTH LDW 1, 5, # ; 1 <- M[LENGTH]:x4 AND,, # LOOP LDB,, # ; get the next integer ADD,, ADD,, #1 ; increment the pointer ADD 1, 1, #-1 ; decrement the iteration count Bp LOOP ; go to next iteration HALT DATA LOCATION LENGTH.FILL x6ffe.fill x4.end Assume the program executes on an implementation of the LC-b that supports virtual memory. The -bit addresses you are familiar with are virtual addresses. Physical memory is 8KB. Page size is 51 bytes. Part a (1 point): How many frames of physical memory are there? The memory management system uses the two-level page table scheme similar to the VAX. Virtual memory is partitioned into two halves. User space starts at x, System space starts at x8. The high bit specifies whether you are in user space or system space. A PTE is bits. For purposes of this question only, we will assume the PTE has the following form: V.. PFN Part b (1 point): How many bits in PFN? Also assume for this problem that the microarchitecture has an 8-entry TLB which contains PTEs for user space only. Assume the TLB is empty before the above program executes. The table on the next page lists in sequence the first nine physical memory accesses required by the LDB instruction to fetch data from the memory array. The table ignores all physical memory accesses due to fetching instructions. When the program starts executing, memory locations x6ffe, x6fff,..., xfd all contain the value #5. 9

10 Problem 5 continued: Part c ( points): Complete the table. Virtual Address Physical Address Data TLB Hit x1 x8f x81e x6ffe x1bff x5 x8a Part d (4 point): System Base egister: User Base egister: Part e ( points): How many physical memory accesses are required to satisfy all data accesses of the LDB instruction in the execution of the entire program? 1

11 ADD ADD D S1 S 1 D S1 1 imm5 AND AND D S1 S D S1 1 imm5 B n z p PCoffset9 JMP 11 Base JS 1 1 PCoffset11 JS 1 Base LDB 1 D Base boffset6 LDW 11 D Base offset6 LEA NOT 111 D 11 D S PCoffset ET TI LSHF SHFL SHFA D S amount4 111 D S 1 amount4 111 D S 1 1 amount4 STB 11 S Base boffset6 STW 111 S Base offset6 TAP 1111 trapvect8 XO XO 11 D S1 11 D S S 1 imm5 not used 11 not used 111 Figure 1: LC-b Instruction Encodings 11

12 MA < PC PC < PC 18, 19 MD < M I < MD 5 To 8 TI ADD BEN< I[11] & N I[1] & Z I[9] & P [I[15:1]] B To 11 To 1 D< S1OP* D< S1&OP* 1 5 AND XO TAP SHF LEA LDB LDW STW STB JS JMP [BEN] 1 PC< PCLSHF(off9,1) 9 D< S1 XO OP* 1 PC< Base MA< LSHF(ZEXT[I[:]],1) 15 4 [I[11]] 8 MD< M[MA] < PC PC< MD 1 < PC PC< Base 1 < PC PC< PCLSHF(off11,1) 1 D< SHF(S,A,D,amt4) 14 D< PCLSHF(off9, 1) MA< Boff6 6 MA< BLSHF(off6,1) MA< BLSHF(off6,1) MA< Boff NOTES Boff6 : Base [offset6] PCoff9 : PC [offset9] *OP may be S or [imm5] ** [15:8] or [:] depending on MA[] MD< M[MA[15:1] ] 1 D< [BYTE.DATA] MD< M[MA] D< MD MD< S M[MA]< MD MD< S[:] 1 M[MA]< MD** To 19 Figure : A state machine for the LC-b 1

13 GateMAMUX GatePC LD.PC PC ZEXT & LSHF1 MAMUX LSHF1 PCMUX ADD1MUX LD.EG S S OUT EG FILE S1 OUT D S1 [:] ADDMUX [1:] [8:] SMUX [5:] [4:] CONTOL LD.I I LD.CC N Z P B A ALUK ALU SHF 6 I[5:] GateALU GateSHF GateMD MA LD. MA DATA.SIZE MA[] WE1 WE WE MEMOY [].W DATA. SIZE ADD. CTL. MIO.EN INPUT KBD KBS DD OUTPUT DS MD LD. MD MEM.EN MIO.EN DATA.SIZE MA[] INMUX Figure : The LC-b data path 1