Department of Electrical and Computer Engineering The University of Texas at Austin

Transcription

1 Department of Electrical and Computer Engineering The University of Texas at Austin EE 360N, Fall 003 Yale Patt, Instructor Santhosh Srinath, Danny Lynch, TAs Exam 1, October 0, 003 Name: Problem 1 (0 points): Problem (0 points): Problem 3 (0 points): Problem 4 (0 points): Problem 5 (0 points): Total (100 points): Note: Please be sure that your answers to all questions (and all supporting work that is required) are contained in the space provided. Note: Please be sure your name is recorded on each sheet of the exam. GOOD LUCK!

2 Problem 1 (0 points): Part a (5 points): All of the following are important considerations that every manufacturer deals with in the design of its next microprocessor. Circle all those that are provided to increase performance of the executing program: compatibility unaligned accesses memory interleaving a TLB virtual memory Part b (5 points): A process is running at priority k, when a page fault occurs. The page fault should be serviced at priority: >k, =k, <k. Circle one. Explain in ten words or less. Part c (5 points): Two structures already discussed in class that can be classified as content addressable memories are and Part d (5 points): Since the microarchitect is able to use all the internal structures of the microarchitecture to his/her convenience, what is the first thing the hardware has to do in dealing with an exception or interrupt? Ten words or less, please.

3 Problem (0 points): A -way set associative write back cache with perfect LU replacement requires 15 x 9 bits of storage to implement its tag store. The cache is virtually indexed, physically tagged. The virtual address space is one megabyte; page size is KB; cache block size is 8 bytes. Part a (10 points) What is the size of the data store of the cache (CacheD) in bytes. Part b (5 points) How many bits of the virtual index come from the virtual page number? Part c (5 points) What is the physical address space of this memory system? 3

4 Problem 3 (0 points): We wish to add virtual memory to the LC-3b. What we have been calling addresses thus far will now be called virtual addresses. That is, VA space is bytes. We wish to specify our memory management system in a way similar to the VAX, which we have studied. However, we will only designate 1/8 of the VA space as system space, specifically the last 1/8 of the VA space (locations xe000 to xffff). Assume PA space is 10 bytes, and page size is 6 bytes. Page tables are formed in the same way we did for the VAX, with each PTE containing 3 access control bits, a reference bit (unlike the VAX), and other bits that make sense. The P0B is xe040. The SB is 0x00. Part a (3 points) What is the appropriate size for a PTE? Part b (5 points) What is the maximum size of the system page table? Part c (6 points) The VA of Y is x008. What is the VA of the PTE of the page containing Y? Part d (6 points) The VA of Z is xe100. What is the PA of the PTE of the page containing Z? 4

5 Problem 4 (0 points): A four-way interleaved, byte-addressable memory is shown in the figure. We can load one MA each successive cycle if necessary. It takes ten cycles after the MA is loaded, to load the corresponding MD with the contents of the memory locations in its respective memory array. It takes an additional cycle to gate MD onto the bus and load its contents into TEMP. The processor supports unaligned memory accesses. LDBIG loads 64 bits from memory into a register. A A k MA3 MD MA MA1 MD MD1 MA0 MD TEMP Part a (3 points) Note the address labeled Ak. What is k? Part b (3 points) How many LD ENABLE signals are required for TEMP? Part c (4 points) Consider LDBIG 3, B, where B is a multiple of 8. How many cycles are required to get the contents of B into TEMP, after the appropriate MA is loaded with B. 5

6 Problem 4 continued: Part d (5 points) edo Part c if B is decimal 800. Part e (5 points) In Part d, which LD ENABLE signals of TEMP are asserted in the cycle where TEMP is loaded with its final value (the contents of B). 6

7 Problem 5 (0 points): We wish to add to the LC-3b the new instruction MSUM, which adds the contents of k consecutive memory locations, and stores the result in one of the general purpose registers. The condition codes will be set according to whether the result is negative, zero, or positive. We will use the unused opcode 1010 for this purpose. The format of the instruction will be MSUM D, Base, Length 1010 D Base Length where the address of the first location to be added is in Base, and the number of locations to be added is in Length. If Length is initially 0, MSUM stores 0 in D. There is no requirement that the contents of Base or Length remain unchanged at the end of this instruction s execution. Example: After the instruction MSUM 1,,3 is executed, where contains x4000, 3 contains #5, and memory is as shown below, 1 will contain the value #8, and condition P will be set. x x4001 x400 x4003 x

8 Problem 5 continued: To implement MSUM, we have chosen to add the following to the LC-3b data path: 1. A new TEMP register, which is sourced from the output of the ALU. This requires a new control signal, LD TEMP.. A four-input MUX to the A input of the ALU. This requires a new control field, AMUX, specified as follows: S1/00, the S1 source from the original data path, MINUS1/01, a constant -1, ZEO/10, a constant 0, TEMP/11, the contents of the new TEMP register. 3. A two-input MUX to the B input of the ALU. This requires a new control signal, BMUX, specified as follows: SMUX/0, the SMUX output from the original data path, BUS/1, the contents on the bus. 4. A third input (I[:0]) to the DMUX. This requires extending the DMUX control field to bits: I[11:9]/00, 111/01, I[:0]/10 I[11:9] 111 I[:0] DMUX SEXT(I[4:0]) DMUX LD.EG 3 EG FILE 3 S S1 3 S OUT OUT S1 SMUX 1 0 BMUX BMUX AMUX TEMP LD.TEMP ALUK B ALU A AMUX GateALU 8

9 Problem 5 continued: 5. We have also added a BENMUX at the input of the BEN register, as shown. This requires a new control signal, BENMUX, specified as follows: Logic/0 BUS[15]/1 I[11:9] N Z P Logic BUS[15] BEN BENMUX LD.BEN Part a. (1 points): We have provided the skeleton of the augmented LC-3b state machine for you to implement MSUM. Using the notation we have adopted for the LC-3b, show what happens in every state. Specify the assignment (i.e, the state number) of each state you use. The five states should be selected from the set 56, 58, 60, 61, 63. Note that state 10, the first state after decode, has both been assigned its state number (i.e., 10 ) and also has been filled in. from 3 TEMP <

10 Problem 5 continued: Part b. (8 points): Specify the control signals required (for both data path control and microsequencer control) to implement each state. Note that we have added control signals corresponding to our changes in the data path. ID Cond J LD.MA LD.MD LD.I LD.BEN LD.EG LD.CC LD.PC GatePC GateMD GateALU GateMAMUX PCMUX DMUX S1MUX ADD1MUX ADDMUX MAMUX ALUK MIO.EN.W LD.TEMP BENMUX AMUX BMUX

11 LC-3b ISA ADD ADD D S S 0001 D S1 1 imm5 AND AND D S S D S1 1 imm5 B 0000 n z p PCoffset9 JMP Base JS PCoffset11 JS Base LDB 0010 D Base boffset6 LDW 0110 D Base offset6 LEA NOT 1110 D 1001 D S PCoffset ET TI LSHF SHFL SHFA D S 0 0 amount D S 0 1 amount D S 1 1 amount4 STB 0011 S Base boffset6 STW 0111 S Base offset6 TAP trapvect8 XO XO 1001 D S D S 0 00 S 1 imm5 not used not used indicates instructions that modify condition codes. 11

12 A state machine for the LC-3b (from Appendix C) MA < PC PC < PC 18, 19 MD < M 33 I < MD 35 To 8 TI ADD 3 BEN< I[11] & N I[10] & Z I[9] & P [I[15:1]] B To 11 To 10 D< S1OP* set CC D< S1&OP* set CC 1 5 AND XO TAP SHF LEA LDB LDW STW STB JS JMP 0 [BEN] 0 1 PC< PCLSHF(off9,1) 9 D< S1 XO OP* set CC 1 PC< Base MA< LSHF(ZEXT[I[7:0]],1) < PC [I[11]] 8 MD< M[MA] 7< PC PC< MD 30 0 PC< Base PC< PCLSHF(off11,1) 13 D< SHF(S,A,D,amt4) set CC D< PCLSHF(off9,1) set CC 14 MA< Boff6 6 MA< BLSHF(off6,1) MA< BLSHF(off6,1) 7 3 MA< Boff NOTES Boff6 : Base SEXT[offset6] PCoff9 : PC SEXT[offset9] *OP may be S or SEXT[imm5] ** [15:8] or [7:0] depending on MA[0] MD< M[MA[15:1] 0] 31 D< SEXT[BYTE.DATA] set CC MD< M[MA] 7 D< MD set CC MD< S M[MA]< MD MD< S[7:0] 17 M[MA]< MD** To 19 1

13 The LC-3b datapath (from Appendix C) GateMAMUX GatePC LD.PC PC ZEXT & LSHF1 MAMUX LSHF1 PCMUX ADD1MUX LD.EG 3 S S OUT EG FILE S1 OUT 3 3 D S1 [7:0] ADDMUX [10:0] SEXT 0 [8:0] SEXT SMUX [5:0] [4:0] SEXT SEXT CONTOL LD.I I LD.CC N Z P B A ALUK ALU SHF 6 I[5:0] LOGIC GateALU GateSHF GateMD MA LD.MA LOGIC DATA.SIZE MA[0] WE1WE0 WE LOGIC MEMOY [0].W DATA. SIZE ADD. CTL. LOGIC MIO.EN INPUT KBD KBS DD OUTPUT DS MD MEM.EN MIO.EN LOGIC DATA.SIZE MA[0] INMUX 13

14 The Microsequencer of the LC-3b base machine (from Appendix C) COND1 COND0 BEN I[11] Branch eady Addr. Mode J[5] J[4] J[3] J[] J[1] J[0] 0,0,I[15:1] 6 ID 6 Address of Next State 14