COSC 6385 Computer Architecture Dynamic Branch Prediction
|
|
- Elaine Gray
- 5 years ago
- Views:
Transcription
1 COSC 6385 Computer Architecture Dynamic Branch Prediction Edgar Gabriel Spring 208 Pipelining Pipelining allows for overlapping the execution of instructions Limitations on the (pipelined) execution of instruction Data Dependencies Control Dependencies Minimizing the effect of the limitations can be done in Hardware Software (Compiler)
2 Branch prediction No instruction is allowed to initiate execution until all branches preceding the instruction have completed How to deal with control hazards Stall the pipeline until we know the next fetch address Guess the next fetch address (branch prediction) Employ delayed branching (branch delay slot) Do something else (fine-grained multithreading) Eliminate control-flow instructions (predicated execution) Fetch from both possible paths (multipath execution) Slide based on a lecture by Onur Mutlu, Carnegie Mellon University branch-prediction-afterlecture.pdf Idea: Predict the next fetch address (to be used in the next cycle) Requires three things to be predicted at fetch stage: Whether the fetched instruction is a branch (Conditional) branch direction Branch target address (if taken) In most instances, target address remains the same for a branch instruction across multiple instances Branch Target Buffer: Store the target address from previous instance and access it with the Program Counter Slide based on a lecture by Onur Mutlu, Carnegie Mellon University branch-prediction-afterlecture.pdf 2
3 An example for ( i=0; i < 000 ; i++ ) { x[i] = x[i] + s; } Loop: L.D F0, 0(R) ADD.D F4, F0, F2 S.D F4, 0(R) ADD R, R, #8 BNE R, R2, Loop Dynamic branch prediction Algorithms using the previous execution of a branch to predict the outcome of the next execution Several techniques for dynamic branch prediction bit branch prediction buffer 2bit branch prediction buffer Correlating Branch Prediction Buffer Tournament predictors Tagged hybrid predictors 3
4 bit Branch prediction buffer (I) Branch prediction buffer: Small memory area indexed by the lower portion of the address of the branch instruction Records whether the branch was taken the last time or not ( bit is sufficient) Address of branch instruction tag BTB index k-bits Branch Target Buffer (BTB) bit per entry 2 k entries Prediction for this branch bit BTB entry is updated after actual outcome of the branch is known Slide based on a lecture by Milos Prvulovic, Georgia Institute of Technology -bit predictor using Branch Target Address Address of branch instruction tag BTB index k-bits tag -bit Branch Target Address =? Instruction found in BTB? prediction next PC PC+4 Slide based on a lecture by Onur Mutlu, Carnegie Mellon University branch-prediction-afterlecture.pdf 4
5 bit Branch Prediction Buffer Limitations Even for a regular loop (embedded in another large loop) the bit Branch Prediction Buffer will mispredict at least the first and the last iteration st iteration: the bit has been set by the last iteration of the same loop to not-taken, but the branch will be taken Last iteration: the bit says taken, but the branch won t be taken 2bit Branch Prediction Buffer A prediction must miss twice before the prediction is changed Can be extended to n-bits Taken Predict taken Taken Not taken Taken Predict taken 0 Not taken Predict not taken 0 Not taken Taken Predict not taken 00 5
6 Correlated branches Partial correlations: one branch could test for cond, and another branch could test for cond && cond 2 (if cond is false, then the second branch can be predicted as false) Multiple correlations: one branch tests cond, a second tests cond 2, and a third tests cond cond 2 (which can always be predicted if the first two branches are known). Slide based on a lecture by Milos Prvulovic, Georgia Institute of Technology Correlated branches Local History What is the predicted outcome of Branch A given the outcomes of previous instances of Branch A? Global History What is the predicted outcome of Branch Z given the outcomes of (all/last n) previous branches A, B,, X and Y executed before Branch Z? Slide based on a lecture by Milos Prvulovic, Georgia Institute of Technology 6
7 Correlated branches For a (,) predictor: each branch has two different branch prediction buffers: Predictor used in case the previous branch in the application has not been taken X / Y Predictor used in case the previous branch in the application has been taken The content of the two branch prediction buffers are determined by the branch to which they belong (local history) Which of the two branch prediction buffers are used is depending on the outcome of the previous branch in the application (global history) Correlated branches - example if ( d==0 ) d = ; if ( d== ) BNEZ R, L!branch b MOV R, # L: ADD R3, R, #- L2: BNEZ R3, L2!branch b2 Initial value of d d==0? b Value of d before b2 d==? 2 No Taken 2 No Taken 0 Yes Not taken Yes Not taken 2 No Taken 2 No Taken 0 Yes Not taken Yes Not taken b2 7
8 Correlated branches - example d=? BPB b b act. BPB b2 B2 act. 2 NT/NT NT/NT the branch prediction buffers for the branches b and b2 are assumed to hold the prediction Not taken for both option (previous branch not taken/taken) Correlated branches - example d=? BPB b b act. BPB b2 B2 act. 2 NT/NT NT/NT assuming BPB for b uses the Not Taken predictor because the previous branch in the application has not been taken BPB for b predicts that b will not be taken 8
9 Correlated branches - example d=? BPB b b act. BPB b2 B2 act. 2 NT/NT T NT/NT BPB for b predicts that b will not be taken b is taken (see table for d=2) Initial value of d d==0? b Value of d before b2 d==? 2 No Taken 2 No Taken 0 Yes Not taken Yes Not taken b2 Correlated branches - example d=? BPB b b act. BPB b2 B2 act. 2 NT/NT T NT/NT T/NT updating the Previous branch has not been taken part of BPB for b to Taken because b has been taken, the last branch has been taken part of BPB b2 will be used BPB b2 predicts, that b2 will not be taken 9
10 Correlated branches - example d=? BPB b b act. BPB b2 B2 act. 2 NT/NT T NT/NT T T/NT NT/T b2 is taken (see table for d=2) updating the Previous branch has been taken part of BPB for b2 to Taken because b2 has been taken, the last branch has been taken part of BPB b will be used Initial BPB value b predicts, d==0? that b will b not be Value taken of d d==? b2 of d before b2 2 No Taken 2 No Taken 0 Yes Not taken Yes Not taken Correlated branches - example d=? BPB b b act. BPB b2 B2 act. 2 NT/NT T NT/NT T 0 T/NT NT NT/T b is not taken (see table for d=0) matches prediction! update of BPB b does not modify any entry taken because b has not been taken, the last branch has not been taken part of BPB b2 will be used BPB b2 predicts that b2 will not be taken Initial value of d d==0? b Value of d before b2 d==? 2 No Taken 2 No Taken 0 Yes Not taken Yes Not taken b2 0
11 Correlated branches A (2,) correlated branch predictor Uses outcome of the last 2 branches to choose from 2 2 different predictions Uses a bit predictor for each of the 4 prediction buffers Predictor used in case the previous 2 branches in the application have both not been taken (00) Predictor used in case the previous branches have the history :second last branch not taken, last branch taken (0) Predictor used in case the previous branches have the history: second last branch taken, last branch not taken (0) Predictor used in case the previous 2 branches in the application have both been taken () A / B / C / D Correlated branches How do we know which of the four sections of our branch predictor to use Need to record the behavior of all branches in the application Initial value of d d==0? b Value of d before b2 d==? 2 No Taken 2 No Taken 0 Yes Not taken Yes Not taken 2 No Taken 2 No Taken 0 Yes Not taken Yes Not taken b2 e.g
12 Frequency of Mispredictions Frequency of Mispredictions Global branch history For a (2,n) branch predictor, the outcome of last two branches is relevant bit global branch history implemented using a 2bit shift register 6% 4% Accuracy of Different Schemes 20% 8% 8% 4096 Entries 2-bit BHT Unlimited Entries 2-bit BHT 024 Entries (2,2) BHT 2% % 0% 8% 6% 4% 0% 2% 0% 6% 6% 6% 5% 5% 4% % % 0% nasa7 matrix300 tomcatv doducd spice fpppp gcc espresso eqntott li 4,096 entries: 2-bits per entry Unlimited entries: 2-bits/entry,024 entries (2,2) Slide based on a lecture by David A. Patterson, University of California, Berkley 2
13 Tournament predictors Combine multiple prediction algorithms Use a predictor to predict which predictor works best Keeps track which predictor was the most accurate for the last execution of a branch Allows to use different prediction algorithms for different types of branches 3
14 Gshare predictor Another example of a correlating branch predictor Combines branch history and branch address to determine index in a branch predictor table Branch history (e.g. 0 bit) Branch address XOR bit predictors 0 prediction TAGE: Tagged hybrid predictor Uses the same algorithm but for different history length Some branches are detected to require long history, while others are predicted accurately with short history Index calculated using a hash of branch history and branch address (of various history length) Entries in history tables are uniquely identified by a tag Tag can be short ( 4-8 bits) since hash already had to match Allows to avoid accidental matches by two different branch instructions to the same entry A prediction is only used if tags match and hash match The prediction for a given branch is the predictor with the longest branch history 4
15 Base predictor prediction tag prediction tag prediction tag prediction tag TAGE: Tagged hybrid predictor P(0) pc pc h(0:9) pc h(0:9) pc h(0:39) pc h(0:79) hash hash hash hash hash hash hash hash P() =? =? =? =? 5
COSC 6385 Computer Architecture. Instruction Level Parallelism
COSC 6385 Computer Architecture Instruction Level Parallelism Spring 2013 Instruction Level Parallelism Pipelining allows for overlapping the execution of instructions Limitations on the (pipelined) execution
More informationTomasulo Loop Example
Tomasulo Loop Example Loop: LD F0 0 R1 MULTD F4 F0 F2 SD F4 0 R1 SUBI R1 R1 #8 BNEZ R1 Loop This time assume Multiply takes 4 clocks Assume 1st load takes 8 clocks, 2nd load takes 1 clock Clocks for SUBI,
More informationDynamic Hardware Prediction. Basic Branch Prediction Buffers. N-bit Branch Prediction Buffers
Dynamic Hardware Prediction Importance of control dependences Branches and jumps are frequent Limiting factor as ILP increases (Amdahl s law) Schemes to attack control dependences Static Basic (stall the
More informationCSE4201 Instruction Level Parallelism. Branch Prediction
CSE4201 Instruction Level Parallelism Branch Prediction Prof. Mokhtar Aboelaze York University Based on Slides by Prof. L. Bhuyan (UCR) Prof. M. Shaaban (RIT) 1 Introduction With dynamic scheduling that
More informationLecture 8 Dynamic Branch Prediction, Superscalar and VLIW. Computer Architectures S
Lecture 8 Dynamic Branch Prediction, Superscalar and VLIW Computer Architectures 521480S Dynamic Branch Prediction Performance = ƒ(accuracy, cost of misprediction) Branch History Table (BHT) is simplest
More informationInstruction Fetch and Branch Prediction. CprE 581 Computer Systems Architecture Readings: Textbook (4 th ed 2.3, 2.9); (5 th ed 3.
Instruction Fetch and Branch Prediction CprE 581 Computer Systems Architecture Readings: Textbook (4 th ed 2.3, 2.9); (5 th ed 3.3) 1 Frontend and Backend Feedback: - Prediction correct or not, update
More informationComputer Architecture: Branch Prediction. Prof. Onur Mutlu Carnegie Mellon University
Computer Architecture: Branch Prediction Prof. Onur Mutlu Carnegie Mellon University A Note on This Lecture These slides are partly from 18-447 Spring 2013, Computer Architecture, Lecture 11: Branch Prediction
More informationCS422 Computer Architecture
CS422 Computer Architecture Spring 2004 Lecture 14, 18 Feb 2004 Bhaskaran Raman Department of CSE IIT Kanpur http://web.cse.iitk.ac.in/~cs422/index.html Dealing with Control Hazards Software techniques:
More informationCS252 S05. Outline. Dynamic Branch Prediction. Static Branch Prediction. Dynamic Branch Prediction. Dynamic Branch Prediction
Outline CMSC Computer Systems Architecture Lecture 9 Instruction Level Parallelism (Static & Dynamic Branch ion) ILP Compiler techniques to increase ILP Loop Unrolling Static Branch ion Dynamic Branch
More informationPage 1. CISC 662 Graduate Computer Architecture. Lecture 8 - ILP 1. Pipeline CPI. Pipeline CPI (I) Pipeline CPI (II) Michela Taufer
CISC 662 Graduate Computer Architecture Lecture 8 - ILP 1 Michela Taufer Pipeline CPI http://www.cis.udel.edu/~taufer/teaching/cis662f07 Powerpoint Lecture Notes from John Hennessy and David Patterson
More informationInstruction Level Parallelism (Branch Prediction)
Instruction Level Parallelism (Branch Prediction) Branch Types Type Direction at fetch time Number of possible next fetch addresses? When is next fetch address resolved? Conditional Unknown 2 Execution
More informationBranch Prediction Chapter 3
1 Branch Prediction Chapter 3 2 More on Dependencies We will now look at further techniques to deal with dependencies which negatively affect ILP in program code. A dependency may be overcome in two ways:
More informationAdministrivia. CMSC 411 Computer Systems Architecture Lecture 14 Instruction Level Parallelism (cont.) Control Dependencies
Administrivia CMSC 411 Computer Systems Architecture Lecture 14 Instruction Level Parallelism (cont.) HW #3, on memory hierarchy, due Tuesday Continue reading Chapter 3 of H&P Alan Sussman als@cs.umd.edu
More informationInstruction-Level Parallelism and Its Exploitation (Part III) ECE 154B Dmitri Strukov
Instruction-Level Parallelism and Its Exploitation (Part III) ECE 154B Dmitri Strukov Dealing With Control Hazards Simplest solution to stall pipeline until branch is resolved and target address is calculated
More informationReduction of Control Hazards (Branch) Stalls with Dynamic Branch Prediction
ISA Support Needed By CPU Reduction of Control Hazards (Branch) Stalls with Dynamic Branch Prediction So far we have dealt with control hazards in instruction pipelines by: 1 2 3 4 Assuming that the branch
More informationLecture 8: Compiling for ILP and Branch Prediction. Advanced pipelining and instruction level parallelism
Lecture 8: Compiling for ILP and Branch Prediction Kunle Olukotun Gates 302 kunle@ogun.stanford.edu http://www-leland.stanford.edu/class/ee282h/ 1 Advanced pipelining and instruction level parallelism
More informationTopics. Digital Systems Architecture EECE EECE Predication, Prediction, and Speculation
Digital Systems Architecture EECE 343-01 EECE 292-02 Predication, Prediction, and Speculation Dr. William H. Robinson February 25, 2004 http://eecs.vanderbilt.edu/courses/eece343/ Topics Aha, now I see,
More informationInstruction-Level Parallelism. Instruction Level Parallelism (ILP)
Instruction-Level Parallelism CS448 1 Pipelining Instruction Level Parallelism (ILP) Limited form of ILP Overlapping instructions, these instructions can be evaluated in parallel (to some degree) Pipeline
More informationInstruction-Level Parallelism Dynamic Branch Prediction. Reducing Branch Penalties
Instruction-Level Parallelism Dynamic Branch Prediction CS448 1 Reducing Branch Penalties Last chapter static schemes Move branch calculation earlier in pipeline Static branch prediction Always taken,
More informationECE 571 Advanced Microprocessor-Based Design Lecture 7
ECE 571 Advanced Microprocessor-Based Design Lecture 7 Vince Weaver http://www.eece.maine.edu/~vweaver vincent.weaver@maine.edu 9 February 2016 HW2 Grades Ready Announcements HW3 Posted be careful when
More informationPipelining. Ideal speedup is number of stages in the pipeline. Do we achieve this? 2. Improve performance by increasing instruction throughput ...
CHAPTER 6 1 Pipelining Instruction class Instruction memory ister read ALU Data memory ister write Total (in ps) Load word 200 100 200 200 100 800 Store word 200 100 200 200 700 R-format 200 100 200 100
More informationPage # CISC 662 Graduate Computer Architecture. Lecture 8 - ILP 1. Pipeline CPI. Pipeline CPI (I) Michela Taufer
CISC 662 Graduate Computer Architecture Lecture 8 - ILP 1 Michela Taufer http://www.cis.udel.edu/~taufer/teaching/cis662f07 Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationBranch prediction ( 3.3) Dynamic Branch Prediction
prediction ( 3.3) Static branch prediction (built into the architecture) The default is to assume that branches are not taken May have a design which predicts that branches are taken It is reasonable to
More informationECE473 Computer Architecture and Organization. Pipeline: Control Hazard
Computer Architecture and Organization Pipeline: Control Hazard Lecturer: Prof. Yifeng Zhu Fall, 2015 Portions of these slides are derived from: Dave Patterson UCB Lec 15.1 Pipelining Outline Introduction
More informationDesign of Digital Circuits Lecture 18: Branch Prediction. Prof. Onur Mutlu ETH Zurich Spring May 2018
Design of Digital Circuits Lecture 18: Branch Prediction Prof. Onur Mutlu ETH Zurich Spring 2018 3 May 2018 Agenda for Today & Next Few Lectures Single-cycle Microarchitectures Multi-cycle and Microprogrammed
More informationCISC 662 Graduate Computer Architecture Lecture 11 - Hardware Speculation Branch Predictions
CISC 662 Graduate Computer Architecture Lecture 11 - Hardware Speculation Branch Predictions Michela Taufer http://www.cis.udel.edu/~taufer/teaching/cis6627 Powerpoint Lecture Notes from John Hennessy
More informationECE 571 Advanced Microprocessor-Based Design Lecture 9
ECE 571 Advanced Microprocessor-Based Design Lecture 9 Vince Weaver http://www.eece.maine.edu/ vweaver vincent.weaver@maine.edu 30 September 2014 Announcements Next homework coming soon 1 Bulldozer Paper
More informationECE 571 Advanced Microprocessor-Based Design Lecture 8
ECE 571 Advanced Microprocessor-Based Design Lecture 8 Vince Weaver http://web.eece.maine.edu/~vweaver vincent.weaver@maine.edu 16 February 2017 Announcements HW4 Due HW5 will be posted 1 HW#3 Review Energy
More informationLecture-13 (ROB and Multi-threading) CS422-Spring
Lecture-13 (ROB and Multi-threading) CS422-Spring 2018 Biswa@CSE-IITK Cycle 62 (Scoreboard) vs 57 in Tomasulo Instruction status: Read Exec Write Exec Write Instruction j k Issue Oper Comp Result Issue
More informationSome material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slides Some material adapted from Hennessy & Patterson / 2003 Elsevier
Some material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slides Some material adapted from Hennessy & Patterson / 2003 Elsevier Science ! CPI = (1-branch%) * non-branch CPI + branch% *
More informationInstruction Level Parallelism. Taken from
Instruction Level Parallelism Taken from http://www.cs.utsa.edu/~dj/cs3853/lecture5.ppt Outline ILP Compiler techniques to increase ILP Loop Unrolling Static Branch Prediction Dynamic Branch Prediction
More informationLecture 15: Instruc.on Level Parallelism -- Introduc.on, Compiler Techniques, and Advanced Branch Predic.on
Lecture 15: Instruc.on Level Parallelism -- Introduc.on, Compiler Techniques, and Advanced Branch Predic.on CSE 564 Computer Architecture Summer 2017 Department of Computer Science and Engineering Yonghong
More informationDynamic Control Hazard Avoidance
Dynamic Control Hazard Avoidance Consider Effects of Increasing the ILP Control dependencies rapidly become the limiting factor they tend to not get optimized by the compiler more instructions/sec ==>
More informationAnnouncements. ECE4750/CS4420 Computer Architecture L10: Branch Prediction. Edward Suh Computer Systems Laboratory
ECE4750/CS4420 Computer Architecture L10: Branch Prediction Edward Suh Computer Systems Laboratory suh@csl.cornell.edu Announcements Lab2 and prelim grades Back to the regular office hours 2 1 Overview
More informationFunctional Units. Registers. The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Input Control Memory
The Big Picture: Where are We Now? CS152 Computer Architecture and Engineering Lecture 18 The Five Classic Components of a Computer Processor Input Control Dynamic Scheduling (Cont), Speculation, and ILP
More informationHY425 Lecture 05: Branch Prediction
HY425 Lecture 05: Branch Prediction Dimitrios S. Nikolopoulos University of Crete and FORTH-ICS October 19, 2011 Dimitrios S. Nikolopoulos HY425 Lecture 05: Branch Prediction 1 / 45 Exploiting ILP in hardware
More informationMulticycle ALU Operations 2/28/2011. Diversified Pipelines The Path Toward Superscalar Processors. Limitations of Our Simple 5 stage Pipeline
//11 Limitations of Our Simple stage Pipeline Diversified Pipelines The Path Toward Superscalar Processors HPCA, Spring 11 Assumes single cycle EX stage for all instructions This is not feasible for Complex
More informationInstruction Level Parallelism
Instruction Level Parallelism The potential overlap among instruction execution is called Instruction Level Parallelism (ILP) since instructions can be executed in parallel. There are mainly two approaches
More informationNOW Handout Page 1. Outline. Csci 211 Computer System Architecture. Lec 4 Instruction Level Parallelism. Instruction Level Parallelism
Outline Csci 211 Computer System Architecture Lec 4 Instruction Level Parallelism Xiuzhen Cheng Department of Computer Sciences The George Washington University ILP Compiler techniques to increase ILP
More informationBranch statistics. 66% forward (i.e., slightly over 50% of total branches). Most often Not Taken 33% backward. Almost all Taken
Branch statistics Branches occur every 4-7 instructions on average in integer programs, commercial and desktop applications; somewhat less frequently in scientific ones Unconditional branches : 20% (of
More informationControl Hazards. Prediction
Control Hazards The nub of the problem: In what pipeline stage does the processor fetch the next instruction? If that instruction is a conditional branch, when does the processor know whether the conditional
More informationOutline EEL 5764 Graduate Computer Architecture. Chapter 3 Limits to ILP and Simultaneous Multithreading. Overcoming Limits - What do we need??
Outline EEL 7 Graduate Computer Architecture Chapter 3 Limits to ILP and Simultaneous Multithreading! Limits to ILP! Thread Level Parallelism! Multithreading! Simultaneous Multithreading Ann Gordon-Ross
More informationESE 545 Computer Architecture Instruction-Level Parallelism (ILP) and Static & Dynamic Instruction Scheduling Instruction level parallelism
Computer Architecture ESE 545 Computer Architecture Instruction-Level Parallelism (ILP) and Static & Dynamic Instruction Scheduling 1 Outline ILP Compiler techniques to increase ILP Loop Unrolling Static
More informationTDT 4260 lecture 7 spring semester 2015
1 TDT 4260 lecture 7 spring semester 2015 Lasse Natvig, The CARD group Dept. of computer & information science NTNU 2 Lecture overview Repetition Superscalar processor (out-of-order) Dependencies/forwarding
More informationInstruction Level Parallelism (ILP)
1 / 26 Instruction Level Parallelism (ILP) ILP: The simultaneous execution of multiple instructions from a program. While pipelining is a form of ILP, the general application of ILP goes much further into
More informationControl Hazards. Branch Prediction
Control Hazards The nub of the problem: In what pipeline stage does the processor fetch the next instruction? If that instruction is a conditional branch, when does the processor know whether the conditional
More informationECE 4750 Computer Architecture, Fall 2017 T13 Advanced Processors: Branch Prediction
ECE 4750 Computer Architecture, Fall 2017 T13 Advanced Processors: Branch Prediction School of Electrical and Computer Engineering Cornell University revision: 2017-11-20-08-48 1 Branch Prediction Overview
More informationDYNAMIC AND SPECULATIVE INSTRUCTION SCHEDULING
DYNAMIC AND SPECULATIVE INSTRUCTION SCHEDULING Slides by: Pedro Tomás Additional reading: Computer Architecture: A Quantitative Approach, 5th edition, Chapter 3, John L. Hennessy and David A. Patterson,
More informationNOW Handout Page 1. Review from Last Time. CSE 820 Graduate Computer Architecture. Lec 7 Instruction Level Parallelism. Recall from Pipelining Review
Review from Last Time CSE 820 Graduate Computer Architecture Lec 7 Instruction Level Parallelism Based on slides by David Patterson 4 papers: All about where to draw line between HW and SW IBM set foundations
More informationCSE 502 Graduate Computer Architecture. Lec 8-10 Instruction Level Parallelism
CSE 502 Graduate Computer Architecture Lec 8-10 Instruction Level Parallelism Larry Wittie Computer Science, StonyBrook University http://www.cs.sunysb.edu/~cse502 and ~lw Slides adapted from David Patterson,
More informationInstruction-Level Parallelism and Its Exploitation
Chapter 2 Instruction-Level Parallelism and Its Exploitation 1 Overview Instruction level parallelism Dynamic Scheduling Techniques es Scoreboarding Tomasulo s s Algorithm Reducing Branch Cost with Dynamic
More informationLooking for Instruction Level Parallelism (ILP) Branch Prediction. Branch Prediction. Importance of Branch Prediction
Looking for Instruction Level Parallelism (ILP) Branch Prediction We want to identify and exploit ILP instructions that can potentially be executed at the same time. Branches are 15-20% of instructions
More informationAdvanced Computer Architecture
Advanced Computer Architecture Instruction Level Parallelism Myung Hoon, Sunwoo School of Electrical and Computer Engineering Ajou University Outline ILP Compiler techniques to increase ILP Loop Unrolling
More informationTopic 14: Dealing with Branches
Topic 14: Dealing with Branches COS / ELE 375 Computer Architecture and Organization Princeton University Fall 2015 Prof. David August 1 FLASHBACK: Pipeline Hazards Control Hazards What is the next instruction?
More informationTopic 14: Dealing with Branches
Topic 14: Dealing with Branches COS / ELE 375 FLASHBACK: Pipeline Hazards Control Hazards What is the next instruction? Branch instructions take time to compute this. Stall, Predict, or Delay: Computer
More informationExploitation of instruction level parallelism
Exploitation of instruction level parallelism Computer Architecture J. Daniel García Sánchez (coordinator) David Expósito Singh Francisco Javier García Blas ARCOS Group Computer Science and Engineering
More informationCMSC 411 Computer Systems Architecture Lecture 13 Instruction Level Parallelism 6 (Limits to ILP & Threading)
CMSC 411 Computer Systems Architecture Lecture 13 Instruction Level Parallelism 6 (Limits to ILP & Threading) Limits to ILP Conflicting studies of amount of ILP Benchmarks» vectorized Fortran FP vs. integer
More information15-740/ Computer Architecture Lecture 29: Control Flow II. Prof. Onur Mutlu Carnegie Mellon University Fall 2011, 11/30/11
15-740/18-740 Computer Architecture Lecture 29: Control Flow II Prof. Onur Mutlu Carnegie Mellon University Fall 2011, 11/30/11 Announcements for This Week December 2: Midterm II Comprehensive 2 letter-sized
More informationReview Tomasulo. Lecture 17: ILP and Dynamic Execution #2: Branch Prediction, Multiple Issue. Tomasulo Algorithm and Branch Prediction
CS252 Graduate Computer Architecture Lecture 17: ILP and Dynamic Execution #2: Branch Prediction, Multiple Issue March 23, 01 Prof. David A. Patterson Computer Science 252 Spring 01 Review Tomasulo Reservations
More informationExercises (III) Output dependencies: Instruction 6 has output dependence with instruction 1 for access to R1
1) a)solution: Let s number instructions: 1. LD R1, 50(R2) 2. ADD R3, R1, R4 3. LD R5, 100(R3) 4. MUL R6, R5, R7 5. STORE R6, 50(R2) 6. ADD R1, R1, #100 7. SUB R2, R2, #8 b) Exercises (III) Data dependencies:
More informationLooking for Instruction Level Parallelism (ILP) Branch Prediction. Branch Prediction. Importance of Branch Prediction
Looking for Instruction Level Parallelism (ILP) Branch Prediction We want to identify and exploit ILP instructions that can potentially be executed at the same time. Branches are 5-20% of instructions
More informationLecture 5: VLIW, Software Pipelining, and Limits to ILP Professor David A. Patterson Computer Science 252 Spring 1998
Lecture 5: VLIW, Software Pipelining, and Limits to ILP Professor David A. Patterson Computer Science 252 Spring 1998 DAP.F96 1 Review: Tomasulo Prevents Register as bottleneck Avoids WAR, WAW hazards
More informationRecall from Pipelining Review. Instruction Level Parallelism and Dynamic Execution
332 Advanced Computer Architecture Chapter 4 Instruction Level Parallelism and Dynamic Execution January 2004 Paul H J Kelly These lecture notes are partly based on the course text, Hennessy and Patterson
More informationChapter 3 (CONT) Instructor: Josep Torrellas CS433. Copyright J. Torrellas 1999,2001,2002,2007,2013 1
Chapter 3 (CONT) Instructor: Josep Torrellas CS433 Copyright J. Torrellas 1999,2001,2002,2007,2013 1 Dynamic Hardware Branch Prediction Control hazards are sources of losses, especially for processors
More informationAppendix A.2 (pg. A-21 A-26), Section 4.2, Section 3.4. Performance of Branch Prediction Schemes
Module: Branch Prediction Krishna V. Palem, Weng Fai Wong, and Sudhakar Yalamanchili, Georgia Institute of Technology (slides contributed by Prof. Weng Fai Wong were prepared while visiting, and employed
More informationAs the amount of ILP to exploit grows, control dependences rapidly become the limiting factor.
Hiroaki Kobayashi // As the amount of ILP to exploit grows, control dependences rapidly become the limiting factor. Branches will arrive up to n times faster in an n-issue processor, and providing an instruction
More informationComputer Architecture Lecture 9: Branch Prediction I. Prof. Onur Mutlu Carnegie Mellon University Spring 2015, 2/4/2015
18-447 Computer Architecture Lecture 9: Branch Prediction I Prof. Onur Mutlu Carnegie Mellon University Spring 2015, 2/4/2015 Agenda for Today & Next Few Lectures Single-cycle Microarchitectures Multi-cycle
More informationControl Hazards - branching causes problems since the pipeline can be filled with the wrong instructions.
Control Hazards - branching causes problems since the pipeline can be filled with the wrong instructions Stage Instruction Fetch Instruction Decode Execution / Effective addr Memory access Write-back Abbreviation
More informationLecture 13: Branch Prediction
S 09 L13-1 18-447 Lecture 13: Branch Prediction James C. Hoe Dept of ECE, CMU March 4, 2009 Announcements: Spring break!! Spring break next week!! Project 2 due the week after spring break HW3 due Monday
More informationAppendix C. Authors: John Hennessy & David Patterson. Copyright 2011, Elsevier Inc. All rights Reserved. 1
Appendix C Authors: John Hennessy & David Patterson Copyright 2011, Elsevier Inc. All rights Reserved. 1 Figure C.2 The pipeline can be thought of as a series of data paths shifted in time. This shows
More informationUG4 Honours project selection: Talk to Vijay or Boris if interested in computer architecture projects
Announcements UG4 Honours project selection: Talk to Vijay or Boris if interested in computer architecture projects Inf3 Computer Architecture - 2017-2018 1 Last time: Tomasulo s Algorithm Inf3 Computer
More informationLecture 5: VLIW, Software Pipelining, and Limits to ILP. Review: Tomasulo
Lecture 5: VLIW, Software Pipelining, and Limits to ILP Professor David A. Patterson Computer Science 252 Spring 1998 DAP.F96 1 Review: Tomasulo Prevents Register as bottleneck Avoids WAR, WAW hazards
More informationPage 1. Today s Big Idea. Lecture 18: Branch Prediction + analysis resources => ILP
CS252 Graduate Computer Architecture Lecture 18: Branch Prediction + analysis resources => ILP April 2, 2 Prof. David E. Culler Computer Science 252 Spring 2 Today s Big Idea Reactive: past actions cause
More informationMetodologie di Progettazione Hardware-Software
Metodologie di Progettazione Hardware-Software Advanced Pipelining and Instruction-Level Paralelism Metodologie di Progettazione Hardware/Software LS Ing. Informatica 1 ILP Instruction-level Parallelism
More informationLecture 9: Case Study MIPS R4000 and Introduction to Advanced Pipelining Professor Randy H. Katz Computer Science 252 Spring 1996
Lecture 9: Case Study MIPS R4000 and Introduction to Advanced Pipelining Professor Randy H. Katz Computer Science 252 Spring 1996 RHK.SP96 1 Review: Evaluating Branch Alternatives Two part solution: Determine
More informationCSE 490/590 Computer Architecture Homework 2
CSE 490/590 Computer Architecture Homework 2 1. Suppose that you have the following out-of-order datapath with 1-cycle ALU, 2-cycle Mem, 3-cycle Fadd, 5-cycle Fmul, no branch prediction, and in-order fetch
More informationLecture 8: Instruction Fetch, ILP Limits. Today: advanced branch prediction, limits of ILP (Sections , )
Lecture 8: Instruction Fetch, ILP Limits Today: advanced branch prediction, limits of ILP (Sections 3.4-3.5, 3.8-3.14) 1 1-Bit Prediction For each branch, keep track of what happened last time and use
More informationFor this problem, consider the following architecture specifications: Functional Unit Type Cycles in EX Number of Functional Units
CS333: Computer Architecture Spring 006 Homework 3 Total Points: 49 Points (undergrad), 57 Points (graduate) Due Date: Feb. 8, 006 by 1:30 pm (See course information handout for more details on late submissions)
More informationLecture 12 Branch Prediction and Advanced Out-of-Order Superscalars
CS 152 Computer Architecture and Engineering CS252 Graduate Computer Architecture Lecture 12 Branch Prediction and Advanced Out-of-Order Superscalars Krste Asanovic Electrical Engineering and Computer
More informationCISC 662 Graduate Computer Architecture Lecture 13 - Limits of ILP
CISC 662 Graduate Computer Architecture Lecture 13 - Limits of ILP Michela Taufer http://www.cis.udel.edu/~taufer/teaching/cis662f07 Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer
More informationLecture 8: Branch Prediction, Dynamic ILP. Topics: static speculation and branch prediction (Sections )
Lecture 8: Branch Prediction, Dynamic ILP Topics: static speculation and branch prediction (Sections 2.3-2.6) 1 Correlating Predictors Basic branch prediction: maintain a 2-bit saturating counter for each
More informationStatic Branch Prediction
Static Branch Prediction Branch prediction schemes can be classified into static and dynamic schemes. Static methods are usually carried out by the compiler. They are static because the prediction is already
More informationChapter 4. Advanced Pipelining and Instruction-Level Parallelism. In-Cheol Park Dept. of EE, KAIST
Chapter 4. Advanced Pipelining and Instruction-Level Parallelism In-Cheol Park Dept. of EE, KAIST Instruction-level parallelism Loop unrolling Dependence Data/ name / control dependence Loop level parallelism
More informationCS433 Homework 2 (Chapter 3)
CS433 Homework 2 (Chapter 3) Assigned on 9/19/2017 Due in class on 10/5/2017 Instructions: 1. Please write your name and NetID clearly on the first page. 2. Refer to the course fact sheet for policies
More informationLecture Topics. Why Predict Branches? ECE 486/586. Computer Architecture. Lecture # 17. Basic Branch Prediction. Branch Prediction
Lecture Topics ECE 486/586 Computer Architecture Branch Prediction Reference: Chapter : Section. Lecture # 17 Spring 2015 Portland State University Why Predict Branches? The decision about control flow
More informationComplex Pipelines and Branch Prediction
Complex Pipelines and Branch Prediction Daniel Sanchez Computer Science & Artificial Intelligence Lab M.I.T. L22-1 Processor Performance Time Program Instructions Program Cycles Instruction CPI Time Cycle
More informationLecture Topics ECE 341. Lecture # 14. Unconditional Branches. Instruction Hazards. Pipelining
ECE 341 Lecture # 14 Instructor: Zeshan Chishti zeshan@ece.pdx.edu November 17, 2014 Portland State University Lecture Topics Pipelining Instruction Hazards Branch penalty Branch delay slot optimization
More informationISA P40 P36 P38 F6 F8 P34 P12 P14 P16 P18 P20 P22 P24
CS252 Graduate Computer Architecture Lecture 9 Prediction/Speculation (Branches, Return Addrs) February 15 th, 2011 John Kubiatowicz Electrical Engineering and Computer Sciences University of California,
More informationNOW Handout Page 1. COSC 5351 Advanced Computer Architecture
COSC 5351 Advanced Computer Slides modified from Hennessy CS252 course slides ILP Compiler techniques to increase ILP Loop Unrolling Static Branch Prediction Dynamic Branch Prediction Overcoming Data Hazards
More informationEI 338: Computer Systems Engineering (Operating Systems & Computer Architecture)
EI 338: Computer Systems Engineering (Operating Systems & Computer Architecture) Dept. of Computer Science & Engineering Chentao Wu wuct@cs.sjtu.edu.cn Download lectures ftp://public.sjtu.edu.cn User:
More informationOld formulation of branch paths w/o prediction. bne $2,$3,foo subu $3,.. ld $2,..
Old formulation of branch paths w/o prediction bne $2,$3,foo subu $3,.. ld $2,.. Cleaner formulation of Branching Front End Back End Instr Cache Guess PC Instr PC dequeue!= dcache arch. PC branch resolution
More informationAdapted from David Patterson s slides on graduate computer architecture
Mei Yang Adapted from David Patterson s slides on graduate computer architecture Introduction Basic Compiler Techniques for Exposing ILP Advanced Branch Prediction Dynamic Scheduling Hardware-Based Speculation
More informationTema 5: Processadors superescalars
Tema 5: Processadors superescalars duard Ayguadé i Josep Llosa These slides have been prepared using material available at: 1) the companion web site for Computer Organization & esign. The Hardware/Software
More informationLecture: Branch Prediction
Lecture: Branch Prediction Topics: branch prediction, bimodal/global/local/tournament predictors, branch target buffer (Section 3.3, notes on class webpage) 1 Pipeline without Branch Predictor PC IF (br)
More informationCOSC4201. Prof. Mokhtar Aboelaze York University
COSC4201 Chapter 3 Multi Cycle Operations Prof. Mokhtar Aboelaze York University Based on Slides by Prof. L. Bhuyan (UCR) Prof. M. Shaaban (RTI) 1 Multicycle Operations More than one function unit, each
More informationCISC 662 Graduate Computer Architecture Lecture 13 - Limits of ILP
CISC 662 Graduate Computer Architecture Lecture 13 - Limits of ILP Michela Taufer http://www.cis.udel.edu/~taufer/teaching/cis662f07 Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer
More informationHY425 Lecture 09: Software to exploit ILP
HY425 Lecture 09: Software to exploit ILP Dimitrios S. Nikolopoulos University of Crete and FORTH-ICS November 4, 2010 ILP techniques Hardware Dimitrios S. Nikolopoulos HY425 Lecture 09: Software to exploit
More informationHY425 Lecture 09: Software to exploit ILP
HY425 Lecture 09: Software to exploit ILP Dimitrios S. Nikolopoulos University of Crete and FORTH-ICS November 4, 2010 Dimitrios S. Nikolopoulos HY425 Lecture 09: Software to exploit ILP 1 / 44 ILP techniques
More informationCS433 Homework 2 (Chapter 3)
CS Homework 2 (Chapter ) Assigned on 9/19/2017 Due in class on 10/5/2017 Instructions: 1. Please write your name and NetID clearly on the first page. 2. Refer to the course fact sheet for policies on collaboration..
More information