Tomasulo Loop Example
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1 Tomasulo Loop Example Loop: LD F0 0 R1 MULTD F4 F0 F2 SD F4 0 R1 SUBI R1 R1 #8 BNEZ R1 Loop This time assume Multiply takes 4 clocks Assume 1st load takes 8 clocks, 2nd load takes 1 clock Clocks for SUBI, BNEZ Show 2 iterations
2 ITER Instruction j k IssueCompResult Busy Addr Fu 1 LD F0 0 R1 Load1 No 1 MULTD F4 F0 F2 Load2 No 1 SD F4 0 R1 Load3 No 2 LD F0 0 R1 Store1 No 2 MULTD F4 F0 F2 Store2 No 2 SD F4 0 R1 Store3 No Mult1 No SUBI R1 R1 #8 Mult2 No BNEZ R1 Loop 0 80 Fu
3 1 LD F0 0 R1 1 Load1 Yes 80 Load2 No Load3 No Store1 No Store2 No Store3 No Mult1 No SUBI R1 R1 #8 Mult2 No BNEZ R1 Loop 1 80 Fu Load1
4 1 LD F0 0 R1 1 Load1 Yes 80 1 MULTD F4 F0 F2 2 Load2 No Load3 No Store1 No Store2 No Store3 No Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8 Mult2 No BNEZ R1 Loop 2 80 Fu Load1 Mult1
5 1 LD F0 0 R1 1 Load1 Yes 80 1 MULTD F4 F0 F2 2 Load2 No 1 SD F4 0 R1 3 Load3 No Store1 Yes 80 Mult1 Store2 No Store3 No Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8 Mult2 No BNEZ R1 Loop 3 80 Fu Load1 Mult1
6 1 LD F0 0 R1 1 Load1 Yes 80 1 MULTD F4 F0 F2 2 Load2 No 1 SD F4 0 R1 3 Load3 No Store1 Yes 80 Mult1 Store2 No Store3 No Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8 Mult2 No BNEZ R1 Loop 4 80 Fu Load1 Mult1
7 1 LD F0 0 R1 1 Load1 Yes 80 1 MULTD F4 F0 F2 2 Load2 No 1 SD F4 0 R1 3 Load3 No Store1 Yes 80 Mult1 Store2 No Store3 No Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8 Mult2 No BNEZ R1 Loop 5 72 Fu Load1 Mult1
8 1 LD F0 0 R1 1 Load1 Yes 80 1 MULTD F4 F0 F2 2 Load2 Yes 72 1 SD F4 0 R1 3 Load3 No 2 LD F0 0 R1 6 Store1 Yes 80 Mult1 Store2 No Store3 No Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8 Mult2 No BNEZ R1 Loop 6 72 Fu Load2 Mult1
9 1 LD F0 0 R1 1 Load1 Yes 80 1 MULTD F4 F0 F2 2 Load2 Yes 72 1 SD F4 0 R1 3 Load3 No 2 LD F0 0 R1 6 Store1 Yes 80 Mult1 2 MULTD F4 F0 F2 7 Store2 No Store3 No Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8 Mult2 Yes Multd R(F2) Load2 BNEZ R1 Loop 7 72 Fu Load2 Mult2
10 1 LD F0 0 R1 1 Load1 Yes 80 1 MULTD F4 F0 F2 2 Load2 Yes 72 1 SD F4 0 R1 3 Load3 No 2 LD F0 0 R1 6 Store1 Yes 80 Mult1 2 MULTD F4 F0 F2 7 Store2 Yes 72 Mult2 2 SD F4 0 R1 8 Store3 No Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8 Mult2 Yes Multd R(F2) Load2 BNEZ R1 Loop 8 72 Fu Load2 Mult2
11 1 LD F0 0 R1 1 9 Load1 Yes 80 1 MULTD F4 F0 F2 2 Load2 Yes 72 1 SD F4 0 R1 3 Load3 No 2 LD F0 0 R1 6 Store1 Yes 80 Mult1 2 MULTD F4 F0 F2 7 Store2 Yes 72 Mult2 2 SD F4 0 R1 8 Store3 No Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8 Mult2 Yes Multd R(F2) Load2 BNEZ R1 Loop 9 72 Fu Load2 Mult2
12 1 LD F0 0 R Load1 No 1 MULTD F4 F0 F2 2 Load2 Yes 72 1 SD F4 0 R1 3 Load3 No 2 LD F0 0 R Store1 Yes 80 Mult1 2 MULTD F4 F0 F2 7 Store2 Yes 72 Mult2 2 SD F4 0 R1 8 Store3 No 4 Mult1 Yes Multd M[80] R(F2) SUBI R1 R1 #8 Mult2 Yes Multd R(F2) Load2 BNEZ R1 Loop Fu Load2 Mult2
13 1 LD F0 0 R Load1 No 1 MULTD F4 F0 F2 2 Load2 No 1 SD F4 0 R1 3 Load3 Yes 64 2 LD F0 0 R Store1 Yes 80 Mult1 2 MULTD F4 F0 F2 7 Store2 Yes 72 Mult2 2 SD F4 0 R1 8 Store3 No 3 Mult1 Yes Multd M[80] R(F2) SUBI R1 R1 #8 4 Mult2 Yes Multd M[72] R(F2) BNEZ R1 Loop Fu Load3 Mult2
14 1 LD F0 0 R Load1 No 1 MULTD F4 F0 F2 2 Load2 No 1 SD F4 0 R1 3 Load3 Yes 64 2 LD F0 0 R Store1 Yes 80 Mult1 2 MULTD F4 F0 F2 7 Store2 Yes 72 Mult2 2 SD F4 0 R1 8 Store3 No 2 Mult1 Yes Multd M[80] R(F2) SUBI R1 R1 #8 3 Mult2 Yes Multd M[72] R(F2) BNEZ R1 Loop Fu Load3 Mult2
15 1 LD F0 0 R Load1 No 1 MULTD F4 F0 F2 2 Load2 No 1 SD F4 0 R1 3 Load3 Yes 64 2 LD F0 0 R Store1 Yes 80 Mult1 2 MULTD F4 F0 F2 7 Store2 Yes 72 Mult2 2 SD F4 0 R1 8 Store3 No 1 Mult1 Yes Multd M[80] R(F2) SUBI R1 R1 #8 2 Mult2 Yes Multd M[72] R(F2) BNEZ R1 Loop Fu Load3 Mult2
16 1 LD F0 0 R Load1 No 1 MULTD F4 F0 F Load2 No 1 SD F4 0 R1 3 Load3 Yes 64 2 LD F0 0 R Store1 Yes 80 Mult1 2 MULTD F4 F0 F2 7 Store2 Yes 72 Mult2 2 SD F4 0 R1 8 Store3 No 0 Mult1 Yes Multd M[80] R(F2) SUBI R1 R1 #8 1 Mult2 Yes Multd M[72] R(F2) BNEZ R1 Loop Fu Load3 Mult2
17 1 LD F0 0 R Load1 No 1 MULTD F4 F0 F Load2 No 1 SD F4 0 R1 3 Load3 Yes 64 2 LD F0 0 R Store1 Yes 80 [80]*R2 2 MULTD F4 F0 F Store2 Yes 72 Mult2 2 SD F4 0 R1 8 Store3 No Mult1 No SUBI R1 R1 #8 0 Mult2 Yes Multd M[72] R(F2) BNEZ R1 Loop Fu Load3 Mult2
18 1 LD F0 0 R Load1 No 1 MULTD F4 F0 F Load2 No 1 SD F4 0 R1 3 Load3 Yes 64 2 LD F0 0 R Store1 Yes 80 [80]*R2 2 MULTD F4 F0 F Store2 Yes 72 [72]*R2 2 SD F4 0 R1 8 Store3 No 4 Mult1 Yes Multd R(F2) Load3 SUBI R1 R1 #8 Mult2 No BNEZ R1 Loop Fu Load3 Mult1
19 1 LD F0 0 R Load1 No 1 MULTD F4 F0 F Load2 No 1 SD F4 0 R1 3 Load3 Yes 64 2 LD F0 0 R Store1 Yes 80 [80]*R2 2 MULTD F4 F0 F Store2 Yes 72 [72]*R2 2 SD F4 0 R1 8 Store3 Yes 64 Mult1 Mult1 Yes Multd R(F2) Load3 SUBI R1 R1 #8 Mult2 No BNEZ R1 Loop Fu Load3 Mult1
20 1 LD F0 0 R Load1 No 1 MULTD F4 F0 F Load2 No 1 SD F4 0 R Load3 Yes 64 2 LD F0 0 R Store1 Yes 80 [80]*R2 2 MULTD F4 F0 F Store2 Yes 72 [72]*R2 2 SD F4 0 R1 8 Store3 Yes 64 Mult1 Mult1 Yes Multd R(F2) Load3 SUBI R1 R1 #8 Mult2 No BNEZ R1 Loop Fu Load3 Mult1
21 1 LD F0 0 R Load1 No 1 MULTD F4 F0 F Load2 No 1 SD F4 0 R Load3 Yes 64 2 LD F0 0 R Store1 No 2 MULTD F4 F0 F Store2 Yes 72 [72]*R2 2 SD F4 0 R Store3 Yes 64 Mult1 Mult1 Yes Multd R(F2) Load3 SUBI R1 R1 #8 Mult2 No BNEZ R1 Loop Fu Load3 Mult1
22 1 LD F0 0 R Load1 Yes 56 1 MULTD F4 F0 F Load2 No 1 SD F4 0 R Load3 Yes 64 2 LD F0 0 R Store1 No 2 MULTD F4 F0 F Store2 No 2 SD F4 0 R Store3 Yes 64 Mult1 Mult1 Yes Multd R(F2) Load3 SUBI R1 R1 #8 Mult2 No BNEZ R1 Loop Fu Load1 Mult1
23 Review: Tomasulo Summary Registers not the bottleneck Avoids the WAR, WAW hazards of Scoreboard Not limited to basic blocks (provided branch prediction) Allows loop unrolling in HW Lasting Contributions Dynamic scheduling Register renaming Load/store disambiguation
24 Dynamic Branch Prediction Performance = ƒ(accuracy, cost of misprediction) Branch History Table (BHT) is simplest Lower bits of PC address index table of 1-bit values Says whether or not branch taken last time Problem: in a loop, 1-bit BHT will cause two mispredictions: Previous loop finishes, sets to not taken Next loop is taken (1 mispredict) Last iteration of this loop is not taken (1 mispredict)
25 Dynamic Branch Prediction Solution: 2-bit scheme where change prediction only if get misprediction twice:
26 BHT Accuracy Mispredict because either: Wrong guess for that branch Got branch history of wrong branch when index the table Based on recent behavior of a single branch to predict 4096 entry table programs vary from 1% misprediction (nasa7, tomcatv) to 18% (eqntott), with spice at 9% and gcc at 12% 4096 about as good as infinite table, but 4096 is a lot of HW Recent behavior of this branch not enough (series of if stmt s)
27 Correlating Branch Predictors Idea: taken/not taken of recently executed branches is related to the behaviors of other branches (as well as its own history) Example Bnez R1, L1 ; b1 Dadd R1, R0, #1 L1: Dsub R3, R1, #1 L2: Bnez R3, L2 ;b2. Assume: R1 = 2,0,2,0,. 1-bit predictor initialized to untaken what happens?
28 Example Bnez R1, L1 ; b1 Dadd R1, R0, #1 L1: Dsub R3, R1, #1 Bnez R3, L2 ;b2. L2: Init R1 P b1 A b1 N b1 P b2 A b2 N b2 2 NT T T NT T T 0 T NT NT T NT NT 2 NT T T NT T T
29 Correlating Branch Predictors (m,n) predictor Using the behaviors of the previous m branches to predict current branch Total n bit to predict a single branch Example: (1,1) predictor Using the behaviors of the previous branch (two possibilities) Using 1-bit to predict each branch
30 NT T Example Bnez R1, L1 ; b1 Dadd R1, R0, #1 L1: Dsub R3, R1, #1 Bnez R3, L2 ;b2 L2:. d P b1 A b1 N b1 P b2 A b2 N b2 2 NT/NT T T/NT NT/NT T NT/T 0 T/NT NT T/NT NT/T NT NT/T 2 T/NT T T/NT NT/T T NT/T Prediction if the last branch of the program is
31 Correlating Branches Idea: taken/not taken of recently executed branches is related to behavior of next branch (as well as the history of that branch behavior) Then behavior of recent branches selects between, say, four predictions of next branch, updating just that prediction Ex: If B1 not taken, then B2 not taken
32 Accuracy of Different Schemes Frequency of Mispredictions 18% Frequency of Mispredictions 16% 14% 12% 10% 8% 6% 4% 2% 0% 1% 0% 1% 5% 6% 6% 11% 4% 6% 5% nasa7 matrix300 tomcatv doducd spice fpppp gcc 4096 Entries 2-bit BHT Unlimited Entries 2-bit BHT 1024 Entries (2,2) BHT espresso eqntott li 4,096 entries: 2-bits per entry Unlimited entries: 2-bits/entry 1,024 entries (2,2)
33 Branch Prediction Buffer Size For a (m,n) predictor size = 2 m x n x #_of_entries For 8K buffer, how many entries for (2,2) predictors? 2 2 x 2 x N = 8K therefore N = 1K
34 Need Same Time as Prediction Branch Target Buffer (BTB): Address of branch index to get prediction AND branch address (if taken) Note: must check for branch match now, since can t use wrong branch address Branch Prediction: Taken or not Taken Return instruction addresses predicted with stack
35 Branch-Target Buffers
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