CISC 662 Graduate Computer Architecture Lecture 13 - Limits of ILP

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1 CISC 662 Graduate Computer Architecture Lecture 13 - Limits of ILP Michela Taufer Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture, 4th edition ---- Additional teaching material from: Jelena Mirkovic (U Del) and John Kubiatowicz (UC Berkeley) Limits of ILP 2 Page 1

2 Limits to ILP Conflicting studies of amount Benchmarks (vectorized Fortran FP vs. integer C programs) Hardware sophistication Compiler sophistication How much ILP is available using existing mechanisms with increasing HW budgets? Do we need to invent new HW/SW mechanisms to keep on processor performance curve? Intel MMX, SSE (Streaming SIMD Extensions): 64 bit ints Intel SSE2: 128 bit, including 2 64-bit Fl. Pt. per clock Motorola AltaVec: 128 bit ints and FPs Supersparc Multimedia ops, etc. 3 Overcoming Limits Advances in compiler technology + significantly new and different hardware techniques may be able to overcome limitations assumed in studies However, unlikely such advances when coupled with realistic hardware will overcome these limits in near future 4 Page 2

3 Limits to ILP Initial HW Model here; MIPS compilers. Assumptions for ideal/perfect machine to start: 1. Register renaming infinite virtual registers => all register WAW & WAR hazards are avoided 2. Branch prediction perfect; no mispredictions 3. Jump prediction all jumps perfectly predicted (returns, case statements) 2 & 3 no control dependencies; perfect speculation & an unbounded buffer of instructions available 4. Memory-address alias analysis addresses known & a load can be moved before a store provided addresses not equal; 1&4 eliminates all but RAW Also: perfect caches; 1 cycle latency for all instructions (FP *,/); unlimited instructions issued/clock cycle; 5 Limits to ILP HW Model comparison Instructions Issued per clock Instruction Window Size Renaming Registers Model IBM Power 5 Infinite 4 Infinite 200 Infinite 48 integer + 40 Fl. Pt. Branch Prediction Perfect 2% to 6% misprediction (Tournament Branch Predictor) Cache Perfect 64KI, 32KD, 1.2MB L2, 36 MB L3 Memory Alias Analysis Perfect?? 6 Page 3

4 Upper Limit to ILP: Ideal Machine (Figure 3.1) Instructions Per Clock Instruction Issues per cycle Integer: FP: gcc e s p r e s s o li fpppp doducd tomcatv Programs 7 What the Perfect Processor must do Look arbitrary far ahead to find a set of instructions to issue Predict all branches perfectly Rename all register Avoid WAR and WAW Determine whether there are any data dependences among the instructions in the issue packet Rename accordingly Determine if any memory dependences exists among the issue packet Handel accordingly Provide enough replicated functional units Allow all the reasy instructions to issue 8 Page 4

5 Window Size Given n issuing instructions: Assume all instructions are register-register Assume total number of registers is unbounded The number of comparisons is: 2n n = n 2 - n Cost of comparison limits the number of instructions that can considered for issue at once The set of instructions that is examined for simultaneous execution is called windows The total window size is limited by: Required storage Comparisons Limited issue rate N-Factor Analysis A window larger than the issue rate is worthwhile if there are dependences or cache misses in the instruction misses. The maximum number of instructions that may issue, begin execution, or commit in the same cycle is usually much smaller than the window size N-Factor Analysis: Limit the size of window Keep all the other parameters the same (ideal) What is the effect on the the amount of parallelism? 10 Page 5

6 Limits to ILP HW Model comparison New Model Model Power 5 Instructions Issued per clock Instruction Window Size Renaming Registers Branch Prediction Infinite Infinite 4 Infinite, 2K, 512, 128, 32 Infinite 200 Infinite Infinite 48 integer + 40 Fl. Pt. Perfect Perfect 2% to 6% misprediction (Tournament Branch Predictor) Cache Perfect Perfect 64KI, 32KD, 1.2MB L2, 36 MB L3 Memory Alias Perfect Perfect?? 11 More Realistic HW: Window Impact Figure 3.2 Change from Infinite window 2048, 512, 128, 32 FP: IPC Instructions Per Clock Integer: gcc espresso li fpppp doduc tomcatv Infinite Page 6

7 Limits to ILP HW Model comparison New Model Model Power 5 Instructions Issued per clock Instruction Window Size Renaming Registers Branch Prediction 64 Infinite Infinite 200 Infinite Infinite 48 integer + 40 Fl. Pt. Perfect vs. 8K Tournament vs bit vs. profile vs. none Perfect 2% to 6% misprediction (Tournament Branch Predictor) Cache Perfect Perfect 64KI, 32KD, 1.2MB L2, 36 MB L3 Memory Alias Perfect Perfect?? 13 Five Levels of Branch Prediction Perfect: all branches and jumps are perfectly predicted at the start of execution Tournament predictor: use multiple predictors, usually one based on global information and one based on local information, and combining them with a selector that chooses the best predictor for each branch Standard 2-bit predictor with with bit entries Profile-based: static predictor uses the profile history of the program and predict the branches is always taking or not taking based on profile None: no branch prediction is used 14 Page 7

8 IPC More Realistic HW: Branch Impact Figure Change from Infinite window to examine to 2048 and maximum issue of 64 instructions 41 per clock cycle 35 Integer: FP: gcc espresso li fpppp doducd tomcatv P r o g r a m Perfect Perfect Selective predictor Standard 2-bit Static None Tournament BHT (512) Profile No prediction 15 Misprediction Rates Misprediction Rate 35% 30% 25% 20% 15% 10% 5% 0% 30% 23% 18% 18% 16% 14% 14% 12% 12% 6% 5% 4% 3% 1% 1% 2% 2% 0% tomcatv doduc fpppp li espresso gcc Profile-based 2-bit counter Tournament 16 Page 8

9 Limits to ILP HW Model comparison Instructions Issued per clock Instruction Window Size Renaming Registers Branch Prediction New Model Model Power 5 64 Infinite Infinite 200 Infinite v. 256, 128, 64, 32, none Infinite 48 integer + 40 Fl. Pt. 8K 2-bit Perfect Tournament Branch Predictor Cache Perfect Perfect 64KI, 32KD, 1.2MB L2, 36 MB L3 Memory Alias Perfect Perfect Perfect 17 IPC More Realistic HW: Renaming Register Impact (N int + N fp) Figure Change 2048 instr window, 64 instr issue, 8K 2 level Prediction Integer: FP: gcc espresso li fpppp doducd tomcatv P r o g r a m Infinite None Infinite None 18 Page

Limits to ILP HW Model comparison New Model Model Power 5 Instructions Issued per clock Instruction Window Size Renaming Registers 64 Infinite 4 2048 Infinite 200 256 Int + 256 FP Infinite 48 integer

10 Limits to ILP HW Model comparison New Model Model Power 5 Instructions Issued per clock Instruction Window Size Renaming Registers 64 Infinite Infinite Int FP Infinite 48 integer + 40 Fl. Pt. Branch 8K 2-bit Perfect Tournament Prediction Cache Perfect Perfect 64KI, 32KD, 1.2MB L2, 36 MB L3 Memory Alias Perfect v. Stack v. Inspect v. none Perfect Perfect 1 MIPS memory allocation for program and data Text segment: Holds programs Instructions Data segment: Static data Dynamic data Stack Segment Static Data: Size known to the compiler Lifetime is the program s entire execution e.g., global variables in C Dynamic Data: e.g., in C data allocated by malloc() 20 Page 10

11 Three Alias Analysis Models Global/stack perfect: Perfect predictions for global and stack references; assume all heap references conflict Inspection: Examine the accesses to see if they can interfere at compile time 0(R0) and 16(R0) do not interfere Addresses that point to different areas (e.g., global and stack areas) never to alias None: All memory references are considered to conflict 21 IPC More Realistic HW: Memory Address Alias Impact Figure 3.6 Instruction issues per cycle Change 2048 instr window, 64 instr issue, 8K 2 level Prediction, 256 renaming registers Integer: FP: 4-45 (Fortran, no heap) gcc espresso li fpppp doducd tomcatv P r o g r a m Perfect Global/stack Perfect Inspection None Perfect Global/Stack perf; heap conflicts Inspec. Assem. None 22 Page 11

12 Limits to ILP HW Model comparison Instructions Issued per clock Instruction Window Size Renaming Registers New Model Model Power 5 64 (no restrictions) Infinite vs. 256, 128, 64, 32 Infinite 4 Infinite Int + 64 FP Infinite 48 integer + 40 Fl. Pt. Branch 1K 2-bit Perfect Tournament Prediction Cache Perfect Perfect 64KI, 32KD, 1.2MB L2, 36 MB L3 Memory Alias HW disambiguation Perfect Perfect 23 IPC Instruction issues per cycle Realistic HW: Window Impact (Figure 3.7) Perfect disambiguation (HW), 1K Selective Prediction, 16 entry return, 64 registers, issue as many as window Integer: FP: gcc expresso li fpppp doducd tomcatv P r o g r a m Infinite Infinite Page 12

13 How to Exceed ILP Limits of this study? These are not laws of physics; just practical limits for today, and perhaps overcome via research Compiler and ISA advances could change results WAR and WAW hazards through memory: eliminated WAW and WAR hazards through register renaming, but not in memory usage Can get conflicts via allocation of stack frames as a called procedure reuses the memory addresses of a previous frame on the stack 25 HW v. SW to increase ILP Memory disambiguation: HW best Speculation: HW best when dynamic branch prediction better than compile time prediction Exceptions easier for HW HW doesn t need bookkeeping code or compensation code Very complicated to get right Scheduling: SW can look ahead to schedule better HW = compiler independence: does not require new compiler / recompilation to run well on different implementations of an architecture 26 Page 13

14 Performance beyond single thread ILP There can be much higher natural parallelism in some applications (e.g., Database or Scientific codes) Explicit Thread Level Parallelism or Data Level Parallelism Thread: process with own instructions and data Thread may be a process part of a parallel program of multiple processes, or it may be an independent program Each thread has all the state (instructions, data, PC, register state, and so on) necessary to allow it to execute Data Level Parallelism: Perform identical operations on data, and lots of data 27 Thread Level Parallelism (TLP) ILP exploits implicit parallel operations within a loop or straight-line code segment TLP explicitly represented by the use of multiple threads of execution that are inherently parallel Goal: Use multiple instruction streams to improve 1. Throughput of computers that run many programs 2. Execution time of multi-threaded programs TLP could be more cost-effective to exploit than ILP 28 Page 14

15 Another Approach: Multithreaded Execution Multithreading: multiple threads to share the functional units of 1 processor via overlapping processor must duplicate independent state of each thread e.g., a separate copy of register file, a separate PC, and for running independent programs, a separate page table memory shared through the virtual memory mechanisms, which already support multiple processes HW for fast thread switch; much faster than full process switch 100s to 1000s of clocks When switch? Alternate instruction per thread (fine grain) When a thread is stalled, perhaps for a cache miss, another thread can be executed (coarse grain) 2 Fine-Grained Multithreading Switches between threads on each instruction, causing the execution of multiples threads to be interleaved Usually done in a round-robin fashion, skipping any stalled threads CPU must be able to switch threads every clock Advantage is it can hide both short and long stalls, since instructions from other threads executed when one thread stalls Disadvantage is it slows down execution of individual threads, since a thread ready to execute without stalls will be delayed by instructions from other threads Used on Sun s Niagara (will see later) 30 Page 15

Course-Grained Multithreading Switches threads only on costly stalls, such as L2 cache misses Advantages Relieves need to have very fast thread-switching Doesn t slow down thread, since instructions

instructions from 1 thread, when a stall occurs, the pipeline must be emptied or frozen New thread must fill pipeline before instructions can complete Because of this start-up overhead,

16 Course-Grained Multithreading Switches threads only on costly stalls, such as L2 cache misses Advantages Relieves need to have very fast thread-switching Doesn t slow down thread, since instructions from other threads issued only when the thread encounters a costly stall Disadvantage is hard to overcome throughput losses from shorter stalls, due to pipeline start-up costs Since CPU issues instructions from 1 thread, when a stall occurs, the pipeline must be emptied or frozen New thread must fill pipeline before instructions can complete Because of this start-up overhead, coarse-grained multithreading is better for reducing penalty of high cost stalls, where pipeline refill << stall time Used in IBM AS/ For most apps: most execution units lie idle For an 8-way superscalar. From: Tullsen, Eggers, and Levy, Simultaneous Multithreading: Maximizing On-chip Parallelism, ISCA Page 16

17 Do both ILP and TLP? TLP and ILP exploit two different kinds of parallel structure in a program Could a processor oriented at ILP to exploit TLP? functional units are often idle in data path designed for ILP because of either stalls or dependences in the code Could the TLP be used as a source of independent instructions that might keep the processor busy during stalls? Could TLP be used to employ the functional units that would otherwise lie idle when insufficient ILP exists? 33 Simultaneous Multi-threading... One thread, 8 units Two threads, 8 units Cycle M M FX FX FP FPBRCC 1 1 Cycle M M FX FX FP FPBRCC M = Load/Store, FX = Fixed Point, FP = Floating Point, BR = Branch, CC = Condition Codes 34 Page 17

18 Simultaneous Multithreading (SMT) Simultaneous multithreading (SMT): insight that dynamically scheduled processor already has many HW mechanisms to support multithreading Large set of virtual registers that can be used to hold the register sets of independent threads Register renaming provides unique register identifiers, so instructions from multiple threads can be mixed in datapath without confusing sources and destinations across threads Out-of-order completion allows the threads to execute out of order, and get better utilization of the HW Just adding a per thread renaming table and keeping separate PCs Independent commitment can be supported by logically keeping a separate reorder buffer for each thread Source: Micrprocessor Report, December 6, 1 Compaq Chooses SMT for Alpha 35 Time (processor cycle) Multithreaded Categories Superscalar Fine-Grained Coarse-Grained Multiprocessing Simultaneous Multithreading Thread 1 Thread 2 Thread 3 Thread 4 Thread 5 Idle slot 36 Page 18

19 Design Challenges in SMT Since SMT makes sense only with fine-grained implementation, impact of fine-grained scheduling on single thread performance? A preferred thread approach sacrifices neither throughput nor single-thread performance? Unfortunately, with a preferred thread, the processor is likely to sacrifice some throughput, when preferred thread stalls Larger register file needed to hold multiple contexts Clock cycle time, especially in: Instruction issue - more candidate instructions need to be considered Instruction completion - choosing which instructions to commit may be challenging Ensuring that cache and TLB conflicts generated by SMT do not degrade performance 37 Page 1

CMSC 411 Computer Systems Architecture Lecture 13 Instruction Level Parallelism 6 (Limits to ILP & Threading)

CMSC 411 Computer Systems Architecture Lecture 13 Instruction Level Parallelism 6 (Limits to ILP & Threading) Limits to ILP Conflicting studies of amount of ILP Benchmarks» vectorized Fortran FP vs. integer