COMP 7860 Embedded Real- Time Systems: Threads

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1 COMP 7860 Embedded Real- Time Systems: Threads Jacky Baltes Autonomous Agents Lab University of Manitoba Winnipeg, Canada R3T 2N2 WWW:

2 RTOS Design As seen in the example of the line tracking robot, it is almost always better to use seperate threads in robotics, because robotics applications must react to asynchronous events makes the code more manageable, easier to maintain

3 RTOS Design Design a small RTOS which can be used for robotics applications Requirements Manage threads Thread synchronization Memory Constraints Small memory foot-print (1KB static RAM) Simple to implement

4 RTOS Multi-tasking OS simulates parallel execution on a single CPU by switching between various threads Time-multiplexing Cooperative Threads yield, i.e., return control back to the OS A badly programmed thread will bring the OS down Pre-emptive A timer interrupt (system tick) interrupts a running thread, saves the thread state and starts the next thread

5 RTOS Requirements Manage threads/processes Create threads/processes Statically fixed number of threads Dynamically variable nr. of threads Stop/kill dynamic threads Adds a lot of complexity since the thread needs to release all resources, otherwise may lead to deadlock Deadlock occurs if no process can proceed because it is waiting for a resource owned by a different thread. Dining philosophers problem

6 RTOS Requirements Thread priorities Often have threads that are more/less important than others Number of priority levels (4) Static/dynamic priorities

7 RTOS Requirements Priority inversion is a phenomenon which can arise in a concurrent programming environment where a high priority task (H) is blocked by a low priority task (L), e.g. because L has locked some resource needed by H, and L then has to wait for a medium priority task (M). The net result is that H ends up waiting for M instead of the other way round - the priorities become inverted. This can be a problem if, for example, M takes a long time, causing H to miss a deadline. A possible cure is to have tasks inherit the maximum priority of any task that is waiting for them. In that case L temporarily becomes high priority until H can proceed, thus preventing M from running in place of H.

8 RTOS Requirements Synchronization Counting semaphore primitives P (wait), V (increment,signal) P try-to-decrement must be atomic Disable context switching Disable interrupts Others Must work with avr-gcc and avr-libc

9 RTOS Considerations Use a timer to generate a 50Hz interrupt to drive the thread scheduler Idle thread Stack management Reduce memory usage Register saves Stack memory

10 AVR-GCC Conventions Data types: char is 8 bits, int is 16 bits, long is 32 bits, long long is 64 bits, float and double are 32 bits (this is the only supported floating point format)

11 AVR-GCC Conventions Data types pointers are 16 bits function pointers are word addresses, to allow addressing the whole 128K program memory space on the ATmega devices with > 64 KB of flash ROM). -mint8 option (see Options for the C compiler avr-gcc ) to make int 8 bits, not supported

12 AVR-GCC Conventions Call-saved registers (r2-r17, r28-r29): May be allocated by gcc for local data. Calling C subroutines leaves them unchanged. Assembler subroutines are responsible for saving and restoring these registers, if changed. r29:r28 (Y pointer) is used as a frame pointer (points to local data on stack ) if necessary. Call-used registers (r18-r27, r30-r31): May be allocated by gcc for local data. You may use them freely in assembler subroutines. Calling C subroutines can clobber any of them - the caller is responsible for saving and restoring.

13 AVR-GCC Conventions Fixed registers (r0, r1): Never allocated by gcc for local data, but often used for fixed purposes: r0 - temporary register, can be clobbered by any C code (except interrupt handlers which save it), may be used to remember something for a while within one piece of assembler code r1 - assumed to be always zero in any C code, may be used to remember something for a while within one piece of assembler code, but must then be cleared after use (clr r1). This includes any use of the [f]mul[s[u]] instructions, which return their result in r1:r0. Interrupt handlers save and clear r1 on entry, and restore r1 on exit (in case it was non-zero).

14 AVR-GCC Conventions Function call conventions: Arguments - allocated left to right, r25 to r8. All arguments are aligned to start in even-numbered registers (odd-sized arguments, including char, have one free register above them). This allows making better use of the movw instruction on the enhanced core. If too many, those that don't fit are passed on the stack.

15 AVR-GCC Conventions Return values: 8-bit in r24 (not r25!), 16-bit in r25:r24, up to 32 bits in r22- r25, up to 64 bits in r18-r25. 8-bit return values are zero/sign-extended to 16 bits by the caller (unsigned char is more efficient than signed char - just clr r25). Arguments to functions with variable argument lists (printf etc.) are all passed on stack, and char is extended to int.

16 AVR-GCC Inline Assembler asm introduces inline assembler Assembly code is single string constant Use line continuation to format %0,%1 correspond to pseudo registers, which are mapped by the compiler Correspond to input, output, clobber registers List of output operands (e.g., result) List of input operands (e.g., asm("\n\ mov %0, %1 \n\ lsr %0\n\ " : "=r" (result) : "r" (value) );

17 AVR-GCC Inline Assembler General form asm(code : output operand list : input operand list : clobber list); Input registers that provide values to your code Output registers that specify result of your expression Clobber registers that are changed because of your code, outputs are always clobbered

18 AVR-GCC Inline Assembler asm volatile instructs the compiler not to do any optimizations Must have at least two colons clobber list may be left off Special registers SREG (PORTE) - Port SP_H, SP_L - Stack pointer tmp_reg - R0 tmp variable, no need to restore zero_reg - R1 always 0 asm volatile("cli"::);

19 AVR-GCC Inline Assembler Register constraints (Depends on assembly language used) a simple upper register R16 to R23 b base pointer pair, y,z d upper register R16 to R31 e pointer register pairs x,y,z G floating point constant I,J 6 bit positive/negative constant t temporary register K/L/N/O/P integer constants 0/2/-1/8,16,24/1 w special upper reg l lower register x/y/z pointer x,y,z M 8 bit constant q Stack pointer register SPH:SPL asm("in %0, %1" : "=r" (value) : "I" (_SFR_IO_ADDR(PORTD)) );

20 AVR-GCC Inline Assembly Read/write register values Can specify a digit to refer to previous register asm volatile("swap %0" : "=r" (value) : "0" (value)); Read only registers asm volatile("in %0,%1\n\t" "out %1, %2\n\t" : "=&r" (input) : "I" (_SFR_IO_ADDR(port)), "r" (output)); Problem occurs if

21 AVR-GCC Inline Assembly 16 bit swap %A0 upper 16 bit %B0 lower 16 bit 32 bit swap %A0..%D0 %A1..%D1 asm volatile("mov tmp_reg, %A0" "\n\" "mov %A0, %B0" "\n\" "mov %B0, tmp_reg " "\n\" : "=r" (value) : "0" (value) ); asm volatile("\t mov tmp_reg, %A0\n\" "\t mov %A0, %D0\n\" "\t mov %D0, tmp_reg \n\" "\t mov tmp_reg, %B0\n\" "\t mov %B0, %C0\n\" "\t mov %C0, tmp_reg \n\" : "=r" (value) : "0" (value) );

22 AVR-GCC Inline Assembly Register pairs X,Y,Z are specified by the e constraint Z %A0=R30, %B0=R31 How to create the original register pair ld r24,z ld r24, %a0 ; Note lower case a

23 AVR-GCC Inline Assembly Clobbers specify registers that are modified Atomic increment No input operand Synchronization store value in memory Better to use tmp_reg Specify R24 as clobbered asm volatile( "cli" "\n\t" "ld r24, %a0" "\n\t" "inc r24" "\n\t" "st %a0, r24" "\n\t" "sei" "\n\t" : : "e" (ptr) : "r24" );

24 AVR-GCC Inline Assembly Memory clobbers *ptr is also changed special clobber memory will reload everything Better specify ptr as volatile

25 AVR-GCC Inline Assembly C Stub functions to hold temporary variables etc. L_dl1%= creates label cnt used as tmp reg. Can also unix label syntax 1:/2: brne 2b void delay(uint8_t ms) { uint16_t cnt; asm volatile ( "\n" "L_dl1%=:" "\n\t" "mov %A0, %A2" "\n\t" "mov %B0, %B2" "\n" "L_dl2%=:" "\n\t" "sbiw %A0, 1" "\n\t" "brne L_dl2%=" "\n\t" "dec %1" "\n\t" "brne L_dl1%=" "\n\t" : "=&w" (cnt) : "r" (ms), "r" (delay_count) ); }

26 AVR-GCC Inline Assembly Names used by the assembler can be defined by the C program unsigned long value asm("clock") = ; C uses value, assembler uses clock Specify register register unsigned char counter asm("r3"); Functions extern long Calc(void) asm ("CALCULATE");

27 PROG_MEM How to put a constant into ROM #include <avr/pgmspace.h> PGM_P array[2] PROGMEM = { "Foo", "Bar" }; int main (void) { char buf[32]; strcpy_p (buf, array[1]); return 0; }

28 PROG_MEM How to put a constant into ROM #include <avr/pgmspace.h> PGM_P array[2] PROGMEM = { "Foo", "Bar" }; int main (void) { char buf[32]; strcpy_p (buf, array[1]); return 0; } Wrong: array is stored in ROM, but strings are still stored in.data section (RAM)

29 PROG_MEM How to put a constant into ROM #include <avr/pgmspace.h> const char foo[] PROGMEM = "Foo"; const char bar[] PROGMEM = "Bar"; PGM_P array[2] PROGMEM = { foo, bar }; int main (void) { char buf[32]; PGM_P p; int i; memcpy_p(&p, &array[i], sizeof(pgm_p)); strcpy_p(buf, p); return 0; }

30 Context Switch Save all registers Find next task Setup thread context Return from interrupt

31 Memory Layout Area to save the registers

32 AVR Interrupt Processing When an interrupt occurs, the following events will take place PC is pushed onto stack (2 Bytes) ISR is responsible for saving the SREG register AtMega128 (>64kB of ROM) RAMPZ register must be saved

33 AVR Interrupt Processing Sample interrupt handler routine How to switch to the new task push zero_reg ; R1 push tmp_reg ; R0 in tmp_reg,_sfr_io_addr(sreg) ; Software has to save SREG/PSW push tmp_reg push r18 ; Save remaining volatile GP registers push r19...

34 AVR Interrupt Processing To restore context setup stack pointer to point to common stack pop registers, SREG, RAMPZ RETI (Enables I Bit in SREG)

Context Switching & Task Scheduling

ECE3411 Fall 2015 Lab 6b. Context Switching & Task Scheduling Marten van Dijk, Syed Kamran Haider Department of Electrical & Computer Engineering University of Connecticut Email: {vandijk, syed.haider}@engr.uconn.edu