CN310 Microprocessor Systems Design

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1 CN310 Microprocessor Systems Design Instruction Set (AVR) Nawin Somyat Department of Electrical and Computer Engineering Thammasat University

2 Outline Course Contents 1 Introduction 2 Simple Computer 3 Microprocessor Architecture 4 Memory 5 Peripherals 6 Applications Outline 1 Instruction Set Instruction Set Memory Spaces Registers 2 AVR Microntroller Instruction Memory AVR Register File 3 AVR Addressing Modes 4 AVR Instructions CN310 Microprocessor Systems Design 2 / 35

3 Instruction Set Instruction set: a set of operations that can be performed on a processer. machine language (binary) machine dependent opcode + (0 or more) operands common operations: arithmentic and logic e.g. ADD, SUB, AND, OR data movement/transfer e.g. MOV, LD, IN, OUT control flow e.g. JMP, BREQ, CALL, RET special/extra/misc operations e.g. SEI, CLI, NOP, SWAP instruction length fixed e.g. RISC variable e.g. CISC addressing mode - where to get/set operand(s) result - effect of executing an instruction CN310 Microprocessor Systems Design 3 / 35

4 Memory Spaces Memory spaces: code space Flash - main code, sometimes also for table data EEPROM - additional code, secondary condtant data data space RAM - main data operation storage Some instruction may be able to access only in certain area in memory spaces. In Harvard architecture: same memory address may refer to different memory space depending on instruction. operations are mostly performed on registers in register file I/O data are accessed through I/O registers from load/store instructions CN310 Microprocessor Systems Design 4 / 35

5 Registers An instruction usually involves access to some register(s). Common register types: accumulator general purpose, register file program counter stack pointer, base pointer status, condition code, flag index, offset segment Some registers are grouped to form larger registers e.g. 2 x 8-bit registers grouped to give 1 x 16-bit register. CN310 Microprocessor Systems Design 5 / 35

6 AVR Instruction AVR is an 8-bit microcontroller with RISC architecture. 131 instructions (ATMega168) 32 x 8 general purpose registers (R0-R31) most instructions execute 1 instruction in 1 cycle most instructions are 16-bit 5 groups of instructions arithmetic and logic branch data transfer bit and bit-test MCU control CN310 Microprocessor Systems Design 6 / 35

7 AVR Memory Interconnections CN310 Microprocessor Systems Design 7 / 35

8 AVR Memory Map CN310 Microprocessor Systems Design 8 / 35

9 AVR Data Memory Map (ATMega168) CN310 Microprocessor Systems Design 9 / 35

10 AVR Register File R27:R26 forms 16-bit X register. R29:R28 forms 16-bit Y register. R31:R30 forms 16-bit Z register. CN310 Microprocessor Systems Design 10 / 35

11 AVR Program and Addressing Modes 1 Register Direct, 1 register Rd 2 Register Direct, 2 registers Rd and Rr 3 I/O Direct 4 Data Direct 5 Data Indirect 6 Data Indirect with Displacement 7 Data Indirect with Pre-decrement 8 Data Indirect with Post-increment 9 Program Memory Constant Addressing 10 Program Memory Addressing with Post-increment 11 Direct Program Memory Addressing 12 Indirect Program Memory Addressing 13 Relative Program Memory Addressing CN310 Microprocessor Systems Design 11 / 35

12 Instruction Set Nomenclature Registers and Operands Rd: Destination (and source) register in the Register File Rr: Source register in the Register File R: Result after instruction is executed K: Constant data k: Constant address b: Bit in the Register File or I/O Register (3-bit) s: Bit in the Status Register (3-bit) X,Y,Z: Indirect Address Register (X=R27:R26, Y=R29:R28 and Z=R31:R30) A: I/O location address q: Displacement for direct addressing (6-bit) CN310 Microprocessor Systems Design 12 / 35

13 Register Direct, 1 Register (Rd) The operand is in register d (Rd). The result is stored in register d (Rd). Example: 5.1 INC R0 ; R0 = R0 + 1 CLR R1 ; R1 = 0x00 NEG R2 ; R2 = 0x00 - R2 (2's complement) CN310 Microprocessor Systems Design 13 / 35

14 Register Direct, 2 Registers (Rr and Rd) Operands are contained in register r (Rr) and register d (Rd). The result is stored in register d (Rd). Example: 5.2 ADD R0, R1 ; R0 = R0 + R1 AND R2, R3 ; R2 = R2 & R3 MOV R4, R5 ; R4 = R5 CN310 Microprocessor Systems Design 14 / 35

15 I/O Direct Operand address (A) is contained in 6 bits of the instruction word. Register r/d (Rr/Rd) is the source/destination register. Example: 5.3 IN R6, $1E ; R6 = I/O[0x1E] OUT $2A, R7 ; I/O[0x2A] = R7 CN310 Microprocessor Systems Design 15 / 35

16 Data Direct A 16-bit Data Address is contained in the 16 LSbs of a two-word instruction. Rr/Rd specifies the source/destination register. Example: 5.4 LDS R8, $0AAA ; R8 = Data[0x0AAA] STS $01CD, R9 ; Data[0x01CD] = R9 CN310 Microprocessor Systems Design 16 / 35

17 Data Indirect Operand address is the content of the X, Y, or the Z register. Example: 5.5 LD R10, X ; R10 = Data[X] ST Y, R11 ; Data[Y] = R11 CN310 Microprocessor Systems Design 17 / 35

Data Indirect with Displacement Operand address is the result of the Y or Z register content added to the address contained in 6 bits of the instruction word.

18 Data Indirect with Displacement Operand address is the result of the Y or Z register content added to the address contained in 6 bits of the instruction word. Rr/Rd specifies the source/destination register. Example: 5.6 LDD R12, Y+1 ; R12 = Data[Y+1] STD Z+2, R13 ; Data[Z+2] = R13 CN310 Microprocessor Systems Design 18 / 35

19 Data Indirect with Pre-decrement The X, Y, or the Z register is decremented before the operation. Operand address is the decremented content of the X, Y, or the Z register. Example: 5.7 LD R14, -X ; X = X-1, R14 = Data[X] ST -Y, R15 ; Y = Y-1, Data[Y] = R15 CN310 Microprocessor Systems Design 19 / 35

20 Data Indirect with Post-increment The X, Y, or the Z register is incremented after the operation. Operand address is the decremented content of the X, Y, or the Z register. Example: 5.8 LD R16, Y+ ; R16 = Data[X], Y = Y + 1 ST Z+, R17 ; Data[Z] = R17, Z = Z + 1 CN310 Microprocessor Systems Design 20 / 35

21 Program Memory Constant Addressing Constant byte address is specified by the Z register content. The 15 MSbs select word address. For LPM, the LSb selects low byte if cleared (LSb = 0) or high byte if set (LSb = 1). Example: 5.9 LPM ; R0 = Prog[Z] LPM R18, Z ; R18 = Prog[Z] CN310 Microprocessor Systems Design 21 / 35

22 Program Memory Addressing with Post-increment Constant byte address is specified by the Z-register contents. The 15 MSBs select word address. The LSb selects low byte if cleared (LSb = 0) or high byte if set (LSb = 1). Example: 5.10 LPM R19, Z+ ; R19 = Prog[Z], Z = Z + 1 CN310 Microprocessor Systems Design 22 / 35

23 Direct Program Memory Addressing Program execution continues at the address immediate in the instruction word. Example: 5.11 JMP $0ABC ; PC = 0x0ABC CALL sub_name ; PC = 0x???? (value resolved by assembler) CN310 Microprocessor Systems Design 23 / 35

Indirect Program Memory Addressing Program execution continues at address contained by the Z register (i.e. the PC is loaded with the contents of the Z register).

24 Indirect Program Memory Addressing Program execution continues at address contained by the Z register (i.e. the PC is loaded with the contents of the Z register). Example: 5.12 IJMP $0ABC ; PC = Z ICALL ; PC = Z CN310 Microprocessor Systems Design 24 / 35

25 Indirect Program Memory Addressing Program execution continues at address PC + k + 1. The relative address k is from to Example: 5.13 RJMP 8 ; PC = PC RCALL -24 ; PC = PC CN310 Microprocessor Systems Design 25 / 35

26 Arithmetic and Logic Instructions Arithmetic and Logic Data Transfer Addition Subtraction Logical AND, OR, XOR One s/two s complement Set/Clear registers Increment/Decrement Multiplication Branch Unconditional - jump Conditional - branch if cond. Skip Subroutine - call/return Compare Move - reg reg Load/Store - I/O reg Program memory - prog reg Input/Output - I/O reg Push/Pop - stack reg Bit and Bit-test Rotate, Shift, Arithmetic shift Bit Load/Store Bit Set/Clear in register MCU Control BREAK, NOP, SLEEP, WDR CN310 Microprocessor Systems Design 26 / 35

27 The Status Register Most flags are set by hardware after executing an instruction. Some flag is programmable, e.g. the global interrupt enable flag. Flags - Nomenclature : Flag affected by instruction 0 : Flag cleared by instruction 1 : Flag set by instruction - : Flag not affected by instruction CN310 Microprocessor Systems Design 27 / 35

28 Example: Arithmetic ADD - Add without carry Description: Adds two registers without the C Flag and places the result in the destination register Rd. Operation: Rd Rd + Rr Syntax: Operands: Proram Counter: ADD Rd,Rr 0 d 31, 0 r 31 PC PC bit opcode: rd dddd rrrr Status Register (SREG) and Boolean Formula: I T H S V N Z C - - CN310 Microprocessor Systems Design 28 / 35

29 Example: Arithmetic Example: 5.14 add r1,r2 ; Add r2 to r1 (r1=r1+r2) add r28,r28 ; Add r28 to itself (r28=r28+r28) Machine Code: rd dddd rrrr add r1,r rd dddd rrrr add r28,r CN310 Microprocessor Systems Design 29 / 35

30 Example: Branch RJMP - Relative Jump Description: Relative jump to an address within PC - 2K + 1 and PC + 2K (words). Operation: PC PC + k + 1 Syntax: Operands: Proram Counter: RJMP k -2K k 2K PC PC + k bit opcode: 1100 kkkk kkkk kkkk Status Register (SREG) and Boolean Formula: I T H S V N Z C CN310 Microprocessor Systems Design 30 / 35

31 Example: Branch Example: 5.15 cpi r16,0x42 ; Compare r16 to 0x42 brne error ; Branch if r16 <> 0x42 rjmp ok ; Unconditional branch error: add r16,r17 ; Add r17 to r16 inc r16 ok: nop ; Destination for rjmp (do nothing) Assume this code starts from address 0x0000 (from cpi instruction.) label ok is resolved into program address 0x0005. Machine Code: 1100 kkkk kkkk kkkk rjmp ok CN310 Microprocessor Systems Design 31 / 35

32 Example: Data Transfer MOV - Copy Register Description: This instruction makes a copy of one register into another. The source register Rr is left unchanged, while the destination register Rd is loaded with a copy of Rr. Operation: Rd Rr Syntax: Operands: Proram Counter: MOV Rd,Rr 0 d 31, 0 r 31 PC PC bit opcode: rd dddd rrrr Status Register (SREG) and Boolean Formula: I T H S V N Z C CN310 Microprocessor Systems Design 32 / 35

33 Example: Data Transfer Example: 5.16 mov r16,r0 ; Copy r0 to r16 Machine Code: rd dddd rrrr mov r16,r CN310 Microprocessor Systems Design 33 / 35

34 Example: Bit and Bit-test SBI - Set Bit in I/O Register Description: Set Bit in I/O Register Operation: I/O(A,b) 1 Syntax: Operands: Proram Counter: SBI A,b 0 A 31, 0 b 7 PC PC bit opcode: AAAA Abbb Status Register (SREG) and Boolean Formula: I T H S V N Z C CN310 Microprocessor Systems Design 34 / 35

35 Example: Bit and Bit-test Example: 5.17 sbi 0x0b,7 ; Set bit 7 in Port D Note: Port D has I/O address of 0x0B. Machine Code: AAAA Abbb sbi 0x0b, CN310 Microprocessor Systems Design 35 / 35

ก AVR Microcontrollers

ก AVR Microcontrollers. ก ก AVR Microcontrollers Architecture 1 Instruction Execution Timing The Parallel Instruction Fetches and Instruction Executions Single Cycle ALU Operation AVR Microcontrollers