Interrupts and timers

Transcription

1 Applied mechatronics, Lab project Interrupts and timers Sven Gestegård Robertz Department of Computer Science, Lund University 2018

2 Outline 1 Interrupts Interrupt types Execution of an interrupt Maskable interrupts 2 Interrupts on AVR Interrupts in AVR-libc 3 Interrupt sources Timers and PWM 4 Concluding remarks 5 Concurrency, a brief overview

3 Overview Interrupts What is it? How are they programmed? Pitfalls? Specific peripherals in the AVR External interrupts Timer Read the data sheet Interrupts and timers 2/33

4 The interrupt mechanism A low-level mechanism for multitasking Interrupt what you are doing to handle an external signal. (Similar to the phone ringing) Vaguely similar to Java Threads or rather, threads can be implemented using interrupts the interrupt mechanism provides no scheduling, etc. interrupts do not provide separate stacks, etc. interrupts may have priorities (not on AVR) Interrupts Interrupts and timers 3/33

5 Types of interrupts Hardware interrupts externally generated frees CPU from polling Software interrupts generated by a CPU instruction On AVR: writing to a pin change interrupt pin configured as output triggers the interrupt used, for instance, to implement system calls (on machines with memory protection) Interrupts : Interrupt types Interrupts and timers 4/33

6 Execution of an interrupt When an (external) signal (IRQ) occurs, the normal execution of the CPU is interrupted: 1 An IRQ (for an enabled interrupt) occurs 2 The program counter (PC) value is pushed onto the stack 3 The CPU jumps to an interrupt handler (ISR) pointed to from the corresponding interrupt vector PC interrupt_table[irq_idx] 4 The ISR handles the interrupt 5 ISR returns to the interrupted routine reti(); ((Possibly) clear interupt flag, then PC pop()) not all interrupt flags are cleared by hardware. If not, the ISR must clear the interrupt flag. Interrupts : Execution of an interrupt Interrupts and timers 5/33

7 Typical interrupt vector table on ATMega88 0 x000 rjmp RESET ; Reset Handler 0 x001 rjmp EXT_INT0 ; IRQ0 Handler 0 x002 rjmp EXT_INT1 ; IRQ1 Handler 0 x003 rjmp PCINT0 ; PCINT0 Handler 0 x004 rjmp PCINT1 ; PCINT1 Handler 0 x005 rjmp PCINT2 ; PCINT2 Handler 0 x006 rjmp WDT ; Watchdog Timer Handler 0 x007 rjmp TIM2_COMPA ; Timer2 Compare A Handler 0 X008 rjmp TIM2_COMPB ; Timer2 Compare B Handler 0 x009 rjmp TIM2_OVF ; Timer2 Overflow Handler 0 x00a rjmp TIM1_CAPT ; Timer1 Capture Handler (---) 0 x01a RESET : ldi r16, high ( RAMEND ); Main program start 0 x01b out SPH, r16 ; Set Stack Pointer to top of RAM 0 x01c ldi r16, low ( RAMEND ) 0 x01d out SPL, r16 0 x01e sei ; Enable interrupts 0 x01f <instr > xxx Interrupts : Execution of an interrupt Interrupts and timers 6/33

8 Maskable interrupts ATmega48/88/ ICR1H and ICR1L Input capture register 1 Bit (0x87) ICR1[15:8] ICR1H An interrupt mask selects which interrupts are enabled (0x86) ICR1[7:0] ICR1L Read/write R/W R/W R/W R/W R/W R/W R/W R/W ATmega48/88/168 Initial value AVR Example: Timer/Counter interrupt mask (TIMSKn). The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the Similar for ICP1 other pin (or optionally peripherals on the Analog Comparator output for Timer/Counter1). The Input Capture TIMSK0 Timer/counter can be used interrupt for defining mask the register counter TOP value. The Bit Input Capture 7 Register 6 is 16-bit 5in size. To 4 ensure 3 that both 2 the high 1 and low 0bytes are read (0x6E) OCIE0B OCIE0A TOIE0 TIMSK0 simultaneously when the CPU accesses these registers, the access is performed using an 8-bit Read/write R R R R R R/W R/W R/W temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit Initial value registers. See Accessing 16-bit registers on page 110. Bits 7..3 Res: Reserved bits TIMSK1 Timer/Counter1 interrupt mask register These bits are reserved bits in the Atmel ATmega48/88/168 and will always read as zero. Bit (0x6F) ICIE1 OCIE1B OCIE1A TOIE1 Bit 2 OCIE0B: Timer/counter output compare match B interrupt enable TIMSK1 Read/write R R R/W R R R/W R/W R/W When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Initial value Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Bit 7, 6 Res: Match Reserved in Timer/Counter bits occurs, that is, when the OCF0B bit is set in the Timer/Counter These bits are unused Interrupt bits Flag in Register the Atmel ATmega48/88/168, TIFR0. and will always read as zero. Some interrupts are non-maskable (e.g., reset) Bit 15 OCIE0A: ICIE1: Timer/Counter1, Timer/Counter0 input output capture compare interrupt match enable A interrupt enable When this the bit OCIE0A is written bit to is one, written and to the one, I-flag and in the Status I-bit in Register the Status is set Register (interrupts is set, globally the Timer/Counter0 enabled), the Timer/Counter1 Compare Match Input A interrupt Capture is interrupt enabled. is The enabled. corresponding The corresponding interrupt is executed Interrupt if Vector a Compare (see Interrupts Match in on Timer/Counter0 page 56) is executed occurs, when that the is, ICF1 when Flag, the located OCF0A in bit TIFR1, is set is in set. the Timer/Counter 0 Interrupt Flag Register TIFR0. Bit 4, 3 Res: Reserved bits These Bit 0 bits TOIE0: are unused Timer/Counter0 bits in the ATmega48/88/168, overflow interrupt and enable will always read as zero. Interrupts : Maskable interrupts When the TOIE0 bit is written to one, and the I-bit in Interrupts the Status and Register timers is set, the 7/33

9 The global interrupt flag Sometimes, you do not want to be interrupted, for performance or data consistency reasons CLear Interrupts: turn off all interrupts CLI / cli(); SEt Interrupts: turn on all interrupts SEI / sei(); Enabling an interrupt requires both enabling it in the corresponding interrupt mask, and setting the global interrupt enabled flag Interrupts : Maskable interrupts Interrupts and timers 8/33

10 Saving and restoring the interrupt flag A more reusable and robust way On the AVR, the interrupt flag is in the status register # include <avr / interrupt.h> void do_something_atomic () { unsigned char sreg = SREG ;// remember status register cli (); // disable interrupts do_stuff (); // without being interrupted SREG = sreg ; // restore status register } take care if you rely on other flags in SREG See also ATOMIC_BLOCK in util/atomic.h Interrupts : Maskable interrupts Interrupts and timers 9/33

11 Handling interrupts in AVR-libc Interrupt names defined in header files (e.g., avr/iomx8.h) Refer to the documentation (avr-libc documentation link in the help menu of AVRstudio.) Example ISR for overflow in Timer 0 # include <avr / io.h> # include <avr / interrupt.h> ISR ( TIMER0_OVF_vect, ISR_NAKED ) { // do something each time timer0 overflows reti (); } Interrupts on AVR : Interrupts in AVR-libc Interrupts and timers 10/33

12 Handling interrupts (cont d) The ISR macro takes attributes to specify its behaviour ISR_BLOCK: run with interrupts disabled ISR_NONBLOCK: do not disable interrupts Nesting interrupts needs more careful analysis Avoid if not necessary ISR ( some_vect, ISR_BLOCK ) { // do something // NB! no reti () as that is done in the // epilogue inserted by the macro } Interrupts on AVR : Interrupts in AVR-libc Interrupts and timers 11/33

13 External interrupts The AVR has two kinds of external interrupts: PCINT: pin change interrupt generates an interrupt when a pin changes value available on all pins three sets of pins (controlled by PCICR) several pins can trigger the same interrupt may be handy for the two encoder signals INT0, INT1 more configurable: pin change, edge, or level triggered controlled by EICRA (PCINT14/RESET) PC6 (PCINT16/RXD) PD0 (PCINT17/TXD) PD1 (PCINT18/INT0) PD2 (PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 Interrupt sources Interrupts and timers 12/

14 Example, PCINT for pin 24 Consult data sheet pin 24 PCINT9 PCICR: PCINT14..8 PCIE1 Find the bit in PCMSK1 volatile int counter; ISR(PCINT1_vect) { // count positive edges if(pinc & (1<<PINC1)) counter++; } void setup_interrupt(){ PCICR = (1<<PCIE1); PCMSK1 = (1<<PCINT9); sei(); } Interrupt sources Interrupts and timers 13/33

15 Timers A counter, clocked from the system clock or externally Can output a waveform on its output pin(s) Prescaler for the system clock (clk/8, clk/64,..., clk/1024) Can give two (three) types of interrupts overflow when the counter wraps output compare when the counter reaches a set value more programmable, two compare values also used for waveform generation (input capture) saves the timer value when an external event occurs useful for accurately timestamping events only in timer 1 on the ATMega88 Interrupt sources : Timers and PWM Interrupts and timers 14/33

16 Prescaling Clocked by clk IO clk I/O clk Tn (clk I/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Clocked by clk IO /8 clk_i/o clk I/O clk Tn (clk I/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Interrupt sources : Timers and PWM Interrupts and timers 15/33

17 Timer usage Required configuration set prescaler for desired frequency range set mode of operation if needed, enable interrupts if needed, setup output pins (DDRx and TCCRnA) PWM mode(s) for waveform generation, it is usually best to use the built-in PWM modes if possible. (typically fast PWM) CTC mode Clear Timer on Compare match allows more fine-grained control over interrupt frequency Interrupt sources : Timers and PWM Interrupts and timers 16/33

18 Fast PWM mode Single slope counting OCRnx controls duty cycle OCRnx is double buffered in the PWM modes OCRnx interrupt flag set OCRnx update and TOVn interrupt flag set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period Interrupt sources : Timers and PWM Interrupts and timers 17/33

19 Fast PWM: Setting period time TOP can be fixed, or set using OCRnA or ICR1 OCRnx/BOTTOM update and TOVn interrupt flag set and OCnA interrupt flag set or ICFn interrupt flag set (interrupt on TOP) TCNTn OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) Period Interrupt sources : Timers and PWM Interrupts and timers 18/33

20 Count Clear Direction Control logic clk Tn TOVn (Int.req.) Clock select Edge detector Tn TOP BOTTOM Timer/counter TCNTn = = 0 (From prescaler) OCnA (Int.req.) = Waveform generation OCnA DATA BUS OCRnA = OCRnB Fixed TOP value OCnB (Int.req.) Waveform generation OCnB TCCRnA TCCRnB Interrupt sources : Timers and PWM Interrupts and timers 19/33

21 Tips Avoid using many interrupts concurrently prototype by polling, then switch to ISR if necessary Usually a good idea to disable interrupts while executing ISRs (e.g., ISR_BLOCK to avoid data races to avoid running out of stack space Try to keep ISRs very short if possible, only store data and/or set a flag and do the actual processing elsewhere Shared data must be global and volatile Concluding remarks Interrupts and timers 20/33

22 Tips... (cont d) Check (in data sheet) if interrupt flags are reset by the hardware or if you need to do it in code if not reset, nonblocking ISRs will get called over and over UART interrupts level triggered external interrupts Concluding remarks Interrupts and timers 21/33

23 Summary, interrupts We have introduced The interrupt mechanism Types Execution Interrupts on the AVR interrupt functionality in avr-libc external interrupts timers, PWM and... do read the data sheet Concluding remarks Interrupts and timers 22/33

24 Concurrency Functions executing (logically) in parallel time sharing Independent routines (preemptive multi-tasking) Interrupting, or preempting, each other Example: two independent controllers Cooperative multi-tasking Triggering, or yielding to, each other Example: a controller and its operator communication On a single CPU routines interrupting (preempting) each other On multiprocessor machines true parallelism Concurrency, a brief overview Interrupts and timers 23/33

25 In small embedded systems Typically No operating system No threads or concurrency primitives A single program A main loop One or a few interrupt routines Potential problems Data consistency (data races) Deadlock Concurrency, a brief overview Interrupts and timers 24/33

26 Race conditions Concurrent acces of a shared resource by multiple routines Even if all routines are correct, the result may sometimes be correct and sometimes wrong The result depends on the order of execution ( interleaving ) of the individual machine instructions Shared resources Variables (i.e., memory locations) Registers Peripherals Concurrency, a brief overview Interrupts and timers 25/33

27 Race conditions (cont d) Example: bank account void deposit ( int acctnbr, int amount ) { int bal = getbalance ( acctnbr ); [ d1] bal = bal + amount ; [ d2] setbalance ( acctnbr, bal ); [ d3] } void withdraw ( int acctnbr, int amount ) { int bal = getbalance ( acctnbr ); [ w1] bal = bal - amount ; [ w2] setbalance ( acctnbr, bal ); [ w3] } Concurrency, a brief overview Interrupts and timers 26/33

28 Example (cont d) Starting balance: 1000 Concurrently Salary is paid: deposit You withdraw 500 What happens if the routines can interrupt each other at any instant? Concurrency, a brief overview Interrupts and timers 27/33

29 Correct executions d1: bal == 1000 w1: bal == 1000 d2: bal == w2: bal == 500 d3: setbalance(bal) w3: setbalance(bal) w1: bal == d1: bal == 500 w2: bal == d2: bal == w3: setbalance(bal) d3: setbalance(bal) * balance is * balance is Concurrency, a brief overview Interrupts and timers 28/33

30 Wrong executions (examples) d1: bal == 1000 w1: bal == 1000 w1: bal == 1000 w2: bal == 500 w2: bal == 500 d1: bal == 1000 w3: setbalance(bal) d2: bal == d2: bal == d3: setbalance(bal) d3: setbalance(bal) w3: setbalance(bal) * balance is * balance is 500 Concurrency, a brief overview Interrupts and timers 29/33

31 The problem Class of operations: read-modify-write needs to be atomic the real value must be consistent with temporary values (local variables) used during the modification Typical scenario Check a condition Act on it, possibly affecting system state Examples Check if data is available in buffer, then read Check that a peripheral is free, then use it Read/write a set of variables that must be consistent Concurrency, a brief overview Interrupts and timers 30/33

32 The solution Critical sections atomic pieces of code that may not (cannot) be interrupted by other routines At the low level turning off interrupts At the higher level semaphores, monitors studied in real-time programming courses Concurrency, a brief overview Interrupts and timers 31/33

33 Deadlock (sketched version) Waiting in a critical section for a condition caused by code in another critical section May lead to circular waiting waiting in a critical section makes it impossible to enter another critical section i.e., the program hangs Avoid waiting in critical sections in particular, interrupt service routines More on the topic, and its analysis, in the real-time programming courses Concurrency, a brief overview Interrupts and timers 32/33

34 Summary, concurrency Be aware of concurrency Keep programs simple Turn off interrupts in interrupt service routines in critical sections of the main loop but not when waiting for an interrupt, of course Avoid waiting in interrupt routines Risk of deadlock Risk of missing other interrupts (i.e., keep ISRs short) Concurrency, a brief overview Interrupts and timers 33/33