Fixed-Width Recursive Multipliers

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1 Fixed-Width Recursive Multipliers Presented by: Kevin Biswas Supervisors: Dr. M. Ahmadi Dr. H. Wu Department of Electrical and Computer Engineering University of Windsor

2 Motivation & Objectives Outline Recursive Digital Multipliers Existing Truncation Methods Fixed-Width Recursive Multiplier Simulation Results Conclusions 1

3 Motivation Constant word size is required throughout arithmetic operations for many applications, i.e. DSP Multiplication is of biggest concern in DSP To cope with the problem, Fixed-Width Multipliers are utilized Fixed-width multipliers are usually obtained by applying truncation schemes to array or tree multipliers We find that the inherent structure of the digital recursive multiplier is also suitable for fixed-width applications 2

4 Objectives Present architecture of the fixed-width recursive multiplier Perform: Error analysis for different truncation schemes Gate complexity analysis 3

5 Recursive Digital Multipliers Recursive, or divide and conquer multiplication was proposed by Karatsuba and Ofman in 1962 Karatsuba-Ofman Algorithm (KOA) multiplies two long integers by executing multiplications and additions on their divided parts Fundamental principles of KOA is utilized in the recursive algorithm [Danysh and Swartzlander] 4

6 Recursive Digital Multipliers Mathematically, the recursive algorithm is established around the fact that any 2n x 2n bit multiplication can be carried out through four n x n bit sub-multiplications Considering two unsigned 2n-bit operands: Multiplicand: Multiplier: A = A H 2 n + A L X=X H 2 n + X L Product: Y = A X = (A H 2 n + A L ) (X H 2 n + X L ) = A H X H 2 2n + (A L X H + A H X L ) 2 n + A L X L 5

7 Recursive Digital Multipliers Block diagram representation for multiplication with a single level of recursion Y is the fixed-width rounded product of 2n bits 6

8 Recursive Digital Multipliers Of the 4 sub-multiples, the one contributing the least to the final product is A L X L Truncation schemes to be presented will target this particular component 7

9 Existing Truncation Methods Truncation schemes generally involve not generating the complete partial product matrix in a multiplication, and then applying a scheme to compensate for the error Correction schemes: - Constant Correction [Y. C. Lim] - Variable Correction [E. J. King and E. E. Swartzlander, Jr.] 8

10 Existing Truncation Methods Constant Correction A constant is added to the remaining columns of the partial products matrix based on average value of the bits which are not formed and expected value of rounding error Variable Correction Correction value is data dependent: - If all elements are zeros in the most significant column not formed, there is no correction - If all elements are ones, then a maximum correction value is used Variable correction results in a lower variance in error Constant correction is efficiently implemented with tree multipliers and variable correction with array multipliers 9

11 Fixed-Width Recursive Multiplier A data-dependent truncation method is proposed Original recursive multiplier can be represented in this way: 2n A H x X L A H x X H A L x X L A L x X H The component A L X L will be truncated 10

12 n 1 n 1 RESEARCH n 2 CENTRE 1 FOR INTEGRATED i A = MICROSYSTEMS - UNIVERSITY OF WINDSOR L an 12 + an a12 + a0 = ai2, i = 0 Fixed-Width Recursive Multiplier Assume A L and X L are n-bit unsigned binary numbers where: n 1 n 1 n 2 1 = = i L n n 0 i i= 0 A a 2 a 2 a 2 a a 2, n 1 n 1 n 2 1 = = j L n n 0 j j= 0 X x 2 x 2 x 2 x x 2. The product can be expressed as: n 1 n 1 A X = ( a x ) 2 L L i j i= 0 j= 0 i+ j 11

13 Fixed-Width Recursive Multiplier Truncation scheme involves first removing the least significant component of the recursive multiplier, A L X L For error compensation, most significant partial product bit of A L X L, a n-1 x n-1, is placed at bit position 2n-1 (which was the MSB position of A L X L ). 12

14 Fixed-Width Recursive Multiplier Inclusion of partial product bits a n-2 x n-2 and a n-3 x n-3 at bit positions 2n-2 and 2n-3, respectively, can provide additional correction, i.e.: C = a x 1 n-1 n-1 2 2n-1 C = a x 2 + a x 2 2n-1 2n-2 2 n 1 n 1 n 2 n 2 C = a x 2 + a x 2 + a x 2 2n-1 2n-2 2n-3 3 n 1 n 1 n 2 n 2 n 3 n 3 d C = a x d n-k n-k k = 1 2 2nk - Thus, mathematically, the term A L X L is approximated by the simpler correction expression, C d : d n 1 n 1 2nk - i+ j d = n-k n-k2 ( i j) 2 k= 1 i= 0 j= 0 C a x a x 13

15 Fixed-Width Recursive Multiplier The range of C and A L X L are also comparable: 2n n+ 1 0 ALX L ( ), 0 C 2 2n 1 It can be seen graphically that maximum value of C tends to approximate the maximum value of A L X L quite well for a large range of n Approximation improves as d increases 1 2n 1 2n 2 0 C 2 (2 + 2 ) d 2 n k 0 C d ( 2 ) k = 1 14

16 Simulation Results Error Statistics: Comparison with existing fixed-width multipliers (6-bit) Fixed-Width Multiplier Type Mean Max. Positive Error Max. Negative Error Variance of Error Truncation True Rounding Constant Correction Constant Correction Variable Correction Recursive Multiplier (Removal of A L X L ) Recursive Multiplier (With proposed truncation scheme) Table I. Error Statistics (2n = 6) 15

17 Simulation Results Error Statistics: Comparison of different sized fixed-width recursive multipliers with 1, 2 and 3 correction bits 2n Number of Correction Bits Mean Error Max. Positive Error Max. Negative Error Variance of Error Table II. Fixed-Width Recursive Multiplier Error Statistics (2n = 6, 8, 10, 12) 16

18 Simulation Results Complexity Comparison: Savings in number of gates It is assumed that base multiplier for the recursive structure is array multiplier Estimate one full adder as 12 gates, one half adder as 4 gates 2n Original Recursive Multiplier Fixed-Width Recursive Multiplier No. of Gates No. of Gates % Savings Table III. Complexity Comparison 17

19 Simulation Results Proposed fixed-width recursive multiplier performs better than those (6-bit multipliers) presented in literature, in terms of computational accuracy Generally, use of more correction bits improves error statistics for all recursive multiplier sizes In terms of complexity, hardware savings are close to 25% when n is large Further hardware reduction is expected in fixed-width multipliers with multi-level recursion 18

20 Multi-level Recursive Multiplier Maximum complexity savings after truncation of least significant submultiple: Levels of Recursion Projected Max. Complexity Savings (%) Table IV. Complexity Savings for Multi-level Recursion 19

21 Conclusions A fixed-width recursive multiplier design has been proposed and simulated Truncation scheme which reduces gate complexity, while minimizing error, has been presented Computational accuracy can be improved with additional correction bits With multi-level recursive multipliers, hardware reduction could potentially reach 44% (3-level recursion) 20

22 Thank you for your attention! 21

23 References M. D.Ercegovac and T. Lang, Digital Arithmetic, Morgan Kaufmann Publishers, San Francisco, USA, Earl E. Swartzlander, Jr., Truncated multiplication with approximate rounding, Asilomar Conference on Signals, Systems, and Computers, vol. 2, pp , Oct Y. C. Lim, Single-precision multiplier with reduced circuit complexity for signal processing applications, IEEE Transactions on Computers, vol. 41, 1992, pp M. J. Schulte and E. E. Swartzlander, Jr., Truncated multiplication with correction Constant, VLSI Signal Processing, VI, New York, IEEE Press, 1993, pp E. J. King and E. E. Swartzlander, Jr., Data-dependent truncation scheme for parallel multipliers, 31st Asilomar Conference on Signals, Circuits and Systems, Pacific Grove, CA, 1997, pp A. Karatsuba and Y. Ofman, "Multiplication of multidigit numbers on automata", Sov. Phys.-Dokl. (English Translation), vol. 7, pp , 1963 A.N. Danysh, and E.E. Swartzlander Jr., "A recursive fast multiplier", Asilomar Conference on Signals, Systems & Computers, vol. 1, pp ,

TRUNCATION SCHEMES FOR RECURSIVE MULTIPLIERS

39 th Asilomar Conference on Signals, Systems and Computers TRUNCATION SCHEMES FOR RECURSIVE MULTIPLIERS Pedram Mokrian,, Huapeng Wu, Majid Ahmadi Research Centre for Integrated Microsystems Department