Verilog Implementation of High Performance RC6 Algorithm using Ancient Indian Vedic Mathematics

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1 ISSN Vol.02,Issue.17, November-2013, Pages: Verilog Implementation of High Performance RC6 Algorithm using Ancient Indian Vedic Mathematics D. RAJESH 1, M. L. RAVI CHANDRA 2 1 PG Scholar, Dept of ECE, NIET, A.P-India, dasarirajesh710@gmail.com. 2 Assoc Prof, Dept of ECE, NIET, A.P-India, mlravigates@gmail.com. Abstract: RC6 is the successor to RC5. It is one of the most promising algorithms that are both fast and secure. It uses four w- bit registers, integer multiplication, quadratic equation and fixed bit shifting. This paper examines how the Vedic algorithm of Urdhva tiryagbhyam speeds up the computation of this algorithm when compared with conventional algorithms in existence. Keywords: RC6, Urdhva, Tiryagbhyam. I. INTRODUCTION RC6, a cryptographic algorithm, is specified as RC6- w/r/b, where w is word size, r is the number of rounds and b is the length of encryption key in bytes. The degree of encryption is based on number of rounds (r) in the algorithm. Thus a user requiring high encryption would prefer higher values of r. The encryption and decryption algorithms use integer multiplication. Actually; multiplication is an important fundamental function in arithmetic operations. Since multiplication dominates the execution time of this algorithm, so there is a need of high speed multiplier. This paper presents a Vedic multiplication algorithm, which uses less number of logic elements. RC6 is a symmetric key block cipher derived from RC5. It was designed by Ron Rivest, Matt Robs haw, Ray Sidney, and Yiqun Lisa Yin to meet the requirements of the Advanced Encryption Standard (AES) competition by the National Institute of Standards and Technology (NIST). The algorithm was one of the five finalists, and was also submitted to the NESSIE and CRYPTREC projects. Though the algorithm was not eventually selected, RC6 remains a good choice for security applications. It is proprietary of RSA Security. The design of RC6 began with a consideration of RC5 as a potential candidate for an AES submission. Modifications were then made to meet the AES requirements, to increase security, and to improve performance. The inner loop, however, is based around the same half-round" found in RC5. RC5 was intentionally designed to be extremely simple, to invite analysis shedding light on the security provided by extensive use of data-dependent rotations. Since RC5 was proposed in 1995, various studies provided a greater understanding of how RC5's structure and operations contribute to its security. While no practical attack on RC5 has been found, the studies provide some interesting theoretical attacks, generally based on the fact that the rotation amounts" in RC5 do not depend on all of the bits in a register. RC6 was designed to thwart such attacks, and indeed to thwart all known attacks, providing a cipher that can offer the security required for the lifespan of the AES. The philosophy of RC5 is to exploit operations (such as rotations) that are efficiently implemented on modern processors. RC6 continues this trend, and takes advantage of the fact that 32-bit integer multiplication is now efficiently implemented on most processors. Integer multiplication is a very effective diffusion" primitive, and is used in RC6 to compute rotation amounts, so that the rotation amounts are dependent on all of the bits of another register, rather than just the low-order bits (as in RC5). As a result the new RC6 has much faster diffusion than RC5. This also allows RC6 to run with fewer rounds at increased security and with increased throughput. RC6 is more exactly specified as RC6-w/r/b, where the parameters w, r, and b respectively express the word size (in bits), the number of rounds, and the size of the encryption key (in bytes). Since the AES submission is targeted at w=32 and r=20, we implemented this version of RC6 algorithm, using a 32 bits word size, 20 rounds and 16 bytes (128 bits) encryption key lengths. The RC6 block cipher diagram as shown in the fig 1. A key schedule generates 2r + 4 words (w bits each) from the b-bytes key provided by the user. These values (called round keys) are stored in an array S [0, 2r+3] and are used in both encryption and decryption. RC6 works on a block size of 128 bits and it is very similar to RC5 in structure, using data-dependent rotations, modular addition and XOR operations; in fact, RC6 could be viewed as interweaving two parallel RC5 encryption processes. However, RC6 does use an extra multiplication operation not present in 2013 SEMAR GROUPS TECHNICAL SOCIETY. All rights reserved.

2 D. RAJESH, M.L. RAVI CHANDRA RC5 in order to make the rotation dependent on every bit in a word, and not just the least significant few bits. The computation of f(x) = (X (2X + 1)) mod 2 w is the most critical arithmetic operation of this block cipher. The goal of this thesis is to implement the RC6 Cipher with FPGA as the target technology. algorithm for the multiplication of large numbers as a lot of propagation delay is involved in such cases. To deal with this problem, we now discuss Nikhilam Sutra which presents an efficient method of multiplying two large numbers. A. Implementation of 2x2 bits Vedic multiplier It is clear that the basic building blocks of this multiplier are one bit multipliers and adders. One bit multiplication can be performed through two input AND gate and for addition, full adder can be utilized. The 2 x 2 bit multiplier is shown in fig.3. Fig.1. RC6 Cipher block diagram. II. VEDIC MULTIPLIER The hardware realization of a 4-bit multiplier is in this hardware design is very similar to that of the famous array (fig.2) multiplier where an array of adders is required to arrive at the final product. All the partial products are calculated in parallel and the delay associated is mainly the time taken by the carry to propagate through the adders which form the multiplication array. Clearly, this is not an efficient algorithm for the multiplication of large numbers as a lot of propagation delay is involved in such cases. To deal with this problem, we now discuss Nikhilam Sutra which presents an efficient method of multiplying two large numbers Fig.3. Block diagram of 2x2 Multiplier Fig.2. Hardware architecture of the Urdhva Tiryakbhyam multiplier The hardware realization of a 4-bit multiplier and the hardware design is very similar to that of the famous array multiplier where an array of adders is required to arrive at the final product. All the partial products are calculated in parallel and the delay associated is mainly the time taken by the carry to propagate through the adders which form the multiplication array. Clearly, this is not an efficient Fig.4. RTL View of 2x2 Bits Multiplier A1 A0 X B1 B A1B0 A0B0 A1B1 A0B Q3 Q2 Q1 Q0 (1) As above let s take two inputs, each of 2 bits; say A1A0 and B1B0. Since output can be of four digits, say Q3Q2Q1Q0. As per basic method of multiplication, result

3 Verilog Implementation of High Performance RC6 Algorithm using Ancient Indian Vedic Mathematics is obtained after getting partial product and doing addition. In Vedic method, Q0 is vertical product of bit A0 and B0, Q1 is addition of crosswise bit multiplication i.e. A1 & B0 and A0 and B1, and Q2 is again vertical product of bits A1 and B1 with the carry generated, if any, from the previous addition during Q1. Q3output is nothing but carry generated during Q2 calculation. This module is known as (fig.4) 2x2 multiplier block. B. implementation of 4x4 bits Vedic multiplier For higher no. of bits in input, little modification is required. Divide the no. of bit in the inputs equally in two parts. Fig.7. RTL View of 4x4 Bit Vedic Multiplier Fig.5. Block diagram of 4x4 Bit Vedic Multiplier Let s analyze 4x4 multiplications, say A3A2A1A0 and B3B2B1B0. Following are the output line for the multiplication result, Q7Q6Q5Q4Q3Q2Q1Q0. Block diagram of 4x4 Vedic Multiplier is given in fig 5. Let s divide A and B into two parts, say A3 A2 & A1 A0 for A and B3B2 & B1B0 for B. Using the fundamental of Vedic multiplication, taking two bit at a time and using 2 bit multiplier block. Each block as shown above fig.6 is 2x2 bits multiplier. First 2x2 multiplier inputs are A1 A0 and B1 B0.The last block is 2x2 multiplier with inputs A3 A2 and B3 B2. The middle one shows two, 2x2 bits multiplier with inputs A3A2 & B1B0 and A1A0 & B3B2. So the final result of multiplication, which is of 8 bit, Q7Q6Q5Q4Q3Q2Q1Q0. The 4x 4 bit multiplier is structured (fig.7) using 2X2 bit blocks. C. implementation of 8x8 bits Vedic multiplier The 8x 8 bit multiplier is structured using 4X4 bit blocks as in this figure the 8 bit multiplicand A can be decomposed into pair of 4 bits AH-AL. Similarly multiplicand B can be decomposed into BH-BL. The 16 bit product can be written as: P=AxB=(AH-AL)x(BH-BL) =AH x BH+AH x BL+AL x BH+ALxBL (2) RESULT = (Q15- Q8) & (Q7- Q4) & (Q3-Q0) Fig.8. 8X8 Bits decomposed Vedic Multiplier. The outputs of 4X4 bit multipliers are added accordingly to obtain the final product. Thus, in the final stage two adders are also required. Now the basic building block of 8x8 bits Vedic multiplier is 4x4 bits multiplier which implemented in its structural model (fig.8). For Fig.6. Algorithm of 4x4 bit Vedic Multiplier. bigger multiplier implementation like 8x8 bits multiplier

4 D. RAJESH, M.L. RAVI CHANDRA the 4x4 bits multiplier units has been used as components which are implemented already in ModelSIm6.1e or Xilinx ISE9.2i library. The structural modeling of any design shows fastest design. D. implementation of 16x16 bits Vedic multiplier The 32 bits multiplicand A is decomposed into pair of 16 bits AH-AL. Similarly multiplicand B can be decomposed into BH-BL. Architecture of 32x32 bits Vedic Multiplier is shown in fig.10 as above. The outputs of 16X16 bit multipliers are added accordingly to obtain the 64 bits final product. Thus, in the final stage two adders are also required the 32X32 bit multiplier is structured using 16X16 bit blocks. The block diagram of 32 x32 bit multiplier (fig.11) is shown below. The implemented RTL View of 32x32 bits Vedic Multiplier by using 16x16 blocks (fig.12) with the help of ModelSim6.1e Tool is given below: RESULT = (Q31- Q16) & (Q15- Q8) & (Q7- Q0) Fig.9. 16x16 Bits decomposed Vedic Multiplier. Fig.11. Block diagram of 32X32 Bit Vedic Multiplier The 16X16 bit multiplier structured using 8X8 bits blocks as in this (fig.9) 16 bit multiplicand A can be decomposed into pair of 8 bits AH-AL. Similarly multiplicand B can be decomposed into BH-BL. The outputs of 8X8 bit multipliers are added accordingly to obtain the 32 bits final product. Thus, in the final stage two adders are also required. Similarly, we have extended same for input bits 32, 64. E. implementation of 32x32 bits Vedic multiplier RESULT = (Q63-Q32) & (Q31-Q16) & (Q15-Q0) Fig X32 Bits proposed Vedic Multiplier. Fig.12. RTL View of 32X32 bits Vedic Multiplier III. RC6 ALGORITHM RC6 can be divided into 3 distinct subdivisions. They are, 1. Key generation module 2. Encryption module and 3. Decryption module

5 Verilog Implementation of High Performance RC6 Algorithm using Ancient Indian Vedic Mathematics A. Key Generation In Key scheduling algorithm more words are derived from the user-defined key for the use for encryption and decryption. The user supplies a key of b bytes, where 0 b 255. The key bytes are zero-padded and stored in little- Indian order. The 2r+4 words are derived and stored in the array S[0,.,2r+3]. This array is used in both encryption and decryption. B. Encryption The plain text is stored in 4 registers A, B, C, and D each of w bit. The 44 sub keys are used to encrypt the plain text to give cipher text. The algorithm can mathematically be represented as: Input: Plaintext stored in four w-bit input registers A, B, C, D Number r of rounds w-bit round keys S[0,,2r + 3] Output: Cipher text stored in A, B, C, D Procedure: B = B + S[0] D = D + S[1] for i = 1 to r do { t=(bx(2b+1))<<<log 2 w u=(dx(2d+1))<<< log 2 w A= ((A t)<<<u)+s[2i] C=((C u)<<< t)+s[2i+1] (A,B,C,D)=(B,C,D,A) } A=A+S[2r + 2] C=C+S[2r+3] Here B and D are pre-whitened, but A and C are postwhitened. Loop controls the rounds, defined by r. C. Decryption The Cipher text is converted to plain text again using the 44 sub keys. The decryption process is just the reverse of encryption process. The algorithm can mathematically be represented as: Input: Cipher text stored in four w-bit input registers A, B, C, D Number r of rounds w-bit round keys S[0,,2r + 3] Output: Plaintext stored in A, B, C, D Procedure: C=C-S[2r+3] A=A- S[2r+2] for i = r down to 1 do { (A,B,C,D)=(D,A,B,C) u=(d x (2D+1))<<< log 2 w t=(b x (2B+1))<<< log 2 w C=((C-S[2i+1])>>> t) u A=((A - S[2i]) >>> u) t } D= D-S[1] B= B-S[0] Here C and A are pre-whitened, but D and B are postwhitened. Loop runs in reverse for r rounds Computation of multiplication is the critical arithmetic operation of the block cipher. Therefore, area and delay of a RC6 processor are closely related to the hardware operator carrying out F(X)=(X(2X+1)) mod 2 w. Hence, Urdhva tiryagbhyam, a Vedic algorithm, is used in the place of wherever the multiplications involved operations so that we can reduce the delay of RC6 algorithm. IV. RESULTS ANALYSIS From the Table 1, it is clear that how the application of Vedic sutra reduces the delay by using less number of logic elements. Hence the layout area is reduced and high speed of computation is achieved. Simulation is done using ModelSim10.2c. Synthesis analysis is achieved using xilinx 12.1c. And the result is shown in fig A. RTL Top Module Fig.13. RTL schematic for top module

6 D. RAJESH, M.L. RAVI CHANDRA TABLE I: COMPARISON BETWEEN CONVENTIONAL AND VEDIC METHOD FOR THE COMPUTATION OF F(X) As shown in figure 13 Key_in, plain_text_in, clk, rst are the inputs and ciper_text_out, plain_text_out are the outputs. From figure 14 Key_in, plain_text_in, clk, rst are the inputs key_index_out are the key outputs and ciper_text_out is encryption output. Ciper_text_in, key_in, clk, rst are the inputs, plain_text_out is the decryption output. As shown in below figure 15 plaintext is the encryption output and using this as a input we will calculate the decryption output and for the decryption output we will calculate the hash code by using rc6 algorithm and it produces 128bit output. 1. Encryption Fig.14. RTL schematic for encryption 2. Decryption Fig.15. RTL schematic for decryption

7 Verilog Implementation of High Performance RC6 Algorithm using Ancient Indian Vedic Mathematics B. Simulation results 1. Key Generation Fig.16. key generation Simulation result 2. Encryption Fig.17. encryption Simulation result From Fig 16 the Key_in value is then will get key_generated value as 42adf0feed3a8bd704943ff38229d9b065278afa c43065aa3a15f3eb603bdf5204f03450f64c65807aba5c5. For figure 17 the Key_in= and plain_text_in= are the input values produced will get the output as ciper_text_out=80d419c42f04fefed5532 5b63cf2df47. ciper_text_in=80d419c42f04fefed5532 5b63cf2df47 is the decryption input and output will get as plain_text_out=

8 D. RAJESH, M.L. RAVI CHANDRA 3. Decryption Fig.18. decryption Simulation result C. Top Module Fig.19. Top module Simulation result In this top module Key_in= and plain_text_in= are inputs values and will get outputs as ciper_text_out=80d419c42f04fefed55325b63cf2df47 and plain_text_out= V. CONCLUSIONS Thus an efficient multiplier using a Vedic algorithm which has high speed, less complexity and consuming much less area is designed. By using this multiplier design, high speed RC6 block Cipher is constructed. Thereby, high performance RC6 algorithm design is constructed. RC6 which has different algorithm of encryption and decryption has been implemented to have

9 Verilog Implementation of High Performance RC6 Algorithm using Ancient Indian Vedic Mathematics the same algorithm between encryption and decryption though inserting symmetry layer using simple rotate and logical operation. That means the half of whole RC6 round uses encryption algorithm and the rest of it uses decryption one and symmetry layer has been put into the middle of encryption and decryption. The proposed RC6 algorithm has no difference with the original one in the speed of process. However it is quite security because by inserting symmetry layer the path of high probability which is needed for differential and linear analysis is cut off so that it is hard to be analyzed. The proposed algorithm decreases the area to about ½ when it implemented to RFID tag including Smart Card and electronic chip which is hardware environment, and can be easily applied to the algorithm which has different encryption and decryption, and make it same. Therefore it can be good idea to be used to design a new block cipher algorithm VI. REFERENCES [1] A. J. Menezes, P. C. Van Oorschot, and S. A. Vanstone, Handbook of Applied Cryptography, CRC Press, M. Young, the Technical Writer s Handbook. Mill Valley, CA: University Science, [2] A. P. Nicholas, K. R. Williamss, J. Pickles, Applications of Urdhva Sutra, Spiritual study group, Roorkee (India), [3] A. P. Nicholas, K. R. Williamss, J. Pickles VerticallyrandkCrosswise Applications of the Vedic Mathematics Sutra, Motilal Banasidass Publishers, Delhi, [4] B. Parhami, Computer Arithmetic, Oxford University Press, [5] R. Zimmerman, A. Curiger, H. Bonnenberg, H. Kaeslin, N. Felber, and W. Fichtner, A 177 Mbit/s VLSI Implementation of the International Data Encryption Algorithm, IEEE Journal of Solid State Circuits, 29(3): , 1994.