Interconnect Testing of Boards with Partial Boundary Scan

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1 Interconnect Testing of Boards with Partial Boundary Scan Gordon D. Robinson & John G. Deshayes GenRad, Inc, 3 Baker Ave. Concord, MA 1742 ABSTRACT Test generation and diagnosis of shorts and opens for boards containing a mixture of boundary scan and normal parts is a difficult problem; much of the difficulty is caused by the fact that the normal logic is powered, active and unpredictable whenever the boundary scan circuitry is being used. Shorts between the boundary scan and conventional parts of the circuit cause significant disruption to boundary scan interconnect diagnosis. In-circuit test access to nodes without boundary scan control can be used to solve these problems, leading to a test method which, although using several distinct stages, is understandable and which can be generated automatically. INTRODUCTION Several papers [2,3,4,5] have described how to perform interconnect testing on boards that contain complete boundary scan facilities. The availability of standard components and cells which adhere to IEEE Std [1] will result in many boards containing a mixture of boundary scan and normal parts, while few will contain only boundary scan parts. Performing a good interconnect test on boards with partial boundary scan facilities is therefore an important practical problem. A good interconnect test method for partial boundary scan boards achieves several goals: The test can be generated automatically using information which is likely to be available and reliable. It will detect shorts between any nodes with either tester or boundary scan access, and give an accurate diagnosis of which nodes are shorted. It will detect opens when there are several access points on the same node, and give an accurate diagnosis of the disconnected access points. In particular it will identify and diagnose open drivers on nodes with several drivers. It will only rarely give incorrect diagnoses in the presence of shorts to totally inaccessible nodes. It will not damage or unduly stress the board. The most significant factor that makes mixed interconnect testing difficult is that all of the logic must be powered in order to use the boundary scan facilities; and so the conventional logic, i.e., that without boundary scan, reacts to changes on the boundary scan signals. See, for example, nodes A and C in Figure 1. The conventional logic may also contain free-running clocks, circuits that are hard to initialize, and other features that make any form of test generation difficult. In order for a test generation and diagnostic method to work reliably, it must assume the worst about the conventional logic: not only are the conventional nodes impossible to control, they are impossible to initialize and so will behave unpredictably and unrepeatably. This means that any shorts between conventional nodes and boundary scan nodes will cause unpredictable and unrepeatable failed test results International Test Conference CH291-6//572$1.OO 199 IEEE

2 Some other factors which add complexity, but no significant theoretical difficulty, to this test generation and diagnostic process include: There are many possible configurations of boundary scan components. There may be single or multiple chains; multiple chains may be completely independent, or may share TMS signals or may share TDI and TDO signals. Some bus nodes are driven by a mixture of boundary scan and non-boundary scan components. Some nodes, such as C in Figure 1, have boundary scan output pins but no boundary scan input pins. Figure 1: Partial Boundary Scan Circuits BACKGROUND Other nodes, such as F in Figure 1, have boundary scan input pins but no boundary scan output pins. Some nodes may have neither tester access nor boundary scan access, and faults involving such nodes could confuse the algorithms. This paper describes the theory of a method for solving this test problem. This method produces reliable diagnostic information even in the presence of multiple shorts between different types of node. Before going into the details of our methods, let us review the ideas and terminology of pure boundary scan interconnect testing, because we will be adapting these ideas to mixed situations. Much of this terminology is from Jarwala and Yau[2]. A boundary scan interconnect test uses the testability facilities to apply a value to each of the boundary scannodes simultaneously, and tocapture the response at the input pins on those nodes. The values applied are called a Parallel Test Vector (PTV); the values captured a Parallel Response Vector (PRV). Several different PTVs are needed to perform the test. The sequence of values applied to a single node by the collection of PTVs is called a Sequential Test Vector (STV); the corresponding sequence of values captured by a single pin is known as the Sequential Response Vector (SRV). Interconnect testing is easy to understand if the STV is treated as an identifier for the node, and the SRV is the identifier of wherever the pin is connected to. Generating boundary scan interconnect tests consists of choosing the identifiers for each node. As a minimum all the identifiers must be different, and the all zero and all one values should not be used. When a node can be driven by several different devices, each such device should contribute both a high and a low to the identifier. Ignoring complex analog situations, whenever a group of nodes is shorted together, the pins on those nodes will see the same identifier. The converse is 573

3 not necessarily true; it is possible for nodes to have the same identifier when they are not shorted toeach other. For example if a group of shorted nodes has the same identifier as another node should have, that node could be part of the shorted group. This situation is termed aliasing in [2]. Aliasing and other more complicated cases can be avoided [2] by choosing identifiers where only one node has the value that dominates a short. Such identifiers are too long to use all the time, and so some methods use a combination of precalculated short identifiers and adadtive identifiers that are calculated while diagnosing the results from applying the precalculated identifiers. The adaptive identifiers need only be long enough to give an unambiguous diagnosis for the problems that the precalculated patterns leave unclear. Impaet of Partial Boundary Scan The term boundary scan node refers to a node that can be controlled and observed by boundary scan facilities. When a short occurs between a boundary scan node and a conventional node, the straightforward interconnect test methods for boundary scan encounter significant problems, because the conventional logic is active during such testing. The short will cause the boundary scan node to have the wrong value whenever the boundary scan node is at the non-dominant level and the conventional node is at the dominant level. If we make the reasonable assumptions that the logic values in the conventional logic are evenly split between high and low, and that the non-dominant values will occur frequently in identifiers, we see that such a short may make a very significant difference to the observed SRVs. Approximately a quarter of the bit positions will be wrong, normally in one direction, which means that there is a significant possibility of misdiagnosis. In addition, because the conventional logic is not being strongly controlled, and is certainly not carefully initialized, those results are likely to be unrepeatable. Attempts to initialize the conventional logic are also likely to fail because the types of fault we are after in interconnect testing are exactly the ones which most often make complex initialization sequences go wrong. we Perform the following stages: METHOD OVERVIEW interconnect test in the First, a conventional shorts test between all the places where the tester has physical access. Second, a test that the testability circuitry in the boundary scan components and the scan path segments between components are all working well enough for them to be usable by later stages. We call this the scan path integrity test. Third, a test for shorts between nodes with physical tester access and boundary scan nodes without such access. We call this the interaction test, because it is looking for interactions between the two areas of the circuit. Finally, a test for opens and shorts on the pure boundary scan nodes themselves. We call this the interconnect test, because it is very similar to other boundary scan interconnect test methods. The interaction and interconnect phases can be run in either order, but this sequence gives simpler diagnostic algorithms. Each of these phases also detects some problems other than its main focus; some of those details are described later. No specific part of the test looks for shorts between nodes with no access at all, nor between inaccessible nodes and accessible ones. Realistically, access to all nodes in a shorted group is needed to be sure that the group has been identified accurately. Our method does take considerable care to ensure that such faults do not confuse the tests such that they give an incorrect diagnosis. Diagnostic Structure This interconnect test is performed in several stages, each of which produces some strong conclusions and some tentative ones. We therefore delay making any definite diagnoses until we have seen all of the evidence. As we run each part of the test we accumulate facts and opinions in the following categories: 574

4 A node has a definite problem. This can never be negated, but is almost always explained by a more specific diagnosis. A set of nodes are suspected of being shorted together. This can be negated by a discovery that some of them are definitely not shorted together. Such negation may mean that we have no idea why a node has a problem, or may split the set into disjoint subsets. It may even remove a node from suspicion completely when aliasing occurs. A node has an open suspected on some pin or pins. A node is suspected of having a driver that is never active; this may well be caused by an open on the driver pin. A node is suspected of having a permanently active driver. After we have run all of the stages of the test, we give a summary of the information remaining in this set of data. CONVENTIONAL SHORTS TEST The first part of the test is a conventional shorts test between all nodes with tester access, using the shorts test facilities of the tester. This part is performed first because it is safe to do, and can detect many shorts which could damage the board if board power were applied. Such shorts testing is also extremely accurate, being based on a direct measurement of the resistance between pairs of nodes. Many users will stop testing the board immediately if this phase identifies problems. If the tester has access to all of the points on the boundary scan path (the DO to T DI connections between components in IEEE Std ) and to the TMS signals, it can accurately diagnose many simple problems (shorts between the boundary scan path and nodes with tester access) which could confuse the rest of the tests [6]. BOUNDARY SCAN INTEGRITY TEST The next part of the test checks that the boundary scan circuitry is working well enough for its results to be useful in the rest of the test. The faults we want to detect at this stage are those where the testability circuitry within components is not working, or where the scan path is broken or shorted. IEEE Std contains a useful facility to assist checking out the testability circuitry: whenever a new instruction is loaded, the value captured in the CAPTURE-IR state and shifted out along the scan path starts off with a 1 sequence. A simple broken connection on the scan path then appears as a constant 1 1, a short to ground as. The simplest form of integrity test consists of loading the BYPASS instruction into each component, and observing the value captured during the CAPTURE-IR state at as many points on the boundary scan path as are available, while also verifying that the points on the boundary scan path are inactive whenever they should be. A pattern of 111, which includes all transitions between logic values, can then be flushed through the BYPASS registers of all the components. If the tester has access to the signals along the scan path, checking that the TDO signals are inactive whenever they should be is a useful mechanism to detect a TDO signal that is shorted to somewhere with no tester access. Unfortunately if such a problem is detected, it can be hard to identify what the scan path node is shorted to, because we cannot then rely on the testability circuitry. Many more tests can be performed on the testability circuitry, such as using SAMPLE to check that the path through the boundary scan register is also operating correctly, and using IDCODE and USERCODE, where these are implemented, to verify that the correct components are on the board. INTERACTIONS TEST This stage of the test looks for shorts between the boundary scan nodes and other digital nodes with tester access, and for opens between a tester nail and any boundary scan input pins on the node. The basic idea of this part of the test is to use EXTEST to hold the boundary scan nodes at the value where they can most easily be backdriven (e.g., a logic high for L) and then to see which of 575

5 Boundary Scan Components U2 A B C U3 J \ U4... Nomal Components Disable Input - U5 F 1111 G 1111 H U1 them move when we use the tester backdrive capability to force the opposite value onto some nowboundary scan nodes. Single Test Node The simplest formof this test uses only one testnode at a time. We force a high onto the test node and scan out the responses at bundary scan inputs, then force a low onto the test node and again scan out the responses. If the test node is shorted to a boundary scan node, we see a failure on one of those scan operations. Similarly if the test node has some boundary scan input pins which are open circuit from the node, both scan operations produce the same value at the position corresponding to such an input cell. However, many shorts, between conventional and boundary scan nodes, but not involving the test node cause failures: whenever such a shorted non-boundary scan node has the dominating logic value the boundary scan node will have the wrong value. If we assume that the logic will have such dominating values half the time, then the boundary scan node will produce an incorrect response on half of the scan operations. Because only a few nodes in the non-boundary scan part of the circuit are likely to change value when the test node moves from a high to a low, there is a reasonably low chance that a short to a node other than the test node will cause the boundary scan node to be high when the test node is high and also low when the test node is low. That chance can be reduced even further by changing the test node several times, and diagnosing a short only when a boundary scan node follows the movement exactly. This can be thought of as applying a sequential test vector (identifier) to a non-boundary scan node, while looking at the SRVs at boundary scan pins to see which nodes capture the same identifier. Multiple Test Nodes To give this test reasonable run times, we use several test nodes at once, giving each of them a unique identifier. We then diagnose a short only when a boundary scan node sees one of the identifiers being driven. Each set of values driven at one time constitutes a Parallel Test Vector, just as if the set of test nodes were controllable from boundary scan devices. Although arbitrary choices of the sets of nodes could be used, we normally use the sets of nodes which are inputs to some component which will be tested in-circuit. This is illustrated in Figure 2. Some nodes can only be used as test nodes by choosing a set of component outputs. The chosen component, UI, is provided with normal in-circuit isolation by disabling any components, such as U5, that drive its inputs. This isolation protects the integrity of the test; reduces or eliminates the stress on U5 from backdriving; and uses exactly the same set of tester resources as the eventual in-circuit test of U1. The component, U1, has its input signals backdriven as if they were edge connector inputs 576

6 and the boundary scan input pins are examined using EXTEST. The PTVs to apply at the component inputs are chosen such that all of the node identifiers are unique, and also such that each node identifier contains several transitions in each direction. This reduces, but does not completely eliminate, the possibility that when we drive one node, the value sequence that propagates to a shorted node is exactly the same as the value we drive, leading us to mistakenly diagnose the driven node as shorted. A series of buffers like those shown in Figure 2 is an obvious case which causes this problem to occur. Nodes D and E follow one of the nodes (F) being driven, and so the short between nodes E and J gives the appearance that J is shorted to F. Of course when D and E are used as test nodes in this test sequence, we will also see that nodes D and E appear to be shorted to J; we report that J is shorted to one of F, D or E. The full length identifier is only needed when problems are identified. Any faults that this test diagnoses are detected as soon as each identifier has both a high and a low logic value. By arranging the second PTV to be the inverse of the first, we can stop the test of each set of nodes after two PTVs ifneither of them detects any problems. This test can be run with only a small amount of backdriving stress, because each PTV only has to be applied during the short time around the CAPTURE-DR state. Result Analysis and Diagnosis There are several different cases we need to consider as we analyze the captured responses. When an input boundary scan pin connected to one of the test nodes produces a SRV that is all one logic value, the diagnosis is an open input pin. When a boundary scan node has an SRV that is identical to one of the STVs being applied, it is very likely to be shorted to that node. As well as these clear pieces of diagnosis, there are several less obvious circumstances that can occur. Some of these circumstances need to be remembered in case a later, more precise diagnosis, gives us the cause of the problem. One of the test pins applying the PTVs may produce a drive verify failure. That means that its sensor detected a logic value different from that being driven. When this happens, the node involved has some fault, which we may not be able to identify more closely. A possible cause could be that the test node is shorted to several different boundary scan nodes, and the backdrive cannot overcome the combined current capacity of all of the shorted nodes. Any boundary scan node which gets an unexpected value that is not one of the STVs being applied has some fault, and so must be included in the diagnosis. A boundary scan node which sees a different SRV from any STV being applied is definitely not shorted to any of the non-boundary scan nodes tested in this section. BOUNDARY SCAN NODE INTERCONNECT TEST The final part of our method is an interconnect test that detects shorts between nodes with full or partial boundary scan control and boundary scan or tester observability. We include the edge connector inputs and outputs in this test, since these can be controlled and observed as easily as boundary scan nodes, and use of them would be required for an interconnect test on a purely boundary scan board. This part of the test first uses a set of precalculated patterns to identify groups of nodes which may be shorted. This is followed by a set of adaptively generated patterns that walk a dominant value through such groups. This is very similar to the C-Test Adaptive Algorithm of Jarwala and Yau. Precalculated Pattern Generation When generating these tests we use standard in-circuit isolation algorithms to disable any normal components that drive nodes with partial boundary scan control. In Figure 3, node A is driven by both U 1, a boundary scan component, and U2, a normal one. In order to use U1 to place values onto 577

7 Boundary Scan Parts Fig 3: Disabling Non-Boundary Scan Drivers the node, we must disable U2 by holding its enable, C, at the disable value. The identifiers chosen for the interconnect test ensure that each boundary scan driver on any node is used to provide both a high and low. The facility within the standard to have shared enables between different pins means that the identifiers need to deal with unknown values. It is easy to find configurations where ensuring that one driver is active means that some other node can have no active drivers. The pattern generation also needs to take into account the fact that sometimes there will not be any access point capturing data on a node. This cannot occur if there are any simple input pins on the node, but can when the only sense points are bidirectional pins. Our algorithms for generating these patterns do not attempt to minimize the length of the identifiers, but deal thoroughly with these tricky cases while keeping the identifier length reasonably small. The test generator also separates the generation of PTVs from the generation of the scan protocols needed to apply the PTVs. This separation allows for flexibility in the scan protocol, and is also necessary to ensure that the adaptive patterns can be run once they have been generated. Precalculated Pattern Application The precalculated patterns can be applied to the board in one of two ways: either by loading them into the tester s serial memory facility [7] or by using the language features (import of data) which allow parts of the digital pattem to be computed at run time. Whichever method is used, it is essential to be able to capture all of the response data from the scan path for later analysis by the diagnostic software (export of data). Precalculated Pattern Result Analysis The analysis of the results From this phase requires some care, particularly when the board has nodes with neither boundary scan nor physical access. Such nodes, if shorted to the boundary scan nodes, can cause many identifier bits to be incorrect. This type of analysis is reasonably straightforward to do algorithmically, but very hard to do with conventional fault dictionaries. The number of different faults such a dictionary would need to include is exponential in the number of circuit nodes: any subset could be shorted, and multiple short groups could occur. Fault dictionary search algorithms are also optimized for a reasonably small number of failing test steps over many pins, whereas these tests fail at many steps on, typically, one output pin. The analysis starts by reconstructing the SRVs seen at each access point (tester pin or boundary scan pin) on each node, taking into account the times when the node has an unknown value or when the pin is not capturing any values because of sharing of cells between input and output functions. This analysis is simplified because we already know which boundary scan nodes are shorted to other accessible nodes; but the possibility of shorts to totally inaccessible nodes cannot be ignored. Different SRVs at Different Places The most obvious symptom is when different SRVs are found at the various sense points on a node. This can be caused either by an open circuit fault or by the node having an ambiguous voltage. Ambiguous voltages can have several possible causes, including shorts and open circuit drivers. When one input pin gives a constant SRV, while others give varying values, the obvious implication is that the input pin is open. That interpretation is even more obvious when the other inputs see the expected SRV. When a highly varied set of SRVs is seen on a node, the most likely cause is an ambiguous electrical 57

8 ... I value. If the variation only occurs when one particular driver of a multiply drivennode should be active, then an open on that driver is likely. Identical SRVs Everywhere When the values at all of the sense points on a node are identical but wrong, we know that the node has a fault. There are several possibilities: When the node has already been diagnosed as shorted to a non-boundary scan node, we assume that the short explains the problem. When several different nodes have the same SRV, we assume that they may be shorted and put them into a set to differentiate with adaptive patterns. This set may include a node which has the correct SRV, when aliasing occurs. When a node SRV is constant whenever some driver should be active, but correct at other times, we suspect an open or inactive driver. This fault may also cause the SRV to retain its previous value whenever such a driver should have been active. When a node has an SRV which is all one logic value except when one driver ought to be active, and is correct when that driver should be active, we suspect a permanently enabled driver. When the node has a unique but wrong SRV which does not look like a driver fault, we suspect a short to an inaccessible node. Adaptive Pattern Generation and Analysis The analysis of the results from the precalculated patterns may produce several sets of possibly shorted boundary scan nodes. Because it is hard to predict exactly how shorts will behave electrically, particularly when they involve more than two nodes, we assume that they could be shorted in any combinations and generate a set of adaptive patterns to attempt to differentiate them, while avoiding the use of drivers which are suspected of having problems. The adaptive patterns are constructed by using a walking dominant value pattern on each of the groups, as this is the simplest pattern guaranteed to show when nodes are not shorted together. Shorts to non boundary scan nodes invalidate the proof of that guarantee, but this still does a lot to disambiguate the possible shorted groups. When there is any doubt about which value will dominate, we use both. The adaptive patterns are not available during the test preparation activities, and so the data import mechanisms are used to apply them. The analysis of the adaptive patterns is essentially the analysis of the precalculated patterns, except that we use the SRVs from the combined sequence. The additional information we gain can be summarized as: Some nodes, which had identical SRVs before, now have different ones, and so are not shorted to each other. This is the major reason for using the walking pattern. Nodes with identical SRVs for both the adaptive patterns and the precalculated ones are considered to be shorted to each other. An incorrect SRV may be seen on a node which responded correctly before. Such a node is not shorted to any accessible boundary scan node, because it would have produced an incorrect response before; it is not shorted to an accessible non-boundary scan node, because such shorts were discovered in the interaction phase. This is reported as a problem, whose most likely explanation is a short to an inaccessible node. DIAGNOSTIC REPORT GENERATION We have now run all of the parts of the interconnect test, and have been rearranging our database of diagnostic facts and hypotheses as we ran each phase, e.g., when we split up groups of nodes we thought were shorted on discovering that they are not. The database now contains all of the identified problems and the explanations we consider likely or plausible. We finish the test by arranging the remaining data into a form suitable for the user, in particular by 579

9 printing out the highly likely explanations for the symptoms. FAULT COVER This test method is sufficiently complicated that it may be unclear at what stage each fault is detected, and what diagnostic complexities occur for some faults. This section categorizes the various fault types and when they will be detected and diagnosed. Faults Involving Testability Circuitry The scan path integrity test checks the testability circuitry inside each component to ensure that it is usable by the rest of this test, so the interesting testability circiiitry faults are those affecting the test access port signals, and particularly the scan path between components. Open circuits on the TMS, TCK or TDO signals have the effect that TDO is inactive at all times; if TDI is open then the only instructions the component can obey are BYPASS and IDCODE, and the componeni output is always high after the first shift cycle when doing BYPASS. These faulty behaviors are all detected by simple scan path integrity tests, and multiple such problems can be identified if all scan path signals are given tester access. Shorts whichaffect TMS,TCKorTDQTDOsignals are extremely difficult to analyze, particularly if these signals are inaccessible. In that case the best that can be said is that the shorts may be detected by the scan path integrity test. When TMS, TCK and the " DWO signals are accessible by the tester, shorts to any other accessible nodes will be diagnosed precisely by the conventional shorts test. Shorts to inaccessible nodes are almost always detected during the scan path integrity test, but the inaccessible nodes involved are not diagnosed. Open Circuit Faults Open circuit faults are detected when there are several access points, which are normally boundary scan cells, on a node. Open circuit inputs normally see a constant value as the node is driven, either by the tester in the interactions phase or by other components in the boundary scan interconnect phase. Open circuit outputs leave the node undriven when they should be active. The nodes that have only one output driver cause the node to be undriven at all times, and so the sense points see a constant value. Opens or inactive drivers on nodes with multiple drivers cause the node to have a wrong value when the open driver ought to be active, and the node behaves correctly at other times. The PTVs applied in the interconnect phase are calculated to ensure that every driver is activated, and the analysis of failed results from that phase looks for failure symptoms that can be explained by driver failures. Short Circuit Faults Shorts involving testability signals have already been mentioned under testability circuitry faults. Other shorts can be categorized according to whether the nodes involved have boundary scan access, tester access, both or none. Shorts often involve more than two nodes, and the full shorted group may only be identified by putting together the evidence from several of our phases. Shorts between nodes with tester access are identified by the conventional shorts test. Shorts between an accessible node and a boundary scan node cause the interactions phase to identify that the accessible node is shorted to the boundary scan node. In rare cases our method may identify a few incorrect possibilities for either the accessible node or the boundary scan node. Shorts between several boundary scan nodes are detected and diagnosed by the boundary scan interconnec t phase. Shorts between inaccessible nodes and nodes with boundary scan access are very likely to be detected in either the interactions phase or the boundary scan interconnect phase. The boundary scan nodes involved will be identified as having some fault, and there is a possibility of misdiagnosis. Shorts affecting inaccessible nodes will probably not be detected. A short between an inaccessible node and an accessible node may be detected during the interactions test as afault on the accessiblenode. 58

10 ... ALTERNATIVES There are several different alternative methods for these interconnect tests. The two major stages which use the boundary scan facilities can be performed in either order, although reversing the order adds a number of complications to the analysis of the SRV data in the boundary scan interconnect test. These cases are simpler to handle when we already know about shorts between normal and boundary scan nodes. The selection of nodes to test simultaneously in the interactions test can also be made in different ways, for instance by choosing sets of nodes which are outputs of components and can be disabled together. Extra efforts could be made to diagnose shorts between IDI/TDO signals and boundary scan nodes. A plausible mechanism to diagnose such problems is to use the backdrive capability of in-circuit and combinational testers to overcome the short. We could take control at every TDO to TDI point along the scan path, force in an EXTEST instruction plus values for the boundary scan register, and verify whether the point on the scan path follows any identifier we place on a boundary scan node. If so, there is a good chance that we have identified the short. There are many complicated special cases in such an approach. SUMMARY Interconnect testing for boards that mix boundary scan and conventional components can be performed effectively using a four-stage strategy: a conventional shorts test where the tester has access; a scan circuitry integrity test; a fairly conventional boundary scan interconnect test; and a test for shorts between those two areas, which is new. There are a number of complications which mean that the analysis of results needy care, even for the conventional parts of the test, but this strategy can be used to give a precise usable diagnosis of these problems. A circuit is not necessarily testable just because it contains boundary scan parts. The test access port on those components is a potential weak link, and physical access to those signals is necessary to get good diagnosis. In addition, shorts involving nodes with neither physical access nor boundary scan access may be impossible to diagnose accurately, and may not even be detectable repeatably. REFERENCES [I] EEE Standard , Standard Test Access Port and Boundary Scan Archilecture. [2] N. Jarwala and C.W.Yau, A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects, Proceedings, International Test Conference, [3] P.T.Wagner, Interconnect Testing with Boundary Scan, Proceedings, International Test Conference, [4] P.Goel and M.T.McMahon, Electronic Chipin-Place Test, Proceedings, International Test Conference, [SI A.Hassan, J. Rajski, and V.K. Agarwal, Testing and Diagnosis of Interconnects using Boundary Scan Architecture, Proceedings, International Test Conference, [61 K. Parker, Production Board Testing in a Boundary Scan Environment, Proceedings, ATE & Instrumentation West, 199. [7] M.L. Fichtenbaum and G.D, Robinson, Scan Test Architectures for Digital Board Testers, Proceedings, International Test Conference,