Mixed Signal IC Testing. Mixed Signal DFT. IEEE Std 蘇朝琴國立交通大學電機工程學系. Mixed Signal IC Testing. IEEE Std. 1149

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1 ixed Signal DFT IEEE Std. 49 蘇朝琴國立交通大學電機工程學系 ST IEEE std 49 P. IEEE Std. 49 IEEE Std. 49. IEEE Std IEEE Std ST IEEE std 49 P.2

2 IEEE Std. 49. Test ccess Port and Boundary Scan rchitecture The Test Technology Technical Council IEEE Computer Society ST IEEE std 49 P.3 IEEE Std. 49. Overview Circuit Structure Operation ode Test ode Configuration ST IEEE std 49 P.4 2

3 Objectives Standards for board level testing Targets: Chip, Board, odule Interconnects Test: External Interconnect Testing Internal Functional Testing ST IEEE std 49 P.5 IEEE Std. 49 Test Standards IEEE Std. 49. Test ccess Port and Boundary Scan rchitecture IEEE Std Extended Serial Test Interface IEEE Std Direct ccess Testability Interface IEEE Std ixed Signal Test Bus IEEE Std odule Test and aintenance (T) Bus Protocol ST IEEE std 49 P.6 3

4 History - Development 985 JETG 986 VHSIC T 988 JTG JETG: Joint European Test ction Group VHSIC Test & aintenance (T) Bus Structure JTG: Joint Test ction Group ST IEEE std 49 P.7 History - Development 99 IEEE Std IEEE 49.a IEEE 49.b BSDL 995 IEEE IEEE 49.4 ST IEEE std 49 P.8 4

5 IEEE Std. 49. Overview Circuit Structure Operation ode Test ode Configuration ST IEEE std 49 P Basic rchitecture Internal Logic TDI TS ISC R Instruction R Bypass R TP Controller U X TDO TCK ST IEEE std 49 P. 5

6 49. - Hardware Overhead TP Controller Boundary Scan Register Instruction Register isc Register Bypass Register Internal Logic ISC R Instruction R Bypass R TP Ctrl U X ST IEEE std 49 P I/O Overhead TDI: Test Data In TDO: Test Data Out TS: Test ode Select TCK: Test Clock TRST*: Test Reset Internal Logic ISC R Instruction R Bypass R TP Ctrl U X ST IEEE std 49 P.2 6

7 49. Boundary Scan Cell IN BS Internal Logic BS OUT Di Si So U X D D U X Do ST IEEE std 49 P Boundary Scan Cell SOUT DIN SIN U X D D U X Shifter ClockDR UpdateDR ode Select DOUT ST IEEE std 49 P.4 7

8 IEEE Std. 49. Overview Circuit Structure Operation ode Test ode Configuration ST IEEE std 49 P Operation ode Di So BSC Do Di BSC So Do Si Normal Si Scan Di So BSC Do Di So BSC Do Si Capture Si Update ST IEEE std 49 P.6 8

9 49. Normal Operation Di Di Si BSC Si So Do Normal So U X D D Circuit operate at normal mode. U X Shifter ClockDR UpdateDR Select ode Do ST IEEE std 49 P Scan Operation Di Di Si BSC Si So Do Scan So U X D D Shift data into boundary scan chain. U X Shifter ClockDR UpdateDR Select ode Do ST IEEE std 49 P.8 9

10 49. Capture Operation Di Di Si BSC Si So Do Capture So U X D D Capture data into boundary scan cell. U X Shifter ClockDR UpdateDR Select ode Do ST IEEE std 49 P Update Operation Di Di Si BSC Si So Do Update So U X D D Capture data into boundary scan cell. U X Shifter ClockDR UpdateDR Select ode Do ST IEEE std 49 P.2

11 49. Tap Controller States Test-Logic-Reset Run-test/idle Data Register Scan Instruction Register Scan Select-DR-Scan Select-IR-Scan Capture-DR Capture-IR Shift-DR Shift-IR Exit-DR Exit-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR ST IEEE std 49 P.2 States of TP Controller Test_Logic-Reset: normal mode Run_Test/Idle: wait for internal test such as BIST Select_DR-Scan: initiate a data-scan sequence Capture_DR: load test data in parallel Shift_DR: load test data in serial Exit_DR: finish phase shifting of data Pause_DR: temporarily hold the scan operation Exit2_DR: finish phase 2 shifting of data Update_DR: parallel load from shift registers ST IEEE std 49 P.22

12 IEEE Std. 49. Overview Circuit Structure Operation ode Test ode Configuration ST IEEE std 49 P andatory Test ode EXTEST: External interconnect test Sample/Preload: Sample interconnect data Bypass: by pass the unrelated chip ST IEEE std 49 P.24 2

13 49. - Optional Test ode INTEST: Internal Test RUNBIST: Run Built-in self test CLP: Latch to safe mode IDCODE: Get device ID code ST IEEE std 49 P EXTEST ode - Scan Update Capture Scan Chip Chip 2 ST IEEE std 49 P.26 3

14 49. - EXTEST ode -2 Scan Update Capture Scan Chip Chip 2 ST IEEE std 49 P Sample ode Capture Scan ST IEEE std 49 P.28 4

15 49. - Preload ode Scan Update ST IEEE std 49 P INTEST ode Scan Update Exec Capture Scan ST IEEE std 49 P.3 5

16 49. - Bypass ode Bypass Bypass Register : a -bit shift register Bypass skips the boundary cells to reduce scan time. ST IEEE std 49 P.3 IEEE Std. 49. Overview Circuit Structure Operation ode Test ode Configuration ST IEEE std 49 P.32 6

17 49. - Configuration Sin BS Sout BS BS TCK TS BS BS ST IEEE std 49 P Serial Configuration BS BS BS BS Sin TCK TS Sout ST IEEE std 49 P.34 7

18 49. - Star Configuration BS BS BS BS TCK TS S S2 S3 S4 ST IEEE std 49 P Star Configuration BS BS BS BS Sin TCK Sout TS TS2 TS3 TS4 ST IEEE std 49 P.36 8

19 49. - BSDL IEEE Std 49.b Boundary Scan Description Language Purposes: Provide standard description language Simplify design work, synthesis is possible. Promote consistency throughout SIC designers Device manufacturers Test developers TE manufacturers ST IEEE std 49 P Summary Presented the background of 49 Studied boundary scan cell circuit structure Studied cell operation modes. Outlined test modes. Presented the boundary scan configuration. ST IEEE std 49 P.38 9

20 IEEE Std. 49 IEEE Std. 49. IEEE Std IEEE Std ST IEEE std 49 P.39 IEEE Std odule Test and aintenance (T) Bus Protocol The Test Technology Technical Council IEEE Computer Society ST IEEE std 49 P.4 2

21 IEEE Std Circuit Structure Operation Protocol ST IEEE std 49 P.4 IEEE Overview To integrate modules into testable and maintainable systems. Contains two types of control modules. T-Bus aster odule () T-Bus Slave odules Based on IEEE Std 49. ST IEEE std 49 P.42 2

22 IEEE Function odule Test Subsystem Test Subsystem Diagnostics Software and Hardware Development ST IEEE std 49 P.43 IEEE Hierarchy System Bus IEEE Std Backplane Test Bus Sutsystem Test Control Component Level Test Bus Other Components Test-Bus Interface Comp. Test Interf. pplication Logic Boundary Scan Rack or Subsystem Board or odule Component ST IEEE std 49 P.44 22

23 T-Bus / On-Board Buses IEEE Std T Bus Test-Bus Interface NSI/IEEE Std 49. NSI/IEEE Std 49. Other Test Buses ST IEEE std 49 P.45 IEEE T-Bus Signals T-Bus aster T-Bus Slave T-Bus Slave n D SD PR CTL TCK ST IEEE std 49 P.46 23

24 IEEE Signals T-Bus aster T-Bus Slave T-Bus Slave n D: T aster Data (2S) SD: T Slave Data (S2) PR: T Pause Request (S2) CTL: T Control (2S) TCK: T Test Clock (2S) ST IEEE std 49 P.47 IEEE Std Circuit Structure Operation Protocol ST IEEE std 49 P.48 24

25 IEEE essage Format aster odule Packet Slave odule Packet Header Packet Count st -od. Data 2nd -od. Data cknowledge st S-od. Data 2nd S-od. Data nth -od. Data nth S-od. Data ST IEEE std 49 P.49 IEEE essage Format Header Packet SB LSB 8-bit odule ddress Field 7-bit Command Field ck Req Bit Par Bit CK. Packet SB LSB 8-bit odule ddress Field 8-bit odule Status Field Par Bit SB 6 LSB Count Packet 6-bit Packet Count Field Par Bit SB 6 LSB Data Packet 6-bit Data Field Par Bit ST IEEE std 49 P.5 25

26 IEEE essage Transmission Data Packet Data Packet 2 Data Packet 3 ST IEEE std 49 P.5 IEEE Protocol Layers aster essage Layer aster Link Layer Slave essage Layer Slave Link Layer Physical Layer ST IEEE std 49 P.52 26

27 IEEE Protocol Layers aster essage Layer aster Link Layer Slave essage Layer Slave Link Layer Physical Layer essage Layer Specify the syntax for messages. Identify the functions that must be supported. ST IEEE std 49 P.53 IEEE Protocol Layers aster essage Layer aster Link Layer Slave essage Layer Slave Link Layer Physical Layer Link Layer Specify the protocol features that permit error-free transfer. Include serialization, packetization of information, parity generation and checking, and address recognition. ST IEEE std 49 P.54 27

28 IEEE Protocol Layers aster essage Layer aster Link Layer Slave essage Layer Slave Link Layer Physical Layer Physical Layer Specify the physical interconnection which comprise the bus. Include the spec. of mini. requirements regarding physical, electrical, and timing characteristics. ST IEEE std 49 P.55 IEEE T-Bus Extension The basic protocol herein for the T-Bus may be extended to meet the needs of specific applications. The extension may address such areas as Fault tolerant Electrical Characteristics Others that allow the T-Bus to be adapted to user applications. ST IEEE std 49 P.56 28

29 IEEE T-Bus Extension Examples Dual T-Buses (2 sets of 5 wires) Fault Recovery Protocol Backup T-Bus aster to monitor bus traffic. By SE (Society of utomotive Engineers) vionics System Division. ST IEEE std 49 P Summary Presented the circuit structure 49.5 Studied the operation protocol Present the extension ST IEEE std 49 P.58 29

30 IEEE Std. 49 IEEE Std. 49. IEEE Std IEEE Std ST IEEE std 49 P.59 IEEE Std ixed Signal Test Bus ixed Signal Working Group The Test Technology Technical Council IEEE Computer Society ST IEEE std 49 P.6 3

31 IEEE Std Overview Circuit Structure Test ode Test Consideration ST IEEE std 49 P.6 IEEE Overview D D D D D D Target mixed signal Printed Circuit ssembles (PC). Components include: ixed Signal Digital nalog Discrete ST IEEE std 49 P.62 3

32 IEEE Targets D D D D D D For production and field test. Provides test access to component pin from edge connectors. void physical access to the pin by TE via bed of nails. ST IEEE std 49 P.63 IEEE Scope Provide standardized approaches to Interconnect Test Parametric Test Internal Test ST IEEE std 49 P.64 32

33 IEEE Interconnect Test D D D D D D D D D D D D Open Defects Short Defects ST IEEE std 49 P.65 IEEE Parametric Test D D- D D- Simple Interconnect Extended Interconnect ST IEEE std 49 P.66 33

34 IEEE Internal Test D D- nalog nalog nalog Digital ST IEEE std 49 P.67 IEEE rchitecture IC IC2 IC Under Test ICn nalog T B B2 T2 ST IEEE std 49 P.68 34

35 IEEE Std Overview Circuit Structure Test ode Test Consideration ST IEEE std 49 P.69 IEEE rchitecture Digital B D Pins Internal Bus 49. TP TDI TDO TS TCK IC Core B B TBIC TP Controller T T2 nalog B Pins nalog TP ST IEEE std 49 P.7 35

36 IEEE rchitecture IC IC2 IC Under Test ICn nalog T B B2 T2 ST IEEE std 49 P.7 IEEE TBIC Core B B2 TP B B TBIC T T2 T T2 VH VL VTH B B2 Vc Switch ST IEEE std 49 P.72 36

37 IEEE B VTH VH VL VG Core Circuit B B2 B B TBIC Test Control Circuitry TP Controller T T2 CD B B2 T T2 TBIC Pin ST IEEE std 49 P.73 IEEE Differential B B B2 VH VL VG VTH Diff. Port B B2 VH VL ST IEEE std 49 P.74 37

38 ixed Signal rchitecture Digital Inputs B nalog Inputs TDI Digital Core Circuit /D nalog Core Digital Outputs DB nalog Outputs TDO ST IEEE std 49 P.75 IEEE Std Overview Circuit Structure Test ode Test Consideration ST IEEE std 49 P.76 38

39 Interconnect Test Open and Short Test VH VL VTH Chip Chip 2 B B2 B B2 ST IEEE std 49 P Parametric Test pply current and measure voltage. B V T B I C B DUT V I B2 ZD ST IEEE std 49 P.78 39

40 Parametric Test easure impedance of a floating ZD. B V T B I C B2 B V I ZD DUT VG ST IEEE std 49 P Parametric Test Impedance of floating ZD with optional Vg. B V T B I C B2 B V I ZD DUT VG Vg Option with Nonzero Vg ST IEEE std 49 P.8 4

41 Parametric Test pply voltage and measure current. T B I C B ZD B T B I C V ST IEEE std 49 P Parametric Test easure complex interconnect network. P V3 P3 Z P2 Z2 V2 V34 Z3 P4 Vg V ST IEEE std 49 P.82 4

42 High Speed pplications Use buffers for better frequency response Current Buffer Voltage Buffer TBIC VG VL VH VTH B nalog Core B2 B ST IEEE std 49 P Internal Test IC Under Test IC IC2 ICn T T2 ST IEEE std 49 P.84 42

43 IEEE Std Overview Circuit Structure Test ode Test Consideration ST IEEE std 49 P Parasitic Effects The COS switch has relatively high impedance. The stray capacitance, resistance, and inductance are large. B Vdd T B I C B nalog Function Pin V B2 Vss ST IEEE std 49 P.86 43

44 Parametric Test Environment IC Under Test IC IC2 ICn T wire segment T2 ST IEEE std 49 P.87 P odel [Becker 992] X(t) h(t) y(t) Wire segments Wire segments.4.84n Via Pin 2pf Wire.76p 369.7p 5.95p 723.7p 723.7p 5.95p 369.7p.253p.2p.339p 2cm Wire Via Pin Interconnect odeling Wire Segment ST IEEE std 49 P.88 44

45 Zin of Buffers Input impedance change from K to EG Phase(rad) Gain Frequency ST IEEE std 49 P Zout of Buffers Output impedance change from to KΩ Phase(rad) Gain Frequency ST IEEE std 49 P.9 45

46 Parasitic Effects Parasitics: wires, pins, and vias. Parasitics deteriorate signal integrity: bandwidth, phase, and amplitude. Parasitic effects increase test data base complexity. nalog testing becomes space and time variant. ST IEEE std 49 P Summary Presented the overview of 49.4 Presented the circuit structure 49.4 Studied the test modes of 49.4 Presented the test consideration ST IEEE std 49 P.92 46