BOUNDARY-SCAN DFT & LAYOUT PRINCIPLES at BOARD LEVEL

Transcription

1 BOUNDARY-SCAN DFT & LAYOUT PRINCIPLES at BOARD LEVEL Ian Saunders JTAG TECHNOLOGIES B.V. UK Sales & Support Centre Tel: Fax:

2 Design For Test - Component Selection Select IEEE compliant devices where possible take heed of any attribute compliance conformance / warning statement in the BSDL file. Where possible ensure that device silicon has been verified against latest BSDL file some IC vendors state this within BSDL file header. All compliant devices must support the mandatory instruction set of BYPASS SAMPLE/PRELOAD EXTEST it is also highly desirable if the optional instructions HIGHZ and IDCODE are supported. Where possible select in-system configuration devices that are IEEE Std.1532 compliant (in support of concurrent programming). Designers are responsible for the level of DFM and DFT implemented within board designs apply pressure on IC vendors to provide a high level of compliance.

3 Design For Test - Compliance Conformance In the first instance the BSDL file for the Intel StrongArm processor specifies that the signals BATTF and VDDF must be driven to the logic 0 state otherwise the device will go into sleep mode. The second instance is an example of COMPLIANCE_PATTERNS attribute for the Xilinx SPARTAN fpga device which requires the PROGRAM pin to be driven to a logic 1 state in order for the device to function in boundary-scan mode. attribute DESIGN_WARNING of SA1110: entity is -- (ref B.8.18) " 1.IEEE circuits on SA1110 are designed " & " primarily to support testing in off-line module " & " manufacturing environment. The SAMPLE/PRELOAD " & " instruction support is designed primarily for " & " supporting interconnection verification test and not " & " for at-speed samples of pin data. " & " 2.Ensure to drive BATTF and VDDF to logic level 0 else the chip " & " will sleep! "; Attribute COMPLIANCE_PATTERNS of XC2S150_FG456 : entity is "(PROGRAM) (1)";

4 Design For Test - Scan Chain Layout 1 JTAG Test Interface Requirements Ensure that all the JTAG Test Access Port control signals (TCK TMS TRST) are connected in parallel. and are used to daisy chain devices into a single scan chain unless: devices must be contained within a separate chain to be compliant with other third-party debuggers or emulators e.g. DSP s. cpld s may require separate chains for their associated configuration software this is not a problem if devices are IEEE 1532 compliant. it may be easier to segment different logic families e.g. ECL / TTL by using different TAP s. it may be better to partition designs into functional blocks for improved diagnostic resolution and optimised test vector execution. Where possible ensure all boundary-scan TAP signals are accessed via primary board edge connector thus eliminating the need for bed-of-nails probing. Keep boundary-scan signal paths as short as possible avoid unnecessary trace looping specify the routing of the TCK and TMS signals as CRITICAL. It is good design practice to buffer all signals interfacing to the board to ensure signal integrity; particularly TCK and TMS.

5 Design For Test - Scan Chain Layout 2 IC1 IC2 ICN TMS TCK TRST* Vcc 1 TRST TMS TCK TRST* Weak 10K Ohm Pull-ups 22 Ohm series damping res. TMS TCK VPP_E AWR User0 Rdy/Bsy User1 Vcc Ohm in series with 100pF to ground Recommended Header For TAP

6 Recommended TAP Headers 1 TRST Mandatory TMS TCK VPP_E 10 Optional AWR User0 14 Rdy/Bsy User1 Vcc - OUT way shrouded (male) header for UUT is T&B or Tyco /AMP

7 Optimum Signal Routing => nets ideally of equal length and separated by ground plane from TMS and TCK to avoid cross-talk IC3 TCK is a critical path net and must be kept as short as possible. Typical Frequency is in range MHz. Use star configuration if possible. Ditto TMS IC4 IC2 IC5 IC1 IC6 TMS TCK

8 Buffer Broadcast Control Signals TMSTCK If Fan -out Restrictions Require TMS (from tester) TCK (from tester) 74 ABT 244 x x Multiple TCK s to improve fan-out DSP s 1-4 DSP s 5-8 Micro_tck Micro_tms 68 Ohm DSP s pf DSP s 5-8 Board fan-out of control lines TMS and TCK must also be considered a general rule of thumb is if track lengths are fairly short fan out to <10 devices from buffered output is acceptable (TCK is more critical than TMS) If track lengths are fairly long it may be worth considering a fan-out of <4. Note that simulation can assist in determining optimum scan signal layouts if controller I/O specifications are available.

9 Utilise Unused I/O pins As Test Nets CONTROL DATA Unused I/O pin otherwise N/C e.g. CPLD or FPGA BS ADDRESS e.g. DSP or µprocessor TMS TCK OR From DIOS e.g. via fixture nail OE~ BS HI-Z (e.g. of FPGA S) or DIOS Nets To Disable -BS Parts & Avoid Bus Contentions Non

10 Design-for-Test - Physical Bypassing JTAG In-Circuit Requirements It may be pertinent to provide a hard-wired capability to bypass boundary-scan components within the board design with zero ohm resistors. Reasons for this may be that the board design has been physically tracked to interface with boundary-scan components however the release of silicon from IC vendor may not yet support this feature. When BYPASSing device remove resistors and and place resistor BYPASS must be removed to prevent IC1 from receiving an erroneous instruction which may cause unpredictable states and must be removed to prevent contention. Single device Multiple devices BYPASS BYPASS IC1 IC4 IC5 IC6

11 Connect WE_ to AutoWrite Input for Optimised Flash Programming Performance WE PIN 1 Control Output HI-Z WE OE TAP CONNECTOR AWR TMS/TCK/TRST e.g. DSP or µprocessor BS DATA ADDRESS F L A S H Programmable Flash Extract from BSDL file BSR description "125 "125 (BC_2 (BC_2 we0_b_bs we0_b_bs output2 output2 X)" X)" & : : "143 "143 (BC_4 (BC_4 wr_b wr_b input input X)" X)" & "144 "144 (BC_2 (BC_2 wr_b wr_b output3 output Z)" Z)" & "145 "145 (BC_2 (BC_2 * * controlr controlr 1)" 1)" &

12 Design-for-Test - Clock Signals JTAG In-Circuit Requirements Ensure where on-board clocks interfere with boundary-scan testing these clocks can be disabled via boundary-scan cells. Where a clock is required to control devices for boundary-scan testing e.g. synchronous DRAM provide the capability for replacing on-board clock with a test clock via boundary-scan cell. When using this technique check on minimum operation frequency of clock distribution circuit it may require a minimum frequency to synchronise with PLL. VCC VCC 3V3 3V3 OE OUT ICS8701 CLOCK DISTRIBU TION OE OUT 0 1 To BSCAN cells ICS8701 CLOCK DISTRIBU TION

13 Special Considerations for SRAM FPGA s Vcc XILINX SRAM BASED devices XC4K Spartan Virtex PROG ALTERA SRAM BASED devices Flex Apex etc.. nconfig INIT SRAM based FPGA s are often subject to changes in their BSCAN behaviour (capability) at different stages during their configuration / programming sequence - read application notes carefully for full details. Shown above are some basic set-ups to avoid devices entering the configuration phase.

14 Contact JTAG Technologies for DFT Booklet or schematic evaluation.