Programmable Data Plane at Terabit Speeds

Transcription

1 AUGUST 2018 Programmable Data Plane at Terabit Speeds Milad Sharif SOFTWARE ENGINEER

2 PISA: Protocol Independent Switch Architecture

3 PISA Block Diagram Match+Action Stage Memory ALU Programmable Parser Programmable Match-Action Pipeline 3

4 PISA Match-Action Unit Multiple simultaneous lookups and actions can be supported Memory ALU Memory ALU Memory ALU Memory ALU Memory ALU Memory ALU Sequential Execution (Match dependency) Staggered Execution (Action dependency) Parallel Execution (No dependency)

5 Introducing Tofino

6 6.5Tb/s Tofino TM Overview Four Match+Action Pipelines Fully programmable PISA Embodiment Single Shared Packet Buffer 16nm technology Port Configurations SerDes, support 1G, 10G, 25G, 40G, 50G, and 100G ports CPU Interfaces PCIe: Gen3 4/ 2/ 1 Dedicated 100GE port Match+Action Pipeline 0 Match+Action Pipeline 2 + Serial I/O Shared Packet Buffer + TM Match+Action Pipeline 1 Match+Action Pipeline 3 6

7 Tofino Simplified Block Diagram Reset / Clocks PCIe CPU DMA engines Control & configuration Rx s 10/25/40/50/100 Pipeline Egress Pipeline Tx 10/25/40/50/100 pipe 0 Rx s 10/25/40/50/100 Pipeline Egress Pipeline Tx 10/25/40/50/100 pipe 1 Traffic Manager Rx s 10/25/40/50/100 Pipeline Egress Pipeline Tx 10/25/40/50/100 pipe 2 Rx s 10/25/40/50/100 Pipeline Egress Pipeline Tx 10/25/40/50/100 pipe 3 7

8 Fully-Programmable Parser TCAM SRAM Eth. Data State Next state Action IPv4 Protocol== 0x11 IPv6 Protocol== 0x06 Match Field Extract Next state Match Field selection Packet Header Vector UDP TCP Input Shift Register shift control From Output Field Extractor 8

9 Packet Header Vector (PHV) A set of uniform containers that carry the headers and metadata. along the pipeline bit words Fields can be packed into any container or their combination. Packing is decided by PHV Allocation pass in the compiler bit words bit words 32 9

10 Match Action Unit Delay Xbar Key # Operand Data Instr. RAM PHV Match RAM/TCAM Action RAM Instruction Address ALUs: Meters, Statistisc, Stateful

11 Match Action Pipeline Full packet Parser Match Action Unit Match Action Unit Match Action Unit Match Action Unit Deparser

12 Match Action Pipeline Full packet urpf Parser IPv4 ACL Deparser IPv4 IPv6 IPv6 ACL Multiple small tables per stage Large tables spread over multiple stages

13 Unified Match Action Pipeline Combined /Egress Match-Action Pipeline MAU 0 PHV MAU n PHV Buffer Parser Deparser Packet Constructor Queues And Packet Buffers Packet body

14 Unified Match Action Pipeline Egress header Combined /Egress Match-Action Pipeline Egress Packet body MAU 0 PHV MAU n PHV Egress Deparser Egress Deparser Egress Packet Constructor Buffer Parser Deparser Packet Constructor Queues And Packet Buffers Packet body

15 Unified Match Action Pipeline Egress header Combined /Egress Match-Action Pipeline Egress Packet body MAU 0 PHV MAU n PHV Egress Deparser Egress Deparser Egress Packet Constructor Buffer Parser Deparser Packet Constructor Queues And Packet Buffers Recirculation Buffer (Packet Reference, Metadata) Packet body

16 Programming Tofino

17 Tofino Architecture Data plane interfaces Intrinsic Metadata ingress_mac_tstamp ingress timestamp assigned by ucast_egress_port output port Tofino-specific Extern Registers, Counters, Meters, Filters, etc. /// Register extern Register<T, I> { /// Instantiate an array of <size> registers. /// The initial value is undefined. Register(bit<32> size); /// Initialize an array of <size> registers and set /// their value to initial_value. Register(bit<32> size, T initial_value); /// Return the value of register at specified index. T read(in I index); /// Write value to register at specified index. void write(in I index, in T value); }

18 Runtime Configuration User Defined P4 16 Core Library Application Packet Test Framework P4 Architecture Model PSA V1Model Extern Libraries /// Indexed counter with `size independent /// counter values. extern Counter<W, I> { /// Constructor W : width of the counter value. I : width of the counter index. type : counter type. Packet an byte /// counters are supported. Counter(bit<32> size, CounterType_t type); P4 Program Arch. Definition Provided by Barefoot Networks P4 Compiler Fronend Backend P4 Visualization Target-Specific Configuration BF-Runtime info BF-Runtime APIs ASIC driver ASIC Model /// Increment the counter value. index: index of the counter to be /// incremented. void count(in I index); }

19 Multi Pipeline configuration App1.p4 P4 Compiler Pipeline Configuration P4 16 Core Library Extern Libraries Arch. Definition App2.p4 P4 Compiler Pipeline Configuration

20 Thank You Contact Information