Programmable Forwarding Planes at Terabit/s Speeds

Transcription

1 Programmable Forwarding Planes at Terabit/s Speeds Patrick Bosshart HIEF TEHNOLOGY OFFIER, BREFOOT NETWORKS nd the entire Barefoot Networks team Hot hips 30, ugust 21, 2018

2 Barefoot Tofino : Domain Specific Processor for Networking Signal Processing Graphics Machine Learning Networking Matlab ompiler OpenL ompiler TensorFlow ompiler >>> P4 ompiler DSP GPU TPU Tofino 2

3 Performance Penalty for Programmable Packet Processing PU - 100x Network Processor - 10x FPG - 10x These ratios have been constant for many years 3

4 Introduction to Tofino Basics of switching Programmable switching Tofino details pplications Presentation Outline What is the processing paradigm for programmable switches? How does Tofino process packets? How does it avoid a performance penalty? What can you do with its programmability? 4

5 Barefoot Tofino - Overview 6.5Tb/s switch 260 lanes of 25G SerDes 260 x 25G Ethernet ports, 130 x 50G, 65 x 100G, or combinations 11B transistors 16nm technology 1250 MHz Equivalent in area and power to fixed function chips Match+ction Pipeline 0 Match+ction Pipeline 2 M + Serial I/O Shared Packet Buffer & TM Match+ction Pipeline 1 Match+ction Pipeline 3 5

6 Barefoot Tofino Block Diagram Reset / locks PIe PU M DM engines ontrol & configuration Rx SerDes Rx Ms 10/25/40/50/100 Ingress Pipeline Egress Pipeline Tx M 10/25/40/50/100 Tx SerDes pipe 0 Rx SerDes Rx SerDes Rx Ms 10/25/40/50/100 Rx Ms 10/25/40/50/100 Ingress Pipeline Ingress Pipeline Traffic Manager Egress Pipeline Egress Pipeline Tx M 10/25/40/50/100 Tx M 10/25/40/50/100 Tx SerDes Tx SerDes pipe 1 pipe 2 Rx SerDes Rx Ms 10/25/40/50/100 Ingress Pipeline Egress Pipeline Tx M 10/25/40/50/100 Tx SerDes pipe 3 6

7 What s in a packet? simple example M IPv4 TP Payload Dest. ddr. Src. ddr. Eth. Type = IPv4 Src. IP Dst. IP IP Proto. Time To Live (TTL) = TP Src. Port Dst. Port Seq. Num. 7

8 Match and ction M Dest. ddr. Packet Header Output M T H T I O N Set Output Port # M T H = T I O N 8

9 Sequence of Match Tables M TBLE IP TBLE L TBLE M T H T I O N M T H T I O N M T H T I O N Exact Match M Dest. ddr. Longest Prefix Match IPv4 Dest. ddr. Ternary Match IPv4 Dest. ddr. TP Src. Port 9

10 Generalizing OpenFlow omponents OpenFlow Generalization Packet Fields Defined standard packet fields User Defined Matching Defined exact and ternary matching on those fields ction Defined actions on those fields - specific, complex Multiple Tables Programming the Forwarding Plane ontrolling the Forwarding Plane Defined sequence of match-action tables Defined PI, e.g. for table, flow entry setup/modification/deletion Same Generalized, simple actions, VLIW with one action per word Same P4 Developed and maintained by P4.org, over 100 members. P4Runtime Developed by Google, Barefoot, ONF and contributed to P4.org 10

11 Define M header header ethernet_t { bit<48> dstddr; bit<48> srcddr; bit<16> ethertype; } Define table matching on M header word table mac { key = { ingress_metadata.bd : exact; l2_metadata.lkp_mac_da : exact; } actions = { dmac_hit; dmac_miss; dmac_redirect_to_cpu; } default_action = dmac_miss; size =M_TBLE_SIZE; } Define table actions action dmac_hit(bit<16> ifindex, bit<16> port_lag_index) { ingress_metadata.egress_ifindex = ifindex; ingress_metadata.egress_port_lag_index = port_lag_index; l2_metadata.same_if_check = l2_metadata.same_if_check, ^ ifindex; } P4 ode Example Open Source Reconfigurable Protocol Independent Target Independent: s/w, FPGs, NIs, fixed and programmable switches Vendor Independent P4 Tutorial at Hot hips 2017 Open Source P4 compiler -> P4 Runtime -> Switch 11

12 Tofino Hardware 12

13 Packet Parsing ETH IPv6 IPv4 packet T M NEXT STTE UDP TP Parser FSM END PKET HEDER VETOR 16 Parsers Per Pipe, Each handles 100G Traffic Header word extract

14 Match-ction Unit (MU) Packet Header Vector in Delay Mux LU Packet Header Vector out X Xbar Match Data # Hash Operand Data Instr. RM Match RM / TM ction RM Instruction ddress SRM / TM RRYS LUs: Meters, Statistics, Stateful 14

15 Table graph mapping to Match-ction Stages L urpf IPv6 L IPv4 Multiple small tables per stage Large tables spread over multiple stages 15

16 Table Predication => SKIP SKIP <= B Multiple tables per stage Each table produces next-table pointer Predication invalidates skipped tables D B D Table Graph Short Forward Branches 16

17 Dependencies and Pipelining STGE L urpf Different Stages IPv6 M Dest. Modification reates Match Data Dependency L IPv4 STGE oncurrent Execution Pipelining Sequential 17

18 How did we get the programmability without the penalty? Didn't use von Neuman processing model ompiler and compiler friendly design Regular architecture: more replication allows better optimization MU area divided into RM arrays + support logic + standard switch features Programmable portion Programmable portion area about 10% of chip area Power is less than the comparable fixed function switches 18

19 spects of switch performance PU, Network Processor performance Use run-to-completion model Throughput dependent on program Hardware switch performance Deterministic Requires assured throughput at 100% traffic, all inputs Most important switch parameters TM packet data ram size Match table ram size Many specific behaviors required Multicast, queue prioritization, WRED, PF, 19

20 pplications Switching pplications: Table and Feature scaling Inband Network Telemetry: (INT P4.org) Data added to packet on each hop - which switch, time spent there, Data collected on exit nswers question: if I'm delayed, who delayed me? Bloom filters, heavy hitter detection omputational Networking pplications: Layer 4 load balancer (SilkRoad: Sigcomm 2017) Replaces ~500 PUs 500x lower latency DDOS protection DNS cache Key-Value store cache (Netache: SOSP 2017) ML parameter server 20

21 Summary Switching is going programmable Tofino achieved no performance penalty vs fixed function switches P4 enables users to build their network their way Opens up wire-speed processing to the networking software industry 21

22 Thank You! 22