Implement IEEE 1588v2 on QorIQ Communications Platforms

Transcription

1 Implement IEEE 1588v2 on QorIQ Communications Platforms FTF-NET-F0071 Xie Xiaobo Software Engineer A P R TM External Use

2 Agenda Introduction of IEEE1588 Basics of Precision Time Protocol Hardware: IEEE 1588 hardware assist block Software: Device driver and application Test setup and results Summary References External Use 1

3 IEEE 1588 Introduction External Use 2

4 What is the IEEE Std 1588? IEEE Std 1588 Standard for a precision clock synchronization protocol for networked measurement and control The standard defines a Precision Time Protocol (PTP) designed to synchronize real-time clocks in a distributed system Intended for local area networks Targeted accuracy of microsecond to sub-microsecond with easy configuration and fast convergence between components IEEE Std (Version 1) approved September 2002 and published November 2002 IEEE Std (Version 2) approved March 2008 and published August 2008 Available from the IEEE 1588 web site ( External Use 3

5 Protocol Comparison Target Uses NTP GPS TTP IEEE Std 1588 Autonomous systems dispersed over a wide area. Time information passed via messages on the Internet. Autonomous systems dispersed over a wide area. Time information passed via satellite. Tightly integrated, closed systems usually connected via a bus or specialized TDMA network Groups of relatively stable components, locally networked (a few subnets), cooperating on a set of well defined tasks Target Accuracy under 1ms possible, 1-10ms typical in LAN, <100ms over the Internet Sub microsecond Sub microsecond Sub microsecond (± 50ns typ) Synchronization Resolution Time Minutes to hours < Minute Resource Requirements Moderate network and compute footprint Moderate compute footprint Moderate compute footprint Small network and compute footprint Latency Correction Yes Yes Configured Yes Update Interval Variable, but normally seconds Approximately every second Milliseconds Approximately every 2 seconds Hardware Required No Yes Yes Yes, to achieve greatest accuracy External Use 4

6 Major motivation for version 2 New application areas with new requirements: Telecom, IEEE 802.1as, power industry. New requirements in original applications Higher accuracy Varied update rates Linear topology (in addition to hierarchical) Rapid reconfiguration after network changes Fault tolerance External Use 5

7 Main differences between V1 & V2 Shorter synchronization frames to save network bandwidth. Transparent clocks to avoid exponential error propagation in cascaded networks. End-to-End and Peer-to-Peer TC. Wider choice of Sync (timing) and Announce (M-S hierarchy) update rates. Profiles to accommodate different market requirements. External Use 6

8 IEEE 1588 Precision Time Protocol Basics External Use 7

9 IEEE Std 1588 Synchronization Message Sequence External Use 8

10 IEEE Std 1588 PTP Non-Management Message Types SYNC messages Master sends an estimate of the sending time When received by a slave clock, the receipt time is noted FOLLOW_UP Messages Always associated with the preceding Sync message Contain the precise sending time of SYNC message measured close to the physical layer of the network DELAY_REQ messages Issued by clock nodes in the Slave state When received by the master clock the receipt time is noted DELAY_RESP Messages Always associated with a preceding Delay_Req message from a specific slave clock Contain the receipt time of the associated Delay_Req message External Use 9

11 Protocol Stack Delay Problem Master Clock Slave Clock Milliseconds of delay and variation introduced by protocol stack PTP UDP IP MAC PTP UDP IP MAC Milliseconds of delay and variation introduced by protocol stack PHY Network PHY IEEE Std 1588 PTP Code Network protocol stack & OS Hardware time-stamping removes protocol stack delay Timestamp generation / message detection PHY MII / GMII External Use 10

12 Boundary Clock Master Clock Switch / Router with Boundary Clock (Slave) (Master) Slave Clock PTP PTP PTP PTP UDP UDP UDP UDP IP IP IP IP MAC MAC MAC MAC PHY Network 1 PHY PHY Network 2 PHY Synchronization across multiple network/subnets External Use 11

13 Peer-To-Peer Transparent Clock Forwards and Corrects Sync and Follow Up messages only. Correction achieved by addition of bridge residence time plus the peer to peer link delay into a Correction filed within the header of message. Need insert a picture for TC External Use 12

14 IEEE 1588 Hardware Assist Timer logic External Use 13

15 IEEE 1588 Hardware Assist Clock Software Time-Stamp External Clock Ref Platform Clock Ref RTC Clock Bypass Enable 32-bit Accum Carry Nominal Clock 64-bit Counter TMR_CNTH/L etsec Tx Clock + 32-bit Addend Tip ADDEND is modified to fine tune the slave clock + TCLK_PERIOD Tip TMR_CNTL/H are modified when difference between master and slave is huge External Use 14

16 IEEE Std 1588 Hardware Assist Clock Phase/Frequency Adjustment Four choices of input clock Addend and accumulator provides a digital fractional divider Provision for bypassing the divider logic ADDEND = 2 32 FreqDivRatio If input clock = 150MHz & desired nominal clock = 100MHz ADDEND = 2 32 (150/100) = 0xAAAA_AAAA External Clock Ref Platform Clock Ref RTC Clock Bypass Enable 32-bit Accum Carry Nominal Clock 64-bit Counter TMR_CNTH/L etsec Tx Clock bit Addend TCLK_PERIOD External Use 15

17 Selection of ADDEND and TCLK_PERIOD The 64-bit counter increments by TCLK_PERIOD on every pulse of nominal clock To represent time in nanoseconds, TCLK_PERIOD should be equal to reciprocal of frequency of nominal clock It is recommended to have TCLK_PERIOD as integral factor of 109 Example: Few integral factors of 109 : 2, 4, 8, 10, 16, 20 For Input clock = 333MHz, recommended choices for nominal clock are 100MHz, 125MHz, 200MHz and 250MHz External Clock Ref Platform Clock Ref RTC Clock Bypass Enable 32-bit Accum Carry Nominal Clock 64-bit Counter TMR_CNTH/L etsec Tx Clock + + TCLK_PERIOD 32-bit Addend External Use 16

18 Working Example of ADDEND Example assumes the accumulator overflows after 9, therefore ADDEND= 9 / (150/100) = 6 The resultant clock may not have 50% duty cycle or uniform period Input Clock = 150MHz Addend = 9 / 1.5 = Carry after 9 Accumulator 6 Nominal Clock = 100MHz External Use 17

19 Using External VCXO Clock Systems which require to synchronize an external clock may choose to bypass internal fine-tuning The counter runs on the input clock SPI or IIC can be used to fine-tune VCXO Tip External clock needs to be tuned VCXO DAC External Clock Ref Platform Clock Ref RTC Clock etsec Tx Clock Bypass Enable Accum + Addend Carry Nominal Clock Counter TMR_CNTH/L + TCLK_PERIOD IIC/SPI External Use 18

20 Timer Extensions Prescaler GCLK TCLK_PERIOD 32-bit FIPER PULSE_OUTn 64 bit ALARM ALARM_OUTn External Clock Ref Platform Clock Ref RTC Clock Bypass Enable 32-bit Accum Carry Nominal Clock 64-bit Counter TMR_CNTH/L etsec Tx Clock bit Addend TCLK_PERIOD External Use 19

21 Timer Extensions (continued) ALARM_OUT is generated when counter is equal to or greater than ALARM can be used to trigger the periodic pulse generator With FIPER as the initial value, a downcounter decrements by TCLK_PERIOD on every pulse of nominal clock A pulse is generated when the down counter reaches zero or less than TCLK_PERIOD Generates periodic pulse with a width of one period of the pre-scaled output clock Down counter is reloaded; the process repeats GCLK outputs pre-scaled output clock Nominal Clock Prescaler TCLK_PERIOD 32-bit FIPER 64 bit ALARM 64-bit Counter TMR_CNTH/L + GCLK PULSE_OUTn ALARM_OUTn TCLK_PERIOD External Use 20

22 Synchronizing PULSE_OUT with TMR_CNT FIPER should be programmed to an integer multiple of TCLK_PERIOD value to ensure a period pulse being generated correctly To generate PPS signal: FIPER = <109 nanoseconds> - TCLK_PERIOD To align PPS signal with TMR_CNT: Program ALARM to a value which is a whole number of seconds, and greater than the present TMR_CNT ALARM = (floor{(tmr_cnt/109) + n})*109 Example: For TMR_CNT = 5.3s and n=2, ALARM = 7s Set TMR_CTRL[FS] to trigger FIPER by ALARM Nominal Clock TCLK_PERIOD 32-bit FIPER 64 bit ALARM 64-bit Counter TMR_CNTH/L + TCLK_PERIOD PULSE_OUTn ALARM_OUTn Tip Only ALARM1 can trigger FIPER1. External Use 21

23 FIPER Re-Alignment Upon Changing TMR_CNT Should user need to change the value of TMR_CNT, the following procedure should be followed to realign the PPS signal: Calculate the new value of ALARM Write new values to TMR_CNTL/H Write calculated values to ALARM1L/H Re-write FIPER to reset the down counter Set TMR_CTRL[FS] Nominal Clock TCLK_PERIOD 32-bit FIPER 64 bit ALARM 64-bit Counter TMR_CNTH/L PULSE_OUTn ALARM_OUTn + TCLK_PERIOD External Use 22

24 Accessing Timer Registers TMR_CNT_L should be read first to get correct 64-bit TMR_CNT_H/L counter values Reads from the TMR_CNT_L register copies the entire 64-bit clock time into shadow registers TMR_CNT_L should be written first Contents of the shadow registers are copied into the TMR_CNT_L and TMR_CNT_H registers following a write into the TMR_CNT_H register Writing the TMR_ALARMn_L register deactivates the alarm event Writing the TMR_ALARMn_L followed by the TMR_ALARMn_H register rearms the alarm function with the new compare value Writing new value to FIPER register resets the down counter used in PULSE_OUT generation ATTENTION Above recommendations should be strictly followed. Any violation may result in unpredictable results. External Use 23

25 IEEE 1588 Hardware Assist Time-Stamping logic External Use 24

26 Time-Stamping Logic There are three different time-stamp capture triggers Reception of a packet Transmission of a packet On the positive or negative edge of the external trigger External Use 25

27 Time-Stamping on Ethernet Frame Reception For etsec: On detection of SFD, the value of TMR_CNT_H/L is copied to TMR_RXTS_H/L if RCTRL[TS] in etsec is set to 1 In addition, the time-stamp is inserted into the packet data buffer as padding alignment bytes if TMR_CTRL[RTPE] is set to 1 AND RCTRL[PAL] (receive pad alignment length) is set to a value greater than or equal to 8 etsec indicates reception of PTP packet to CPU CPU reads time-stamp from RxBuffer or TMR_RXTS_H/L External Use 26

28 Time-Stamping on Ethernet Frame Reception For dtsec: When enabled by setting RCTRL[RTSE] in dtsec, every incoming packet will be accompanied with an 8-byte time-stamp The BMI will extract the timestamp and copy it to the timestamp field within the IC. The whole frame together with timestamp is copied into external buffers and FD is enqueued to indicate reception of PTP packet to CPU CPU reads time-stamp from Frame Descriptor External Use 27

29 Time-Stamping while Ethernet Frame Transmission Foe etsec: etsec supports two-step clock The time-stamp of frame being transmitted is stored in registers or frame control buffer The follow-up packet carries the actual time-stamp of previous packet etsec supports selective time-stamping for Tx packets using TxFCB[PTP] In dtsec, setting TCTRL[TTSE] to 1 ensures that all the packets will be time-stamped during transmission The packet ID and time-stamp are stored in the TMR_TXTS1-2_ID and TMR_TXTS1-2_H/L registers External Use 28

30 Time-Stamping in FCB while Ethernet Frame Transmission To get time-stamps of transmit packets on FCB, following requirements should be met: TMR_CTRL[RTPE], TxBD[TOE] and TxFCB[PTP] should be set to 1 A minimum of two TxBDs are used per packet The first points to the start of the 8 byte TxFCB The second points to the start of frame data The TxFCB, and at least the first 16 bytes of the TxPAL, must be located in contiguous memory locations The time-stamp is written to memory location TxBD[Data Buffer Pointer]+ 0x10 External Use 29

31 Time-Stamping while Ethernet Frame Transmission For dtsec: When enabled by setting TCTRL[TTSE], every requested transmit packet will cause the return of a time-stamp value from the dtsec The BMI receives the actual timestamp after the frame is transmitted. In the TX confirmation phase, The BMI writes the timestamp into the timestamp field within the IC of the sent frame and issues DMA request to copy IC portion into external memory dtsec also supports two-step clock External Use 30

32 Time-Stamping on TRIG_IN The polarity of TRIG_IN signal can be chosen using TMR_CTRL[ETEPn] TMR_TEVENT[ETSn] is set if external trigger is received TMR_ETTS1 2_H/L stores the time-stamp Attention P1010 has 16 pairs of TMR_ETTSn_H/L registers External Use 31

33 IEEE 1588 Hardware Assist Interrupts, Registers and Signals External Use 32

34 Share Hardware Assist IEEE 1588 Block Generally QorIQ have more than one etsec/dtsec(s) There is single IEEE1588 block shared among all etsec(s) in a device Every FrameManager has its own instance of 1588 hardware assist block All dtsecs corresponding to an FM share the 1588 hardware assist However, there are some registers and interrupts dedicated per etsec/dtsec Tip Since the common 1588 time-stamping registers exist within the etsec1 memory space, the etsec1 controller must remain enabled in order to use 1588 time-stamping for any Ethernet port. External Use 33

35 Hardware Assist IEEE 1588 Interrupts The Interrupt controller has different interrupt numbers associated with 1588 interrupts of different etsecs Interrupts generated on transmission or reception of Ethernet packet are dedicated per-etsec These interrupts are indicated by TMR_PEVENT Interrupts generated by ALARM, FIPER and external trigger (TRIG_IN) are registered to etsec timer These events are shown by TMR_TEVENT Internal Interrupt Number Interrupt Source 52 etsec timer 53 etsec timer 54 etsec timer External Use 34

36 Hardware Assist IEEE 1588 Registers All the registers of Hardware Assist IEEE 1588 are valid only on etsec1 memory region except registers listed below TMR_TXTS1 2_ID : Transmit Time Stamp Identification Register TMR_TXTS1 2_H/L : Transmit Time Stamp Register TMR_RXTS_H/L : Receive Time Stamp Register TMR_PEVENT: Timer PTP Packet Event Register TMR_PEMASK : Timer Event Mask Register TMR_STAT : Timer Status Register Attention Access to any other register of Hardware Assist IEEE 1588 from memory region other than etsec1 is illegal External Use 35

37 Hardware Assist IEEE 1588 Registers (Cont.) For dtsec: All the registers of Hardware Assist IEEE 1588 are valid on FMan s 1588 timer module memory region except registers listed below which resides in the dtsec s memory region: TMR_CTRL is not the same to the TMR_CTRL register in the 1588 timer module TMR_PEVENT - Time-stamp event register TMR_PEMASK - Timer event mask register Comparing to etsec: No TMR_TXTS1 2_ID Register No TMR_TXTS1 2_H/L Register No TMR_RXTS_H/L Register The BMI get the timestamp to put into the IC timestamp field External Use 36

38 Hardware Assist IEEE 1588 Signals TSEC_1588_CLK_IN: One of the four choices of input clocks TSEC_1588_CLK_OUT: Output of pre-scalar TSEC_1588_TRIG_IN[1:n] : External trigger input TSEC_1588_PULSE_OUT[1:n] : Output of FIPER TSEC_1588_ALARM_OUT[1:n]: Output of ALARM Attention 1. The number of TSEC_1588_TRIG_IN, TSEC_1588_PULSE_OUT and TSEC_1588_ALARM_OUT may vary from device to device 2. There might be some variation in the name of the signal from device to device External Use 37

39 IEEE 1588 Software Device Driver and Application External Use 38

40 Initialization Routine Get the frequency of the input clock Calculate as explained earlier and feed results in ADDEND and TCLK_PERIOD Write desired value to TMR_PRSC and FIPER Calculate and feed ALARM register Set TMR_CTRL[FS] to trigger FIPER with ALARM Choose input clock using TMR_CLK[CKSEL] Start timer by setting TMR_CTRL[TE] to 1 Initialize rest of the registers for time-stamps and interrupts are required External Use 39

41 IXXAT Software Block Diagram The application interacts with the network layer to send/receive PTP messages Using 1588 APIs, the application gets the time-stamps of packets sent or received Based on time-stamps, it decides to tune the clock using 1588 APIs Application Layer Messaging Unit Network Layer Clock Servo Mechanism 1588 Timer APIs Kernel Hardware External Use 40

42 IOCTL command for IXXAT Software GET_RX_TIMESTAMP : To read time-stamp of packet received GET_TX_TIMESTAMP : To read time-stamp of packet transmitted GET_CNT : Read value of TMR_CMT SET_CNT : Write new value of TMR_CNT along with reinitializing FIPER and ALARM ADJ_ADDEND : Write new data to ADDEND GET_ADDEND : Read ADDEND External Use 41

43 Open Source Software Block Diagram The ioctl interface is implemented as socket ioctl. - Command: SIOCSHWTSTAMP The 1588 message transfer by UDP protocol. The Clock PTP driver is character driver External Use 42

44 PTP Clock driver Interface PTP Clock driver register themselves by presenting a 'struct ptp_clock_info' to the registration method - ptp_clock_register(). struct ptp_clock_info ptp_gianfar_caps = { };.owner.name.adjfreq.adjtime.gettime.settime.enable = THIS_MODULE, = "gianfar clock", = ptp_gianfar_adjfreq, = ptp_gianfar_adjtime, = ptp_gianfar_gettime, = ptp_gianfar_settime, = ptp_gianfar_enable, A character device is created for each registered clock. User space can use an open file descriptor from the character device as a POSIX clock id and may call clock_gettime, clock_settime, and clock_adjtime. External Use 43

45 Timestamp Processing in Open Source A shared time stamp structure struct skb_shared_hwtstamps. struct skb_shared_hwtstamps { }; ktime_t hwtstamp; ktime_t syststamp; /* hwtstamp transformed to system time base */ Time stamps for received packets was stored in the skb. Get a pointer to the shared time stamp structure by calling skb_hwtstamps(). Then set the time stamps in the structure skb_shared_hwtstamps. For outgoing packets, skb_hwtstamp_tx() clones the original skb and adds the timestamp to structure skb_shared_hwtstamps. The cloned skb with the send timestamp attached is looped back to the socket's error queue. PTPd get the RX timestamp by calling recvmsg() and the TX timestamp by calling recvmsg(flags=msg_errqueue). External Use 44

46 PTPd Block Diagram External Use 45

47 IEEE 1588 Test Setup and Result External Use 46

48 IEEE 1588 Std Protocol on QorIQ Platform IEEE Std 1588 Master (TWR-P1025) IXXAT/PTPd IEEE Std 1588 application S/W IEEE Std 1588 Slave (TWR-P1025) IXXAT/PTPd IEEE Std 1588 application S/W PTP stack evaluation version - will stop after 4 hours -0, ; 0, ; 0, ; 0, ; 2152; -0, ;-0, ; 0, ; 0, ; 3132; -0, ;-0, ; 0, ; 0, ; 2960; -0, ;-0, ; 0, ; 0, ; 2268; 0, ; 0, ; 0, ;-0, ; 1792; 0, ; 0, ; 0, ;-0, ; 1648; 0, ; 0, ; 0, ;-0, ; 1760; 0, ; 0, ; 0, ;-0, ; 1944; -0, ;-0, ; 0, ;-0, ; 2032; Plot the Offset from Master Raw Data External Use 47

49 IXXAT Application Testing Result External Use 48

50 [nsec] TM PTPd Application Testing Result Time [Sec] External Use 49

51 Summary Using IEEE 1588 Hardware Assist logic, sub-50ns synchronization can be achieved over the network Hardware support for 1588 is available in all the devices of QorIQ family Being used for industrial, telecom and consumer (audio-video sync) applications Synchronized pulses and alarm functionality available in QorIQ family External Use 50

52 References Reference Manuals of QorIQ devices AN3423: Application note on IEEE External Use 51

53 Freescale Semiconductor, Inc. External Use