Optical Interconnection Networks based on Microring Resonators

Transcription

1 Optical Interconnection etwors based on Microring Resonators A Bianco, D Cuda, M Garrich, G Gavilanes, P Giaccone and F eri Dipartimento di Elettronica, Politecnico di Torino, Italy, {lastname}@politoit IEIIT-CR (Italian ational Research Council), Italy, davidecuda@politoit Abstract Optical interconnection networs are gaining interest given the high information densities demanded by applications such as the large-scale switching fabrics employed in future high capacity routers In this context, silicon microring resonators appear as one of the most promising devices to perform switching operations directly in the optical domain However, the peculiar asymmetry of the physical characteristics of microring resonators impose new constraints in the design of interconnection networs In this paper, we first study the properties of classical interconnection architectures when microring resonators are employed as building blocs; then, we propose new microring-based architectures able to achieve large scalability at a reasonable complexity Finally, we introduce a configuration algorithm able to minimize the overall blocing probability I ITRODUCTIO Internet traffic eeps increasing Each new generation of high-capacity routers and switches must process an always increasing amount of data traffic Thus, moving some switching operations from the electronic to the optical domain can be a viable alternative to deeply cut down networ power consumption On the one hand, predictions outlined by the International Technology Roadmap for Semiconductors [5] show that the main performance limitation of feasible on-die electronic interconnects is the length of metal-dielectric wirings, becoming critical for distance above the millimeters Indeed, the higher the information densities that switches and routers have to support, the stricter become the design constraints to be fulfilled, especially in terms of electromagnetic compatibility issues, maximum distances which electronic signals can cover without regeneration and power requirements On the other hand, recent breathroughs in CMOS-compatible silicon photonic integration are boosting the penetration of optical technologies into interconnection systems [] [4] As a matter of fact, photonic technologies can transport huge information densities, their performances are, at a first approximation, independent of the bitrate and offer the possibility to cover larger distances without regeneration We present here new solutions for large integrated optical switching fabrics which can be used to interconnect router/switch linecards Silicon microring resonators represent one of the most promising optical devices to this end Microring resonators are small foot-print devices, which have already proved to be suited for a wide range of applications, including signal processing, filtering, delaying or modulating optical signals In addition, they have been considered also to build sensors, modulators, microlasers, memories and slowlight elements [6] We are interested in the use of microring resonators as switching devices, as proposed in [3], [4], [7] In this context, we propose new interconnection architectures using microring resonators as optical Switching Elements (SEs) In a microring resonator SE (see Fig (a)), an incoming optical signal can be either coupled to the ring (if the input signal wavelength is equal to the resonance wavelength of the microring) or it can continue along its path (if the input signal wavelength is different from the resonance wavelength) Microring resonators show intrinsic asymmetric power penalties, because optical signals traveling across the ring suffer larger power penalties than the signals that are not coupled into the ring [8] In classical interconnection networs (both electronic and photonic), input signals usually present power losses that are independent of the state of the interconnection networs On the contrary in microring-based interconnection networs, it is crucial to minimize the number of times an input signal is coupled into a ring while traveling through the interconnection networ, since it penalizes the signal as it propagates to the corresponding output Hence, to maximize scalability, we propose different architecture designs and a suitable control algorithm able to cope with microring physical impairments In Sec II, we first describe simple SEs based on microring resonators that can be used as building blocs to create interconnection networs In Sec III, we investigate scalability in terms of cost and performance of three classical networs based on microring SEs To optimize the trade-off between cost and performance, we also propose two new multistage networs in Sec IV and the mirroring technique in Sec V In Sec VI we present a variation of the classical Paull s algorithm for Clos networs [9], that configures microringbased switching fabrics and drastically reduces the probability of occurrence of highly impaired states in the switching fabric Finally, we present some design evaluation of the proposed solutions in Sec VII, and we draw some conclusions in Sec VIII II MICRORIG-BASED SWITCHIG ELEMETS Microring resonators are basically composed by a waveguide bent to itself in a circular shape, coupled to one or two waveguides or to another microring Fig (a) shows an example of a microring coupled to two waveguides to build a SE This basic building bloc is called B-SE Optical

2 signals entering the input port can be deflected to the drop port, when the ring is properly tuned (or in resonance) with the input signal wavelength, or just continue along the input waveguide towards the through port in the normal untuned state Experimental measurements [] show that the B-SE presents an asymmetric behavior In that particular case, for microrings controlled through laser pumps, input signals sent to the drop port experience larger power losses (around 5 db) than signals routed to the through port (low enough to be negligible) because of the propagation inside the ring and the ring-waveguide coupling Regarding the crosstal, the same study shows that the extinction ratios are different for through and drop ports; so the interfering signals present in output ports due to power leaages are different in both states; this leads to an unbalanced coherent crosstal accumulation when several SEs are cascaded, as it happens in large-scale interconnection networs In switching applications, microring resonators must be tuned to change their switching state Indeed, it is possible to change the microring effective refractive index (and hence their resonance frequency) exploiting thermal-optic [], carrier injection [] effects, or by means of optical pumps [] Depending on the technology used, different tuning times, as well as different power penalties, can be observed In the remainder of the paper, we assume that microrings are controlled by carrier injection techniques because they ensure (fast) switching times of few hundred ps [] We also assume a single wavelength operation; the incoming optical signal is either coupled or not to the ring depending on the wavelength to which the ring is tuned to All the proposed architectures can be extended to a Wavelength Division Multiplexing (WDM) scenario, assuming to use the wavelength striping technique, and that the WDM channel comb fits exactly the period of the microring transfer function A physical model of microrings, as the one presented in [4], is outside the scope of this wor Here, we simply assume that the B-SE can be either in a High-Loss State (HLS), or in a Low-Loss State (LLS) Indeed, we wish to study interconnection networ architectures able to scale to large sizes by reducing the number of SEs in HLS that optical signals should cross while moving from input to output ports Building up on the B-SE structure, it is possible to design more complex SEs that can be used as building elements in interconnection architectures Fig (b) depicts a possible implementation of a basic SE (called B-SE) The B-SE exploits two B-SEs jointly controlled to provide two switching states In the bar state (in out, in out ), each ring deflects the corresponding optical input signal to the drop port of the respective B-SE In the cross state (in out, in out ), each ring lets the corresponding optical input signal pass to the through port of the respective B- SE Hence, also the B-SE exhibits an asymmetric behavior, because the bar state is a HLS, and the cross state is LLS with negligible power losses, as also experimentally measured in [7] Finally, we propose a modified version of the B-SE, useful P in Ring Through Port Drop Port Through Port (a) Basic SE (B- SE) Fig in out Ring in out Ring (b) Basic SE (B-SE) in in Ring Ring out out (c) Mirrored SE (M- SE) Elementary microring-based switching elements to optimize the design of multistage interconnection networs Fig (c) shows a Mirrored-SE (called M-SE); By crossconnecting input ports, the bar state is now realized by setting up the internal SE in the cross state (LLS), whereas the cross state is achieved with an internal bar state (HLS) III BASIC MULTISTAGE ARCHITECTURES The SEs presented in Sec II can be used as building elements to assemble a larger interconnection networ with input and output ports The networ must be configured to support a given set of input-output pairs defined by a permutation π: input i must be connected to output π(i) When we say that a connection from i to π(i) must be established, we mean that a pacet from input i must be transferred to output π(j) according to the decision of an external pacet scheduler The sequence of SEs traversed by the connection, defines a path in the switching networ ote that we borrow some terminology from the circuit-switching domain, but our scenario is pacet switching We aim at maximizing the scalability for large switching fabrics in terms of cost (ie, the number of used microrings) and performance The cost, denoted by C, is evaluated with the total number of microrings present in the networ The performance is evaluated through the maximum number of SEs configured in HLS that the input signal must cross in the optical interconnection, considering all possible input-output permutations Such number is denoted by X and referred as the power penalty index The best scalability is achieved by minimizing both C and X for a given We will consider a networ design constrained by a given maximum power penalty index ˆX, equal to the maximum number of HLS SEs that optical signals are allowed to cross Whenever X ˆX, then all the possible input-output permutations can be established On the contrary, when X > ˆX, there will exist some permutations for which some input-output connections cannot be established, since the corresponding path would violate the target ˆX; in such a case, the connection is said to be bloced, and the corresponding pacet will not be sent across the switching fabric A Crossbar networs based on microring resonators Firstly, we discuss the properties of the crossbar (XBAR) architecture, which will be used also as basic building bloc for the new architectures that will be later proposed Crossbars can be built exploiting B-SEs: Fig shows an example of

3 i input stage a b n middle (switching) stage j output stage Fig 4 4 microring-based crossbar connecting 4,, 3 and 4 3 crossbar, in which column waveguides are attached to the input ports and row waveguides to the outputs The crossbar exhibits the best performance scalability, because each input can be connected to any output crossing a single B-SE in HLS Hence, the maximum number of SEs in HLS that any optical signal crosses is X XBAR () = However, the crossbar exhibits the worst scalability in terms of cost, since C XBAR () = As a consequence, the crossbar requires a large footprint, and a large number of SEs must be controlled, although via a simple routing algorithm The definition of non-blocing networs less costly than the crossbar, naturally leads to multistage interconnects; we consider Clos networs and Benes networs, and we later introduce some variations to these architectures to achieve the best scalability in terms of cost and performance B Clos networs based on microring resonators Clos networs [9] are well-nown multistage interconnection networs, whose cost scalability is better than the one of the crossbar Fig 3 shows a symmetric three-stage Clos networ: each SE of the first stage and of the third stage is connected with all the SEs of the middle stage The first design parameter is the number of SEs in the first and the third stage, denoted by The second design parameter is the number of SEs in the second stage, affecting the blocing property In the following, we consider n = / SEs in the middle stage since this is the minimum n that guarantees a non-blocing rearrangeable networ As a consequence, the first and third stage SEs are of size n n, and the second stage of SEs are of size When all SEs are implemented by crossbars, X CLOS = 3 and the minimum networ cost, obtained for n = /, is equal to C CLOS () = 3 C Benes networs based on microring resonators Benes networs are Clos networs that are recursively constructed with basic SEs of size ; it must hold = h for some integer h From the cost point of view, they offer the best scalability, being asymptotically optimal [9] In general, an Benes networ has a number of stages (columns Fig 3 Rearrangeable non-blocing Clos networ TABLE I COMPARISO BETWEE DIFFERET ETWORK ARCHITECTURES, HAVIG DEFIED ˆ = ( ˆX )/ etwor Cost Power penalty Crossbar ˆX Clos 3 3 ˆX Benes log log ˆX M-Benes 4 log log ˆX HCB /ˆ + ( ˆX ) 3 ˆX log M-HCB 4 /ˆ + ( ˆX 3) 3 ˆX log HBC /ˆ + ( ˆX ) ˆX log M-HBC 4 /ˆ + ( ˆX ) 3 ˆX log + of B-SEs) equal to log, each stage including / basic B-SEs Hence, the cost scales as C BEES () = log () because each SE includes rings In terms of performance, X BEES () = log () since in the worst case there exists a path that passes through a HLS SE in each stage Hence, Benes networs show a poor performance scalability, since X BEES grows with the size ; given a maximum value ˆX for the power penalty index, it is impossible to build networs with size > ( ˆX+)/ IV HYBRID MULTISTAGE ARCHITECTURES The upper part of Table I provides a synoptic overview of the cost and the performance for the basic architectures To improve scalability for large, we now combine the Clos networ architecture (based on simple crossbar with good performance scalability) with the Benes networ (with optimal cost scalability), considering two possible variants: i) the Hybrid Crossbar-Benes networ and ii) the Hybrid Benes- Crossbar networ A The Hybrid Crossbar-Benes (HCB) architecture The HCB networ is depicted in Fig 4 and it consists of a Clos networ in which the middle-stage modules are implemented through Benes networs, instead of crossbars Lie

4 crossbar Benes crossbar h h crossbars n Fig 4 Hybrid Crossbar-Benes (HCB) networ Fig 5 Hybrid Benes-Crossbar (HBC) networ the original Clos networ, the HCB networ is constrained to = n, being n the size of the crossbars, and = h the size of the Benes networs for some integer h Clearly, from the cost perspective, the best solution is to mae the Benes networ as large as possible, up to = /, when the HCB networ degenerates into a Benes networ On the contrary, from the performance perspective, since X HCB = log (/n) + (3) we must increase the crossbar size n Thus, given a target ˆX 3, it must satisfy X HCB ˆX and n /ˆ, having defined ˆ = ( ˆX )/ The value n = /ˆ ensures both feasibility and minimum cost Finally, C HCB (, ˆX) = ˆC XBAR (n) + nc BEES (ˆ) = ˆ + ( log ˆ ) = ˆ + ( ˆX ) = ( ˆX 3)/ + ( ˆX ) (4) for 3 ˆX log ote that (4) is lower than a crossbar for ( ˆX )/( ( ˆX 3)/ ) B The Hybrid Benes-Crossbar (HBC) architecture The HBC networ is depicted in Fig 5 (with = n h ) and it consists of a Benes networ factorized until a certain level h, when the middle stage is substituted by = h crossbars of size n Again, from the cost perspective, we must increase the Benes part up to = / when the HBC degenerates into a Benes networ However, from the performance point of view, since X HBC = h + = log (/n) + (5) the best solution is to decrease the level of factorization h (up to h = when the HBC degenerates into a crossbar) Thus, to satisfy a given target ˆX, it must be XHBC ˆX and n /ˆ, having defined ˆ = ĥ and ĥ = ( ˆX )/ The value n = /ˆ ensures both feasibility and minimum cost ow the HBC cost scales as: C HBC (, ˆX) = ˆC XBAR (n) + (ĥ)(/) = ˆ + ( ˆX ) = ( ˆX )/ + ( ˆX ) (6) for ˆX log ote that (6) is asymptotically half the cost of the HCB and it shows a complexity lower than a crossbar for ( ˆX )/( ( ˆX )/ ) V MIRRORED ARCHITECTURES To further improve the scalability of multistage networs, ie, either to reduce the power penalty index X or to achieve larger for a given maximum power penalty index ˆX, we propose the mirroring technique that exploits the spatial dimension, as shown in Fig 6(a) We use two different switching planes, topologically identical: the normal plane is built with B-SEs only, whereas the mirrored plane with M-SEs only Depending on the architecture, all inputs are connected to both planes by means of either: (i) the B-SE (Fig (a)) which implicitly introduces a power penalty asymmetry to the signal between both planes, or (ii) the plane selector depicted in Fig 6(b), which introduces a constant power penalty to both planes, or (iii), when possible, integrating the selector with an extension of the first stage of the architecture However, each output merges passively the information from both planes by means of a coupler, which introduces a negligible performance impairment with respect to the plane selector Since a HLS SE configuration in one plane corresponds to a LLS one in the other plane, all input/output connections that would cross X B-SEs in HLS in the normal plane can be routed on the mirrored plane along the same path, crossing (S X) M-SEs in HLS, where S is the total number of traversed SEs in each plane; whenever X > S/, the routing algorithm will choose the path along the mirrored plane, with lower power penalty As a consequence, we can start from a plane characterized by a power penalty index X

5 Inputs ormal plane Mirrored plane (a) Mirrored architecture Fig 6 Outputs in i Mirrored architecture and plane selector ormal plane out Mirrored plane out (b) Plane selector and build the whole networ with power penalty index: X M = X/ + X S (7) where X S is the power penalty introduced by the selector; as a consequence, the power penalty is roughly halved by doubling the cost of the Benes part of the networ, constituted only by SEs (ie, doubling the number of SEs) This allows to scale the size of the networ given the same ˆX, as shown below for each architecture From the routing point of view, computing the path in the mirrored architecture has the same complexity as computing it for just a single plane, since the corresponding SE states in normal and mirrored plane are identical ote that mirroring the crossbars (based on B-SEs) does not provide any advantage in terms of power penalty Two possible solutions to build the crossbars are possible: (i) the crossbars are replicated in both two planes; (ii) each crossbar is shared between the two planes, by adding one passive coupler at the inputs of each crossbar, and one plane selector at the outputs Solution (i) has the advantage of avoiding additional power penalty, but it introduces the cost of replicating the crossbars On the contrary, solution (ii) shows a larger power penalty, but this is compensated by a smaller cost In the following, we have considered solution (i); solution (ii) is left for future wors In the following, the mirroring technique will be denoted with the prefix M- and it is applied to Benes, HCB and HBC networs A Mirrored Benes networs In the M-Benes networ, a selector is needed and it is either a B-SE or the plane selector of Fig 6(b) On the one hand, the B-SE introduces an asymmetric behavior in terms of power penalty, and maes more complex the layout to connect directly the drop port and the through port to each of the two planes On the other hand, the plane selector adds a constant power penalty of one extra B-SE in HLS to all the signals, but may be simpler to implement due to its layout suited for an homogeneous selection between both planes Therefore, we consider the plane selector for the M-Benes Since the Benes networ presents an odd number of stages, when we build a plane with a maximum power penalty X BEES, from (7) we obtain a M-Benes networ with: X M-BEES = X BEES + = log (8) Let be the maximum size of a Benes networ satisfying ˆX; let us recall (): ˆX = log A mirrored version satisfying ˆX is built with two Benes networs in which the maximum power penalty is relaxed up to ˆX, according to (8) Hence, such Benes networs can have up to ports compatible with ˆX = log By simple algebra, it can be shown that = /, ie the mirroring technique allows to scale the networ by a quadratic factor The final cost is simply obtained by considering the plane selectors and the two Benes networs: C M-BEES () = C BEES () + = 4 log B Mirrored HBC networs The M-HBC networ requires a selector due to the Benes part at the edges of the networ Similarly to the M-Benes networ, we use the plane selector of Fig 6(b) Let X HBC be the maximum power penalty in a single plane HBC networ Due to the even number of Benes stages that compose the HBC networ and the single crossbar stage in the middle, we obtain the following performance for the M-HBC networ: X M-HBC = X HBC + + = log n + (9) Let ˆX be the maximum power penalty satisfied in a HBC networ According to (9), we can build a M-HBC in which the maximum power penalty is relaxed up to ˆX 3 Therefore, recalling that ˆ = ( ˆX )/, the cost scales as: C M-HBC (, ˆX) = C HBC (, ˆX 3) + = 4 ˆ + ( ˆX ) = ˆX 3 + ( ˆX ) () for 3 ˆX log + ote that for high values of, () is convenient with respect to (6) for a power penalty ˆX > 5 C Mirrored HCB networs Differently from the mirrored versions of Benes and HBC networs, it is possible to integrate the plane selector in the first stage crossbar Indeed, in a mirrored HCB networ, the first stage is composed by crossbars of size n n The plane selector is connected to two crossbars (one for each plane) and allows to connect each input port with n output ports (n for each plane) This observation suggests a possible way to integrate n plane selectors and two n n first-stage crossbars with just a a single n (n) crossbar, reducing the cost by and the power penalty by one Let X HCB be the maximum power penalty in a single plane HCB networ Due to the odd number of Benes stages that compose the HCB networ and the crossbars stages at the edges, we obtain the following performance for the M-HCB: X M-HCB = X HCB + = log n + () Let ˆX be the maximum power penalty satisfied in a HCB networ According to (), we can build a M-HCB in

6 which the maximum power penalty is relaxed up to ˆX Therefore, recalling that ˆ = ( ˆX )/, the cost scales as: C M-HCB (, ˆX) = C HCB (, ˆX ) = 4 ˆ + ( ˆX 3) = ˆX 3 + ( ˆX 3) () for 3 ˆX log + ote that for high values of, () is convenient with respect to (4) for a power penalty ˆX > 3 VI POWER-PEALTY-AWARE ROUTIG ALGORITHM In Sec III we have proposed different networ architectures, whose cost and performance have been summarized in Table I Independently of the configuration algorithm, both the crossbars and the Clos networs experience a fixed power penalty: X XBAR = and X CLOS = 3 On the other hand, for all the other networs considered in this paper, the power penalty depends on the path chosen by the routing algorithm to establish the required connections In this section, we show the design of a routing algorithm, aware of HLS and LLS states, that reduces the power penalty Aim of the routing algorithm is to configure the state of each SE to satisfy any given input-output permutation π We consider the well-nown Paull algorithm [9] which has been designed to configure a three-stage Clos networ, but it is also suitable for multi-stage interconnection networs based on recursive Clos construction At each recursion level, the networ is abstracted as an equivalent three stage Clos networ Referring to Fig 3, consider a basic Clos networ with I- stage and III-stage modules of size n n; as a consequence, n modules are present in the II stage The algorithm starts from the networ and from a given permutation π of size, and it computes the configuration of all the + n switching modules to establish all the connections of π Then, if the middle-stage modules are, internally, Clos networs, the Paul algorithm is applied recursively to each individual module to establish all the connections of a permutation π of size computed in the external recursion level Consider now just a basic Clos networ that must be configured according to π The Paull algorithm wors in an incremental way, considering the inputs in an arbitrary order When input x is considered, the algorithm computes the path to connect x to output π(x) by configuring (see Fig 3): (i) the first-stage SE where input x is placed (we denote this as module i ), (ii) the third-stage SE where output π(x) is located (we denote this as module j ), (iii) one or two SEs present in the second stage By construction, exactly one of the two cases can occur: ) there exists a II-stage module a that can be connected to both modules i and j; in this case, II-stage module a is configured to support the connection from its internal input i to its internal output j; I-stage module i is configured to connect input x to its internal output a; III-stage module j is configured to connect its internal input a to π(x); ) otherwise, there exist two II-stage modules a and b, such that a can be connected to module i, and b can be connected to module j; in this case, the algorithm moves a set of pre-existing connections from a to b and viceversa, and recomputes accordingly the configurations of the I- stage modules and III-stage modules; then either a or b is used to support the new connection from x to π(x), similarly to the previous case The Paull algorithm can exploit many degrees of freedom to establish the connections given by π: (i) the sequence of inputs considered by adding the connections in π, (ii) the choice of a and b, (iii) the choice of the paths to be moved from/to a and b Of course, each routing choice affects the power penalty experienced by the paths across the switching fabric We propose to modify the Paull algorithm to exploit such degrees of freedom in choosing a and b, among all the n possible II-stage modules, to minimize the power penalty This modified version of the algorithm will be denoted by PPA- Paull (Power-Penalty-Aware Paull algorithm), in contrast with the classical version denoted simply by Paull In the case n >, the I-stage and III-stage modules are crossbars and the power penalty introduced by them is always two, independently from the choice of the II-stage module Hence, PPA- Paull chooses randomly a II-stage module that is currently available In the case n = (ie B-SEs at the I-stage and III-stage), the power penalty depends on the state of I-stage module i and III-stage module j Let us assume that all the inputs and the outputs of the whole Clos networ are numbered in increasing order starting from and that the II-stage module a is the upper module, whereas b is the lower one When an odd input is connected to an odd output, PPA-Paull will choose (if available) b to configure both B-SEs at the edges in LLS Analogously, when an even input is connected to a even output, a will be chosen Otherwise, either a or b will be chosen at random, since exactly one B-SE in the I-stage or III-stage will be in HLS (ie, the power penalty will be always one) VII UMERICAL EVALUATIO In Sec VII-A we investigate the design of interconnection networs by comparing the cost and the performance In Sec VII-B we investigate by means of simulation the performance improvement offered by the PPA-Paull algorithm with respect to the classical Paull algorithm A Interconnection networ design We compare interconnection networs by evaluating both the performance (in terms of power penalty index X) and the cost (in terms of number of microrings) Fig 7 shows the power penalty of different networs in function of Crossbars and Clos networs show a fixed power penalty index, as expected On the contrary, the Benes networ shows the worst scalability in performance, because X scales logarithmically with respect to the number of inputs, coherently with () The HCB and the HBC networs (for the two different cases n = 6 and n = 3) show the same

7 3 5 XBAR Closs Benes M-Benes HBC/HCB n=6 HBC/HCB n=3 M-HBC/M-HCB n=3 M-HBC/M-HCB n=6 4 XBAR Clos Benes M-Benes HBC M-HBC HCB M-HCB X 5 Cost Fig 7 Power penalty index Fig 9 Cost for maximum power penalty index ˆX = 5 Cost 4 3 XBAR Clos Benes M-Benes HBC M-HBC HCB M-HCB Fig 8 Cost for maximum power penalty index ˆX = 7 scalability law, as described by (3) and (5) As shown in Sec V, the mirrored technique roughly reduces X by a factor of two Thus, if we impose a maximum power penalty index ˆX, it is possible to build Benes networs with a number of ports equal to / instead of ; similar gains apply to the Benes part of the other networs ote that this advantage appears only for large, as predicted by our models Fig 8 and Fig 9 show the cost for different interconnection networs for two different values of maximum power penalty; the points refer only to feasible configurations, that is, compatible with the given target ˆX The main figure refers to smaller networs ( ranging from 4 to ), whereas the inset figure refers to larger networs ( from to 6 ) In general, the crossbar always shows the highest cost, while Benes networs always the lower one, whenever feasible Fig 8 shows that the only feasible Benes networ, when ˆX = 7, is for = 6 Instead, exploiting the mirroring technique, networs up to = 8 can be built Clos networs show the lowest complexity for very large Indeed, as the networ size increases, the worst case power penalty grows As a consequence, when ˆX is smaller, edge or inner crossbars in HBC/HCB networs must be larger On the contrary, Fig 9 shows that, if the target ˆX is larger, the size of crossbars inside the HBC and HCB networs decreases, reducing the overall cost Mirrored hybrid architectures reduce by a square factor the size of the internal crossbars For low values of ˆX, the mirroring technique becomes cost-effective for smaller HCB and HBC networs are feasible whenever the Benes networ violates the HLS constraint Among the two hybrid solutions, the HCB architecture exhibits a larger complexity than HBC networ, and similar observations hold for their mirrored solutions B The performance of the routing algorithm We compare the performance of the PPA-Paull algorithm with respect to the classical version of the Paull algorithm We report results only for Benes networs, which provide an upper bound on the power penalty experienced by the other architectures We assume a microring based interconnection networ, in synchronous operation, ie, time is divided into intervals of fixed duration (timeslots) and the networ transfers data units of fixed size (cells); the timeslot duration is equal to the transmission time of a cell In the case of variable-size pacets, incoming pacets are chopped into cells, while outputs reassemble all the cells belonging to the same pacet We consider a uniform traffic scenario, with ρ being the average load at each input port At each timeslot, we generate an input-output permutation π in which each input is active with probability ρ Starting from a random input and considering all the other inputs in a sequential fashion, a sequence of consecutive connections is generated according to the rule: if input i is active, it is connected to π(i) The routing algorithm adds each connection at the time in an incremental way, during the same timeslot Each path computed by the algorithm will result in a certain power penalty index; if such index is larger than ˆX, the corresponding connection is bloced To compare the routing algorithms, we measure the blocing probability P B ( ˆX) as the

8 Throughput Paull (ρ=9) Paull (ρ=5) Paull (ρ=) PPA-Paull (ρ=9) PPA-Paull (ρ=5) PPA-Paull (ρ=) Xˆ Fig Throughput under uniform traffic for = 64 P B (Xˆ ) Fig ρ = PPA-Paull (=3) PPA-Paull (=64) PPA-Paull (=8) Paull (=3) Paull (=64) Paull (=8) Xˆ Blocing probability in Benes networs under uniform traffic with average fraction of bloced input-output pairs over the number of active inputs As a complementary measurement, the throughput is evaluated as the average number of connections that are established without blocing in a generic timeslot; the maximum throughput is equal to the average load ρ and it is reached when a connection is never bloced, for any permutation In the figures, the throughput and the blocing probability are averaged across many timeslots Fig shows the throughput in function of the maximum power penalty ˆX for a Benes networ and different input loads: ρ {, 5, 9}, corresponding to a lightly, medium and highly loaded networ, respectively For enough large ˆX, the throughput reaches its maximum value (, 5 or 9 for each couple of curves), since the routing is not affected by the power penalty; in such case, all the algorithms behave the same ote that the number of stages for the considered networ is S(64) =, hence larger values of ˆX are not affecting the routing On the other side, smaller values of ˆX reduce the possibility of finding feasible paths; in the extreme case, the throughput approaches zero In general, PPA-Paull achieves always a better throughput than Paull When the input load ρ increases, the minimum ˆX to achieve the maximum throughput increases, since the routing is more constrained by a larger number of preliminary paths added during the current timeslot Fig, Fig and Fig 3 show the blocing probability in function of the maximum power penalty, each figure referring to a different value of input load The smaller plot inside each figure details the blocing probability for low values of ˆX The total number of stages S() in function of are S(3) = 9, S(64) = and S(8) = 3; whenever ˆX > S(), the blocing probability is zero by construction and the maximum throughput is achieved On the contrary, when ˆX approaches zero, the routing is severely constrained by the power penalty: the blocing probability increases and the throughput tends to zero Furthermore, as increases, in all the figures the blocing probability increases due to the larger networ depth In general, the reduction in the blocing P B (Xˆ ) Fig ρ = PPA-Paull (=3) PPA-Paull (=64) PPA-Paull (=8) Paull (=3) Paull (=64) Paull (=8) Xˆ Blocing probability in Benes networs under uniform traffic with probability due to PPA-Paull with respect to Paull is very large, reaching more than two orders of magnitude in some cases To better understand such results, consider the case in which just one path must be connected (this event may happen for low input load) If we set ˆX =, there will be only one specific destination (among possible ones) reachable by each input; the corresponding path will be found by PPA- Paull Thus, at low load and under uniform traffic, we can expect PB PPA-Paull () = / (consistently with the values in the figure) ow observe that, in a Benes networ, there exist always log = / different paths connecting any input to any output, since in the first log stages there are always two output ports in each module that can be used to reach any destination, whereas in the last log stages there exists just one output port in each module to reach the desired output Given an input-output pair with a possible path compatible with ˆX = (this pair is chosen with probability / as shown above), the Paull algorithm will choose one random path among the / available paths, but only one of them

9 P B (Xˆ ) Fig 3 ρ = PPA-Paull (=3) PPA-Paull (=64) PPA-Paull (=8) Paull (=3) Paull (=64) Paull (=8) Xˆ Blocing probability in Benes networs under uniform traffic with will be able to satisfy the constraint ˆX = Hence, we can expect that PB Paull() = / (coherently with the values in the figure), which is larger than PB PPA-Paull () We now evaluate the maximum power penalty experienced by a single path computed by PPA-Paull At each factorization level, PPA-Paull chooses the configuration of the first and the third stage to minimize the power penalty; in the case of a single path, the power penalty can increase by one at each factorization level As a consequence, the maximum power penalty will be log, equal to the number of factorization levels Hence, for low load, we expect that the blocing probability tends to zero when ˆX log Indeed, Fig shows that the observed blocing probability goes to zero for ˆX = 6, 7, 8 when = 3, 64, 8, which is very close to the bound found before VIII COCLUSIOS ACKOWLEDGMETS This wor was partially supported by the BOE project, a etwor of Excellence funded by the European Commission within the 7th Framewor Programme REFERECES [] M Haurylau, G Chen, H Chen, J Zhang, A elson, D H Albonesi, E G Friedman, and P M Fauchet, On-chip optical interconnect roadmap: Challenges and critical directions, IEEE Journal of Selected Topics in Quantum Electronics, vol, no 6, pp , ovember 6 [] A V Krishnamoorthy, X Z R Ho, H Schwetman, J Lexau, P Koa, G Li, I Shubin, and J E Cunningham, The integration of silicon photonics and vlsi electronics for computing systems intra-connect, in Photonic in Switching, 9 [3] M Petracca, B G Lee, K Bergman, and L P Carloni, Design exploration of optical interconnection networs for chip multiprocessors, in Hot Interconnects, 8, pp 3 4 [4] A Bianco, D Cuda, R Gaudino, F eri, G Gavilanes, and M Petracca, Scalability of optical interconnects based on microring resonators, IEEE Photonic Technology Letters, vol, no 5, pp 8 83, July [5] S I Association, International technology roadmap for semiconductors, [6] L Tobing and P Dumon, Photonic Microresonator Research and Applications Springer,, pp 3 [7] B G Lee, A Biberman, Sherwood-Droz, C B Poitras, M Lipson, and K Bergman, High-speed x switch for multi-wavelength message routing in on-chip silicon photonic networs, in European Conference on Optical Communication (ECOC), May 8 [8] A Bianco, D Cuda, M G R Gaudino, G Gavilanes, P Giaccone, and F eri, Optical interconnects based on microring resonators, in ICC, May [9] J Y Hui, Switching and traffic theory for integrated broadband networs Kluwer, 99 [] B G Lee, A Biberman, P Dong, M Lipson, and K Bergman, Alloptical comb switch for multiwavelength message routing in silicon photonic networs, IEEE Photonic Technology Letters, vol, no, pp , May 8 [] B G Lee, A Biberman, Sherwood-Droz, M Lipson, and K Bergman, Thermally active 4x4 non-blocing switch for networs-on-chip, Annual Meeting of the Lasers and Electro-Optics Society (LEOS), p TuBB3, ov 8 [] C Li and A Poon, Silicon electro-optic switching based on coupledmicroring resonators, in Conference on Lasers and Electro-Optics (CLEO), May 7 In this paper we analyzed the scalability in terms of cost and performance of different interconnection networs based on microring resonators We described the basic and switching elements, and we highlighted the asymmetric power penalty of the different switching states Then, we analyzed the effects of these asymmetries on the cost and feasibility of crossbar, Benes and Clos networs To achieve a better compromise between costs (in terms of switching elements) and performance (in terms of power penalty), we proposed (i) two architectures based on different combinations of the Benes and crossbar networs and (ii) the mirroring technique Finally, we proposed a simple variation of the classical Paull algorithm to set up new connections, and we investigated the corresponding improvement in terms of the power penalty Given the promising results obtained in our studies, we believe that the role of microring resonators in future high capacity photonic interconnection networs will become more and more relevant