Graphene-enabled hybrid architectures for multiprocessors: bridging nanophotonics and nanoscale wireless communication

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Sergi Abadal*, Albert Cabellos-Aparicio*, José A.

* NaNoNetworking Center in Catalunya (N3Cat) Optical

1 Graphene-enabled hybrid architectures for multiprocessors: bridging nanophotonics and nanoscale wireless communication Sergi Abadal*, Albert Cabellos-Aparicio*, José A. Lázaro, Eduard Alarcón*, Josep Solé-Pareta* and Mario Nemirovsky * NaNoNetworking Center in Catalunya (N3Cat) Optical Communications Group (GCO) Senior ICREA Research Professor in Barcelona Supercomputing Center (BSC)

2 Table of Contents Introduction The need for Photonic Networks-on-Chip Graphene-enabled Hybrid Optical/Wireless Network-on-Chip Concluding Remarks 6/22/2012 2

3 Table of Contents Introduction The need for Photonic Networks-on-Chip Graphene-enabled Hybrid Optical/Wireless Network-on-Chip Concluding Remarks 6/22/2012 3

4 Motivation The performance bottleneck of multicore processors has shifted from the computation capacity to the inter-core communication capacity. Need new scalable communication techniques Initial approach: Network-on-Chip (NoC) 6/22/2012 4

5 Network-on-Chip Network-on-Chip: substitute bus-based architectures with wireline routed networks to communicate cores of a processor. 6/22/2012 5

6 Network-on-Chip: Problems The initial concept of Network-on-Chip has already become outdated due to scaling. Technology Downscaling Higher delay per length Higher power consumption Core Density Upscaling Higher power consumption Higher multihop latency Higher router complexity Higher comm requirements 6/22/2012 6

7 Network-on-Chip: Problems It seems that copper-based interconnections will no longer be able to meet the sustained increase of the requirements in this scenario. High energy per bit ratio 6/22/2012 7

8 Table of Contents Introduction The need for Photonic Networks-on-Chip Graphene-enabled Hybrid Optical/Wireless Network-on-Chip Concluding Remarks 6/22/2012 8

9 The Need for Photonic NoCs [1] D. A. B. Miller, 2009 Energy per bit requirements Foreseen efficiency for electrical interconnects Target efficiency for optical interconnects 6/22/2012 9

10 The Advent of Nanophotonics High photonic device footprint CMOS process incompatibility Nanophotonics Low device area CMOS compatibility 6/22/

11 The Advent of Nanophotonics (II) High photonic device footprint CMOS process incompatibility Graphene Nanophotonics Nanoscale Si Photonics Low device area CMOS compatibility 6/22/

The Advent of Nanophotonics (III) Nanoscale Silicon Photonics

Individual elements at >40 Gb/s [4] Broadband Modulator of

for 500 GHz) [6] [3] T. Baehr-Jones et al, 2012 [4] M.

12 The Advent of Nanophotonics (III) Nanoscale Silicon Photonics Graphene Nanophotonics Wafer-scale platform at 25Gb/s [3] Individual elements at >40 Gb/s [4] Broadband Modulator of only 25 µm 2 [5] Photodetector at 40 GHz bandwidth (potential for 500 GHz) [6] [3] T. Baehr-Jones et al, 2012 [4] M. Ashgari et al, 2011 [5] M. Liu et al, 2011 [6] F. Xia et al, /22/

13 Photonic Network-on-Chip (I) [7] S. Abadal et al, 2012 Nanophotonics + NoC = Photonic NoC High-bandwidth and low-power NoC A wide variety of design proposals for Photonic NoC appeared recently [7]: Different logical topologies Fully optical or O/E hybrid. Arbitration-based or contention-free Two examples 6/22/

Plane Electrical Control Plane [8] A. Shacham, K.

14 Photonic Network-on-Chip (II) Photonic Mesh Hybrid Optoelectric Design Circuit-switched Photonic Data Plane Electrical Control Plane [8] A. Shacham, K. Bergman, et al, 2008 Photonic Switches 6/22/

15 Photonic Network-on-Chip (III) ATAC Fully Optical Crossbar Contention-Free [9] G. Kurian et al, 2010 Processor [~400 µm] Waveguide Bundle 6/22/

16 Photonic Network-on-Chip (IV) DO WE NEED HYBRID ARCHITECTURES? Since some all-optical functions are costly to implement (e.g. buffering, header processing), all-optical NoC designs need costly arbitration schemes or contention-free architectures. Moreover, all-optical NoC options do not scale well. The hybrid approach can provide better scalability by relaxing of some all-optical constrains. However, we want to additionally offer new features. 6/22/

17 Table of Contents Introduction The need for Photonic Networks-on-Chip Graphene-enabled Hybrid Optical/Wireless Network-on-Chip Concluding Remarks 6/22/

18 Graphene-enabled Hybrid Optical/Wireless NoC (I) 6/22/

Graphene-enabled Hybrid Optical/Wireless NoC (VI) WHY GRAPHENE FOR WIRELESS?

not meet either bandwidth or size requirements Graphene antennas are size

19 Graphene-enabled Hybrid Optical/Wireless NoC (VI) WHY GRAPHENE FOR WIRELESS? Because of graphene-based nano-antennas [10, 11] Metallic on-chip antennas do not meet either bandwidth or size requirements Graphene antennas are size compatible with processors Wireless communication at the core level. [10] J.M. Jornet, Ian F. Akyildiz, 2010 [11] I. Llatser et al, 2012 Bandwidth is enough as we expect to radiate in the THz band 100 µm ~ 1mm 1 ~ 10 µm 50 µm ~ 1mm 6/22/

20 Graphene-enabled Hybrid Optical/Wireless NoC (II) WHY WIRELESS? Latency Reconfigurability Inherent broadcast and multicast Improved Scalability 6/22/

21 Graphene-enabled Hybrid Optical/Wireless NoC (III) Broadcast/multicast capabilities are of key importance: Some pervasive parallel applications entail massive all-to-all communication BigData 3D FFT (Supercomputing) MapReduce (Google) A vital part of on-chip traffic is multicast: Cache coherence Data consistency Global resource management 6/22/

22 Cache Coherence A = 1 A = 1 A = 1 A = 1 6/22/

23 Cache Coherence A = 2 A = 1 A = 1 A = 1 6/22/

24 Cache Coherence A = 2 A = 2 A = 2 A = 2 6/22/

25 Cache Coherence A = 2 A = 2 A = 2 A = 2 6/22/

26 Graphene-enabled Hybrid Optical/Wireless NoC (V) Providing broadcast and multicast communication at the core level could signify not only a relief in the latency and power bottlenecks of traditional multicore architectures, but also a paradigm shift in the way cores of a processor interact between them and with memory. 6/22/

27 Table of Contents Introduction The need for Photonic Networks-on-Chip Graphene-enabled Hybrid Optical/Wireless Network-on-Chip Concluding Remarks 6/22/

28 Concluding Remarks Modern multiprocessors need efficient and scalable ways to communicate its cores. 6/22/

29 Concluding Remarks Modern multiprocessors need efficient and scalable ways to communicate its cores. Graphene enables solutions for this matter, by providing both high-bandwidth, low-power (nanophotonics) and reconfigurable, inherently broadcast (nanoscale wireless) on-chip communication. 6/22/

30 Concluding Remarks Modern multiprocessors need efficient and scalable ways to communicate its cores. Graphene enables solutions for this matter, by providing both high-bandwidth, low-power (nanophotonics) and reconfigurable, inherently broadcast (nanoscale wireless) on-chip communication. Our vision is a graphene-enabled hybrid opticalwireless on-chip network that will provide means for novel multiprocessor architectures. 6/22/

31 References (I) [1] D. A. B. Miller, Device Requirements for Optical Interconnects to Silicon Chips, Proc. IEEE 97, , [2] Rajeev J. Ram, CMOS Photonic Integrated Circuits, Optical Fiber Communication Conference (OFC), March 2012, Los Angeles, California [3] T. Baehr-Jones et al, A 25 Gb/s Silicon Photonics Platform Preprint at [4] M. Asghari, and A. V. Krishnamoorthy, Silicon photonics: Energy-efficient communication, Nature Photonics 5, , [5] M. Liu et al. A graphene-based broadband optical modulator, Nature, vol. 474, no. 7349, pp. 64-7, [6] F. Xia et al. Ultrafast graphene photodetector, Nature Photonics, vol. 4, pp , Dec [7] Abadal, S., Cabellos-Aparicio, A., Lázaro, J. A., Alarcón, E., Solé-Pareta, J., Graphene-enabled hybrid architectures for multiprocessors: bridging nanophotonics and nanoscale wireless communication, to appear in Proceedings of ICTON, /22/

32 References (II) [9] A. Shacham, K. Bergman, and L. P. Carloni, Photonic networks-on-chip for future generations of chip multiprocessors, IEEE Transactions on Computers, vol. 57, no. 9, pp , Sep [8] G. Kurian et al. ATAC: A 1000-Core Cache-Coherent Processor with On-Chip Optical Network, in Proceedings of the 19th international conference on Parallel architectures and compilation techniques. ACM, 2010, pp [10] Jornet, J. M. and Akyildiz, I. F., "Graphene-based Nano-antennas for Electromagnetic Nanocommunications in the Terahertz Band," in Proc. of EUCAP 2010, Fourth European Conference on Antennas and Propagation, Barcelona, Spain, April [11] I. Llatser, C. Kremers, A. Cabellos-Aparicio, J. M. Jornet, E. Alarcón and D. N. Chigrin, Graphene-based Nano-patch Antenna for Terahertz Radiation, in Photonics and Nanostructures - Fundamentals and Applications, May /22/

33 Thank you! Thank you very much for your attention. Any question? 6/22/

34 Thank you! 6/22/

35 Nanophotonics Silicon Photonics [3] T. Baehr-Jones et al, 2012 Nanoscale Silicon Photonics (Silicon-On-Insulator) Total reflection waveguides are obtained by the deposition of the silicon waveguide on top or below of a silicon oxide (SiO 2 ) insulator layer. 6/22/

36 Nanophotonics Silicon Photonics (II) [3] T. Baehr-Jones et al, 2012 [4] M. Ashgari et al, 2011 Wafer-scale photonics platform at 25Gb/s with 1Vpp have been demonstrated in [3], including: Modulators Filters Detectors Individual elements demonstrated at higher speeds (40 Gb/s) [4] 6/22/

37 Graphene Nanophotonics [5] M. Liu et al, 2011 [6] F. Xia et al, 2009 Graphene Nanophotonics Consists on the propagation of confined light in the form of plasmons in graphene nano-structures. 6/22/

38 Graphene Nanophotonics (II) [5] M. Liu et al, 2011 [6] F. Xia et al, 2009 CMOS compatibility is maintained as graphene technology is, in principle, compatible with CMOS processes. The first results are indeed promising: Optical Modulator of only 25 µm 2 with broadband operation [5] Transistor-based photodetector at 40 GHz (potential for 500 GHz bandwidth) [6] 6/22/

Hybrid On-chip Data Networks. Gilbert Hendry Keren Bergman. Lightwave Research Lab. Columbia University

Hybrid On-chip Data Networks. Gilbert Hendry Keren Bergman. Lightwave Research Lab. Columbia University Hybrid On-chip Data Networks Gilbert Hendry Keren Bergman Lightwave Research Lab Columbia University Chip-Scale Interconnection Networks Chip multi-processors create need for high performance interconnects