Silicon Photonics PDK Development

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1 Hewlett Packard Labs Silicon Photonics PDK Development M. Ashkan Seyedi Large-Scale Integrated Photonics Hewlett Packard Labs, Palo Alto, CA

2 Outline Motivation of Silicon Photonics Approach to PDK development Theory Design Optical Components Experimental Results PDK Results Future Work

Penetration of optics into communication

3 Penetration of optics into communication systems Level of integration Photonic fabric for future datacenters Active optical cable Mid-board optics Co-packaged Integrated HPE The Machine Multiple SOC + memory nodes High radix packet switch, exploiting photonic IO Optical switching for reconfiguration Intra-rack fiber in all-to-all topology All fiber from motherboard edge Inter-rack fiber, all-to-all between racks, many parallel paths Electrons Compute Photons Ions Communicate Store VCSEL-based OE engine HPE Photonic Roadmap All-optical Hybrid laser Silicon PIC logic

The Photonic Opportunity for Data Movement Energy efficient,

challenge to continued scalability across computing platforms

movement Bandwidth taper from chip to system forces extreme

4 The Photonic Opportunity for Data Movement Energy efficient, low-latency, high-bandwidth data interconnectivity is the core challenge to continued scalability across computing platforms Energy consumption completely dominated by costs of data movement Bandwidth taper from chip to system forces extreme locality Reduce Energy Consumption Eliminate Bandwidth Taper K. Bergman, ECOC,

5 Exascale network energy requirements End-to-end data movement energy budget: 10 Gigaflop/J, 10% of the envelope 10 Gigaflop/J, 15% of the envelope 50 Gigaflop/J, 10% of the envelope 50 Gigaflop/J, 15% of the envelope Energy budget per bit (pj) s of pj to 10s pj 10s of pj to single pjs pjs to fjs! Verbosity (byte/flop) 0.25 pj/bit K. Bergman, ECOC, 2015

6 Objective: Build analytical model in Verilog-A that predictably determines electro-optical behavior of ring modulator Inputs: Waveguide dimensions Through/Drop Gaps DC heater voltage AC modulator drive Verilog-A model Map physical dimensions to analytical equation parameters Experimentally determine device behavior dependence on input parameters by a Design of Experiments

7 Proposed Approach Workflow Dream Scenario This approach allows an automated PCell approach that would automatically modify the GDS depending on choice of foundry, design parameters, etc. 7

The Dream Explained Existing Capabilities Cadence/Lumerical https://www.lumerical.com/solutions/partners/c adence/ Mentor Graphics/Lumerical http://www.mentor.

8 The Dream Explained Existing Capabilities Cadence/Lumerical adence/ Mentor Graphics/Lumerical -lumerical-optical-design IPKISS/Luceda STMicroelectronics F. Boeuf, OFC, 2015 Remaining steps are open areas for innovation and development, as proposed in this UHU Project approach 8

9 Carrier-Injection Ring Modulator Fabricated at Leti (Grenoble, FR) on 200mm platform 5 and 10 micron diameter ~2dB/bend loss Q in the range of 7-12k routinely Resistive heater in silicon rib 30 uw/ghz efficiency Carrier injection P-i-N diode ER > 10dB IL < 1dB 450nm Buried Oxide 250nm Intrinsic Si 300nm P+ Si N+ Si Buried Oxide/Cladding

10 Ring Resonator PDK Component W cp G th G dr W cp Vary gaps for a fixed coupler width to achieve critical coupling as determined by quality factor Q and extinction ratio (ER)

11 Lumerical MODE varfdtd Simulation Setup

12 Lumerical Modeling Simulation results

13 Simulation Results cont d.

14 Cadence Virtuoso SKILL Code and Layout

15 Full Reticle

16 Ring Resonator DOE Layout

17 Gt = 150:25:300 Extract Q and ER from Microring Spectra Gd = 175:25:325 Over Coupling Under Coupling

18 Experimental Statistical Data

19 Extract Coupling Coefficients from Q and ER: Equations Define:, L t 2a d c 1 2a c 2 r Q FSR From FSR Under coupling: c R 2 Over coupling: 1 0 c (1 R ) 2 1 (1 0) 2 0 c (1 R ) 2 c (1 R0) a 2 2 a From the transmission at resonance wavelength R 0

20 Extract Coupling Coefficients from Q and ER: Experiments Kappa thru decreases with Gthru Kappa drop decreases with Gdrop There are some unexpected fluctuations, especially in kappa drop

21 Model of Coupling Coefficient vs. Coupling Gap Q Define: 1 2a 2 t L 2 r FSR ( ) Thru port ER 1 2a 2 d Q and ER depend on delta_1 and 2a: 1 2a 1 2a 2 t d Drop port efficiency 2 1 2a 2 Use average of the kappa thru (or drop) a1 = b1 = c1 = 0 a exp( b G ) c t 1 a exp( b G ) c 2a 2 2 d 2 a2 = b2 = c2 = Therefore, we just need to store a1, b1, c1, a2, b2, c2, we could calculate delta_1 and 2a and then the Q and ER

22 Virtuoso Simulated Ring Spectra Gthru = 200 nm x-axis: wavelength in um y-axis: optical power in mw Input optical power = 1mW Gdrop = 175 nm Under-coupling Gdrop = 225 nm Critical-coupling Gdrop = 275 nm Over-coupling

23 Virtuoso Schematic Simulations R. Wu, et al., IPR (Vancouver) 2016

24 Virtuoso Simulation Results R. Wu, et al., IPR (Vancouver) 2016

25 Objective: 0.25Tb/s/fiber+ with <5pJ/bit (all inclusive) Low (<10k) Wider channel spacing Less channels Short photon lifetime Higher data rate Low (<10 Gb/s) Easier/Cheaper driver design Lower PD sensitivity and TIA power Cavity Q Data Rate High (>10k) Narrow channel spacing More channels Long photon lifetime Lower data rate High (>10 Gb/s) More challenging driver design Higher PD sensitivity and TIA power What is the crosstalk between two channels given a certain Q, spacing, and data rate? Leakage due to Lorentzian lineshape Sidebands from modulation Spectral Blue shift of Lorentzian

26 Back to Back On-Chip Transceiver 23 lines at 50GHz spacing 5 channel Transmitter Optical Power supply 5 channel Receiver Electrical I/O & power * C. Li et. al. ISSCC 13, IEEE Design & Test 14 * K. Yu et. al. OFC 15, ISSCC 15 * C. H. Chen et. al. OIC 13, 14, 15

27 Back-to-Back Simulation in Virtuoso: Schematic Mod Output Optical Eye PD Photocurrent Electrical Eye 20 Gb/s Gthru = 200 nm Gdrop = 225 nm Critical-coupling

28 Eye Diagrams Laser power increased ~2dB here to improve eye quality Ring Mod: 10 Gb/s 15 Gb/s 20 Gb/s 25 Gb/s On-Chip PD:

29 Device Optical Transmission

30 Experimental Setup Tunable Laser 1 Tunable Laser 2 3dB Combiner 8dB/Grating IL Photonics Chip Tunable Optical Filter + df + df D /D Anritsu PPG D /D Anritsu PPG High-Speed Photodetector (Discovery Semi.) Anritsu BER Anritsu BER DCA Scope

31 Related Experimental Results Seyedi, et al., Photonics in Switching 2016

32 Future Steps Work to improve uniformity and number of comb laser lines DWDM with packaged CMOS driver

33 Thank You

PIC training: Interconnect System Design

PIC training: Interconnect System Design Keren Bergman PhoenixSim Optical hardware Meisam Bahadori, Sébastien Rumley Lightwave Research Laboratory Columbia University Network Application Silicon Photonics