Architectural Time-predictability Factor (ATF) to Measure Architectural Time Predictability

Transcription

1 Architectural Time-predictability Factor (ATF) to Measure Architectural Time Predictability Yiqiang Ding, Wei Zhang Department of Electrical and Computer Engineering Virginia Commonwealth University

2 Outline Motivation Architectural Time Predictability (ATP) Architectural Time-predictability Factor (ATF) Evaluation Conclusions

3 Embedded and Real-Time Applications Medical equipment Robotics Space exploration Avionics Automobiles iphone 3

4 Worst-Case Execution Time (WCET) Possible Execution Time BCET WCET 0 Average case Execution Time Estimated WCET "Then there was the man who drowned crossing a stream with an average depth of six inches. -W.I.E. Gates 4

5 Variation of Execution Time on Microprocessors Inputs if Runtime Program Paths Timing of Processors Caches Pipelines Branch Prediction Speculation OOO Execution To Processor Cache then else L2 or Memory From Processor Blk X Blk Y 5

6 Motivation Multicore and manycore processors with shared resources will aggravate the WCET analysis problem! Interferences in shared caches Interferences in shared buses or interconnection networks Impact of synchronization and cache coherence traffic Solution: Design for Time Predictability (or WCET Analyzability)

7 Related Work Designs of time-predictable processors SPEAR employed a simple 3-stage pipeline and no cache memories [2] Time-predictable multi-core architecture to support WCET analyzability [3] A simple asymmetrical multiprocessor architecture for hard realtime applications, which has no dynamic features [4] A time-predictable Java processor [5] Metrics of time predictability The pessimism of WCET analysis and BCET analysis [4] State-induced time predictability and input-induced time predictability [6] Combining WCET analyzability and the stability of the system [7]

8 Motivation However currently there is no effective and widely accepted metric to quantitatively evaluate time predictability of processors, which greatly impedes the advancement of time-predictable processor design A Quantitative Guide Needed

9 Architectural Time Predictability Architectural Time Predictability (ATP) Given an architectural design of a processor, architectural time predictability indicates how close the actual timing behavior is to the baseline timing behavior specified in the timing contract of the processor ATP evaluates this gap Baseline timing behavior specified in timing contract Actual timing behavior with architectural effects Length of execution time

10 Architectural Time-predictability Factor Architectural Time Factor (ATF) Given a processor P, an arbitrary real-time trace T, the actual execution time D(P, T), and the statically predicted execution time based on the timing contract S(P, T), ATF can be defined as: ATF(P, T) D(P, T) S(P, T) S(P, T) D(P, T) Instruction scheduling Running on a processor static sched time dynamic exec time ATF dynamic exec time static sched time

11 ATF for VLIW VLIW processor is relatively more time-predictable than superscalar processor which dynamically scheduling the instructions by the hardware VLIW architecture exposes as much timing and hardware information as possible to the compiler which schedules the instructions HPL-PD based VLIW processor still has some architectural features that can compromise architectural time predictability Branch architecture Speculative execution Cache memories

12 Compute Static Scheduling Time Static Scheduling Time Analysis

13 ATF of a VLIW Processor ATF of all benchmarks in an ideal VLIW processor ATF of all benchmarks in a realistic VLIW processor

14 Architectural Time-predictability Factor ATF with the number of integer ALUs ranging from 1, 2 to 4 ATF of a processor with SPMs compared with ATF of a processor with caches

15 Conclusions ATF can provide useful insights of processor s architectural time predictability Our evaluation indicates that while speculative execution, branch prediction and cache memories can all affect architectural time predictability, caches have the most significant impact on ATP of the VLIW processor we studied

16 Conclusions (cont.) Increasing the number of functional units can improve performance but degrade time predictability Using SPMs instead of caches can increase time predictability but may degrade performance We can use ATF to make better and quantitative tradeoffs between time predictability and performance to support both hard and soft realtime computing and/or a mix of real-time and non-real-time applications with different criticalities

17 References [1] Y. S. Li, S. Malik and A. Wolfe. Performance estimation of embedded software with instruction cache modeling. ACM TDES, Volumn 4, Issue 3, [2] M. Delvai, W. Huber, P. Puschner, and A. Steininger. Processor support for temporal predictability - the spear design example. In Real-Time Systems, Proceedings. 15th Euromicro Conference on, july 2003, pp [3] M. Paolieri, E. Qui nones, F. J. Cazorla, G. Bernat, and M. Valero, Hardware support for wcet analysis of hard real-time multicore systems, in Proceedings of the 36th annual international symposium on Computer architecture, ser. ISCA 09. New York, NY, USA: ACM, 2009, pp [4] L.Thiele and R.Wilhelm, Design for time-predictability, in Perspectives Workshop: Design of Systems with Predictable Behaviour, ser. Dagstuhl Seminar Proceedings, L. Thiele and R. Wilhelm, Eds., no Dagstuhl, Germany: Internationales Begegnungs- und Forschungszentrum f ur Informatik (IBFI), Schloss Dagstuhl, Germany, [5] M. Schoeberl, Time-predictable computer architecture, EURASIPJ. Embedded Syst., vol. 2009, pp. 2:1 2:17, January 2009

18 References [6] J. R. Daniel Grund and R. Wilhelm, A template for predictability definitions with supporting evidence, in Bringing Theory to Practice: Predictability and Performance in Embedded Systems, 2011 [7] R. Kirner and P. Puschner, Time-predictable computing, in 8 th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems, Waidhofen, Austria, 2010

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