2. Link and Memory Architectures and Technologies

Transcription

1 2. Link and Memory Architectures and Technologies 2.1 Links, Thruput/Buffering, Multi-Access Ovrhds 2.2 Memories: On-chip / Off-chip SRAM, DRAM 2.A Appendix: Elastic Buffers for Cross-Clock Commun. Manolis Katevenis CS-534 Univ. of Crete and FORTH, Greece

2 2.1 Links, Throughput/Buffering, Multi-access Ovrhds Table of Contents: Rate, Throughput, Buffer Space, Serial - Parallel Parallel and Serial Transmission Links Parallel-Serial Conversion: Multiplexing, Demultiplexing Rate, Throughput, Capacity, Load Throughput Time Buffer Space Equation Point-to-Point versus Multi-Access Links Turn-around Overhead, Link Utilization Arbitration Overhead Sequential versus Parallel Transmissions U.Crete - M. Katevenis - CS-534 2

3 2.1.1 Parallel Transmission Links Out-of-band Framing start-of-packet, end-of-packet valid word / idle line Usable for short distances (datapaths): requires synchronization among wires at high frequencies: source-synchronous (unidirectional) & partial-word clocking Signaling rate on Clock vs. Data Wires: Plain Clocking: signaling rate on clock wire is twice the rate of data wires DDR (Double Data Rate): double the signaling rate on all other wires as well, to match the maximum feasible rate presumably already used for the clock wire U.Crete - M. Katevenis - CS-534 D F ck (Data) (framing) (clock) n 1 1 Plain Clocking: D F ck D F ck min. pulse width = T min. pulse width = T/2 DDR Clocking: min. pulse width = T/2 min. pulse width = T/2

4 Serial DataIn 1 Local Estimated Clock Serial Transmission Links compare & adjust sample & hold, ser2par conv. DataOut n framing Local Adjusted Clock adjust local clock PLL cmp Local Osc. fast ck div Clock Recovery slow ck Eliminate Timing Skew problem among wires; Reduce wire cost Need data to contain edges every so often for clock recovery (phase-locked loop PLL) to work line coding (e.g. 8b/10b) U.Crete - M. Katevenis - CS-534 4

5 Parallel-to-Serial Conversion: Multiplexing out out cnt cnt ck slow ck fast ck slow ck fast ck byte Bit-Interleaved Byte-Interleaved Note: buffer space = sizeof (one periodic frame) U.Crete - M. Katevenis - CS-534 5

6 Serial-to-Parallel Conversion: Demultiplexing ck fast in in Clock Recovery ck fast ck slow framing φ φ φ φ φ φ φ φ Bit-Interleaved writeaddr counter Byte-Interleaved ck slow U.Crete - M. Katevenis - CS framing

7 Codes, Framing, Rate, Throughput,Capacity, Load Line coding provides extra Control Characters used for framing: start/end-of-packet, idle, etc. Signaling Rate (Baud Rate): electrical symbols / second e.g. quadrature modulation 1 symbol = 2 bits Transmission Rate: raw bits / second (raw bps) Throughput: useful bits / second (useful bps) Throughput = Transmission Rate minus Overhead Capacity: Peak rate or throughput Load: Current, actual (average) throughput or (non-idle) rate U.Crete - M. Katevenis - CS-534 7

8 2.1.2 Throughput Conservation m λ1 λ1 λ1 Λ λ2 λ2 λ2 λ2 n Aggregation (multiplexing) Distribution (demultiplexing) m λ 1 = Λ = n λ 2 either Instantaneous (no buffering) or Average (with buffering) what is conserved is the useful-information throughput coding may change, idle bits may be added or removed, information may be filtered and/or selectively dropped, etc U.Crete - M. Katevenis - CS-534 8

9 Throughput-Buffer Equ. Bytes time window w A(t) λ in buffer mem. λ out D(t) λ in2 Cumulative amount of "useful" data arriving bits A(t) w1 λ in1 λ out1 buffer occupancy λ out departing bits D(t) λ in w2 delay (if FIFO departures) time λ out2 Buffer Space λ in - λ out w time U.Crete - M. Katevenis - CS-534 9

10 Throughput Time Buffer Space Equation Buffer Space λ in - λ out w time Throughput Conservation Law holds in the long-run Time scale for long run is proportional to Buffer Space Buffer is proportional to Burst Size burst: a large throughput difference that persists for certain time Average Delay = (Average Buffer Occupancy) / λ express the area between arrival and departure curves as either: vertical slices: (average buffer occupancy) (time window) horizontal slices: (avg. delay) (# of Bytes) = (delay) λ w (assume FIFO, but average is same under any service policy) U.Crete - M. Katevenis - CS

11 Parallel Link Forms / Concepts: Bit Cell-Slice Packet Flow bit 1 of 8 By. 1-8 packet 1 flow 1 bit 2 of 8 By packet 2 flow 2 bit 3 of 8 By packet 3 flow 3 bit 4 of 8 By packet 4 flow 4 bit 5 of 8 By packet 5 flow 5 bit 6 of 8 By packet 6 flow 6 bit 7 of 8 By packet 7 flow 7 bit 8 of 8 By of 64B cell packet 8 flow 8 Inverse Multiplexing same handling for all wires (same time, same destination) different handling (diff. times & destinations) U.Crete - M. Katevenis - CS

12 Parallelism Styles: Data-only vs. Data-and-Control Data-only link parallelism SIMD Style: multiple wires or sub-links carry data portions of a same packet same control (routing, scheduling, contention resolution, buffering) for all wires / sub-links / portions of the packet Data-and-Control link parallelism MIMD Style: sub-links carry different packets each control is separate for each sub-link called Inverse Multiplexing the key to scalable switching U.Crete - M. Katevenis - CS

13 2.1.3 Point-to-Point versus Multi-Access Links Point-to-Point: Shared Medium: xmit1 xmitn xmit rcvr rcvr1 rcvrm (e.g. high-speed copper or fiber links) (e.g. wireless links, old ethernet, buses) Higher Performance: no turn-around delay no arbitration overhead increased parallelism when used with switches This course: point-to-point! Lower Cost: broadcast & select: switching is inherent in the medium natural in some environments --e.g. wireless without directional antenas U.Crete - M. Katevenis - CS

14 Multiple-Access Links (Buses): Turn-Around Overhead xmitter X1 X1 xmitter shared medium d R1 R2 receiver d receiver distance Slope= speed c d/c Slope= speed c Slope= speed c For non-overlapping reception: d/c idle time on every change of transmitting station, where c = speed of light in the link medium time U.Crete - M. Katevenis - CS d/c

15 How many bits is the length of the wire? Turn-around delay expressed as a lost opportunity to transmit an amount of information equivalent to: How long (in meters) is a packet on the wire? Duration of each transmit session (assume one packet), in time or in equivalent packet "length" on the wire: pck sz = 10 Kb = 1.2 KB avg IP pck sz. pck sz = 1 Kb = 128 B equivalent packet "length" on the wire 20m 200m 2km 20km 200km p a c k e t t i m e 100ns 1us 10us 100us 1ms d=2km d/c = 10 us d=200m d/c = 1 us K 12K d=20m d/c = 100 ns c ~= 200 Mm/s K 10K 100K 10M 100M 1G 10G 10M 100M 1G 10G bits bits/s link throughput link throughput bits/s Bytes 15

16 Link Utilization = f( Packet Sz, Wire L, Throughput ) packetsize Link = = Utilization packetsize + turnaroundbitequiv packettime packettime + turnarounddelay = = = = = = 99% 91% 50% 128 B, 2 m; or 1.2 KB, 20 m; or 12 KB, 200 m 128 B, 20 m; or 1.2 KB, 200m; or 12 KB, 2 km = = 9% 128 B, 200 m; or 1.2 KB, 2 km = = 1% 128 B, 2 km; or 1.2 KB, 20 km Link Utilization 10M 100M 1G 10G bits/s Link Throughput Packet Size, Link Length U.Crete - M. Katevenis - CS

17 Multiple-Access Links (Buses): Arbitration Overhead xmit1 1. req-1 2. grant Arbiter 1. req-n xmitn 3. data rcvri Separate medium for requests and grants? increased media cost, increased latency. Shared medium for all of request, grant, and data? reduced throughput, increased latency. Optimistic arbitration (CDMA/ethernet style)? limited peak throughput, very high latency at high loads U.Crete - M. Katevenis - CS

18 Sequential versus Parallel Transmissions Shared Medium: Point-to-Point Links + Switches: Single transmission at a time Multiple transmissions in parallel U.Crete - M. Katevenis - CS