Basics DRAM ORGANIZATION. Storage element (capacitor) Data In/Out Buffers. Word Line. Bit Line. Switching element HIGH-SPEED MEMORY SYSTEMS

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1 Basics DRAM ORGANIZATION DRAM Word Line Bit Line Storage element (capacitor) In/Out Buffers Decoder Sense Amps... Bit Lines... Switching element Decoder... Word Lines... Memory Array Page 1

2 Basics BUS TRANSMISSION Decoder DRAM CPU BUS CONTROLLER In/Out Buffers Decoder... Word Lines... Sense Amps... Bit Lines... Memory Array Page 2

3 Basics [PRECHARGE and] ROW ACCESS Decoder DRAM CPU BUS CONTROLLER AKA: OPEN a DRAM Page/ or ACT (Activate a DRAM Page/) or RAS ( Strobe) In/Out Buffers Decoder... Word Lines... Sense Amps... Bit Lines... Memory Array Page 3

4 Basics COLUMN ACCESS Decoder DRAM CPU BUS CONTROLLER READ Command or CAS: Strobe In/Out Buffers Decoder... Word Lines... Sense Amps... Bit Lines... Memory Array Page 4

5 Basics DATA TRANSFER Decoder DRAM CPU BUS Out CONTROLLER In/Out Buffers Decoder... Word Lines... Sense Amps... Bit Lines... Memory Array... with optional additional CAS: Strobe note: page mode enables overlap with CAS Page 5

6 Basics BUS TRANSMISSION Decoder DRAM CPU BUS CONTROLLER In/Out Buffers Decoder... Word Lines... Sense Amps... Bit Lines... Memory Array Page 6

7 Basics CPU A F Mem Controller E 1 DRAM B C D E 2 /E 3 A: Transaction request may be delayed in Queue B: Transaction request sent to Memory Controller C: Transaction converted to Command Sequences (may be queued) D: Command/s Sent to DRAM E 1 : Requires only a CAS or E 2 : Requires RAS + CAS or E 3: Requires PRE + RAS + CAS F: Transaction sent back to CPU DRAM Latency = A + B + C + D + E + F Page 7

8 Basics Read Timing for Conventional DRAM RAS CAS Access Access Transfer out out Page 8

9 ary Tree MOSYS FCRAM Structural Modifications Targeting Latency Conventional DRAM (Mostly) Structural Modifications Targeting Throughput $ VCDRAM FPM EDO P/BEDO SDRAM ESDRAM Interface Modifications Targeting Throughput Page 9 Rambus, DDR/2 Future Trends

10 Read Timing for Conventional DRAM Access Access Transfer Overlap RAS Transfer CAS out out Page 10

11 Read Timing for Fast Page Mode Access Access Transfer Overlap RAS Transfer CAS out out out Page 11

12 Read Timing for Extended Out Access Access Transfer Overlap RAS Transfer CAS out out out Page 12

13 Read Timing for Burst EDO Access Access Transfer Overlap RAS Transfer CAS Page 13

14 Read Timing for Pipeline Burst EDO Access Access Transfer Overlap RAS Transfer CAS Page 14

15 Read Timing for Synchronous DRAM Clock RAS CAS Access Access Transfer Overlap Transfer Command ACT READ Page 15 (RAS + CAS + OE... == Command Bus)

16 Inter- Read Timing for ESDRAM Regular CAS-2 SDRAM, R/R to same bank Clock Command ACT READ PRE ACT READ Bank ESDRAM, R/R to same bank Clock Command ACT READ PRE ACT READ Bank Page 16

17 Write-Around in ESDRAM Regular CAS-2 SDRAM, R/W/R to same bank, rows 0/1/0 Clock Command ACT READ PRE ACT WRITE PRE ACT READ Bank Bank ESDRAM, R/W/R to same bank, rows 0/1/0 Clock Command ACT READ PRE ACT WRITE READ Bank Page 17 (can second READ be this aggressive?)

18 Internal Structure of Virtual Channel Bank B Bank A 2Kb Segment 16 Channels (segments) Input/Output Buffer $ 2Kb Segment 2Kbit # s s 2Kb Segment 2Kb Segment Decoder Sense Amps Sel/Dec Activate Prefetch Restore Read Write Page 18 Segment cache is software-managed, reduces energy

19 Internal Structure of Fast Cycle RAM SDRAM FCRAM 13 bits Decoder Decoder 8M Array 8M Array 15 bits (8Kr x 1Kb) (?) Sense Amps Sense Amps t RCD = 15ns (two clocks) t RCD = 5ns (one clock) Page 19 Reduces access time and energy/access

20 Internal Structure of MoSys 1T-SRAM addr Bank Select Auto Refresh $ Page 20 s

21 Comparison of Low-Latency DRAM Cores DRAM Type Bus Speed Bus Width (per chip) Peak BW (per Chip) RAS CAS (t RCD ) RAS (t RAC ) PC133 SDRAM MB/s 15 ns 30 ns ESDRAM MB/s 12 ns 24 ns VCDRAM MB/s 30 ns 45 ns FCRAM 200 * MB/s 5 ns 22 ns 1T-SRAM MB/s 10 ns DDR * MB/s 20 ns 45 ns DRDRAM 400 * GB/s 22.5 ns 60 ns RLDRAM 300 * GB/s??? 25 ns Page 21