TAG Word 0 Word 1 Word 2 Word 3 0x0A0 D2 55 C7 C8 0x0A0 FC FA AC C7 0x0A0 A5 A6 FF 00

Size: px

Start display at page:

Download "TAG Word 0 Word 1 Word 2 Word 3 0x0A0 D2 55 C7 C8 0x0A0 FC FA AC C7 0x0A0 A5 A6 FF 00"

Robert Clarke
5 years ago
Views:

1 ELE 758 Final Examination 2000: Answers and solutions Number of hits = 15 Miss rate = 25 % Miss rate = [5 (misses) / 20 (total memory references)]* 100% = 25% Show the final content of cache using the content of SDRAM (4) TAG Word 0 Word 1 Word 2 Word 3 0x0A0 D2 55 C7 C8 0x0A0 FC FA AC C7 0x0A0 A5 A6 FF 00 Fig. 1.1 Direct-mapped cache (4 x 4 words) Question # 1.2 a) Determine block size (N) in BYTES if miss penalty Tm = Taddr (SDRAM) + NxTw: Block size N = 64 Bytes Tav = Rhit x Th + R miss x T miss = R hit x Th + (1 Rhit) x [Taddr (SDRAM) + N x Tw ] N = [ T av R hit x Th (1 R hit)x Taddr (SDRAM)] / (1- Rhit) x Tw = = [21.5 ns 0.95 x 10 ns x 10 ns (1 0.95) x 80 ns ] / (1 0.95) x 10 ns = 16 Words = 16 x 4 Bytes = 64 Bytes b) Determine number of cache entries - N entr = 4096 N entr = Cache SRAM volume / Block size = 64 K x 32 bits / 16 x 32 bites = 4096 b) Create address word fields: Byte offset field contains 2 bits, because 32 bits Word contains 4 Bytes Block offset field contains 4 bits, because block contains 16 words Index field contains 12 bits, because cache contains 4096 entries Tag field contains 14 bits, because 32 bits (Addr. Word) 12 bits (Index field) 4 bits (block offset field) 2 bits (byte offset field) = 14 bits

2 CPU initiates data loads from the following Virtual addresses: a) 0x000061F3; b) 0x0000C015; c) 0x0000A034 For each reference determine Virtual and Physical page number, Page offset and Physical address, TLB and Cache hit or miss, Data read and necessity of Write back procedure initiation: Note: If the data is located in Main memory please put DMM- Data in the Main Memory For Virtual address = 0x000061F3 Determine the followings: Virtual page # = Page offset = 1F3 TLB hit or miss Hit Cache hit or miss Hit Physical page # 204 Physical address 0x2041F3 Data to CPU 0xAC Initiate the write back procedure? Yes or No (circle)? For Virtual address = 0x0000C015 Determine the followings: Virtual page # = 0000C Page offset = 015 TLB hit or miss Miss Cache hit or miss Hit Physical page # 02A Physical address 02A015 Data to CPU 7F Initiate the write back procedure? Yes or No (circle)? For Virtual address = 0x0000A034 Determine the followings: Virtual page # = 0000A Page offset = 034 TLB hit or miss Miss Cache hit or miss Miss Physical page # 1C0 Physical address 0x1C0034 Data to CPU DMM Initiate the write back procedure? Yes or No (circle)? Question # 3.1 V fpp = 2 sides x 80 tracks x 18 sectors x 512 B = 1440 KB Question # 3.2 Number of disks = 8

3 Ndisks = Total volume / (Number of cylinders * number of sectors * block size * 2) = = B / (4200 x 63 x 512 B x 2) = 7.99 = 8 Data transfer rate in Mbytes / S (speed with which data can be transferred to CPU from the disk). R hdd = MB / S R hdd = Number of rotations per second * number of sectors per track * block size = (6000 RPM / 60 S) x 63 x 512 B = B /S = MB / S Page fault penalty (time to replace block when page fault occurs), assuming that write back procedure is always initiated (worst case scenario) and there is no HDDcontroller overhead: T fp = 5 ms T fp = (Access time + Page transfer time) x 2 = 1.23 ms B / B/S = =(1.23mS ms) x 2 = 5 ms Question # 3.3 a) Video-output sub-system: D-to-A converters for R, G and B channels -Resolution and video-signal frequency: R-channel DAC: Resolution 10 bits; G-channel DAC: Resolution 12 bits; B-channel DAC: Resolution 10 bits; Conversion rate for RGB DACs M Samples / S Conv. Rate = 1280 x 1024 pixels x 100 frames / s = MS/s b) Calculate the frequency for synchro-signals for the non-interlived video-output: Vertical synchro-signal frequency F vs = 100 Hz

4 Horizontal synchro-signal frequency F hs = KHz F hs = 1024 rows x 100 frames / s = KHz c) Video-RAM subsystem : Calculate the total value of Video-RAM (Graphic mode), which should have two pages. One page is used for synchronous video-output and another to accumulate the data from the PCI-bus (next frame). Total Video-RAM volume = 10 M bytes V vram = 1280 pixels / row x 1024 rows x 32 bits /pixel x 2pages = KB = 10 MB Calculate minimum data transfer rate in M Bytes / S necessary to transfer the next frame (picture) within the display period of current frame: R dt (video) = 500 MB / S (2) R dt = 1280 pixels / row x 4 B / pixel x 1024 rows / frame x 100 frames / S = 500 MB / S Question #.4.1 a) Calculate the maximum PCI-bus data transfer rate for addressed (each data has individual address) and non-addressed (burst) data transmission (page transfer, etc.) Addressed mode Data transfer rate R dt (addr) = 132 Mbyte / S (1) Non-addressed mode Data transfer rate R dt (addr) = 264 Mbyte / S (1) Addr mode R = 8 B x 33 MHz / 2 (addr / data multiplexed) = 132 MB /S Non-addr mode R = 8 B x 33 MHz = 264 MB / S b) What a maximum refresh rate is possible to support by the above designed videoadapter (Question 3.3) if non-addressed mode for data transfer is used in PCI-bus. Max. Refresh rate (pictures / sec.) = 52.8 ~ 50 pictures / S Max. Refresh rate = 264 MB / S / 5 MB / picture = 52.8 pictures / S

5 Question # 4.2 Design the PCI-to- Centronics interface controller. Parameters of the Centronics parallel port are known from the timing diagram: - Data Strobe generates 2 us after the Data (1 Byte) is set on the data lines; - Data Strobe pulse width (pulled down) = 4 us (microseconds); - Time delay between front edge of Data Strobe and front edge (falling) of Acknowledge signal = 8 us (During this period of time device is busy ); - Acknowledge pulse width = 5 us; - It is necessary to have 5 us between the end edge (rising) of the Acknowledge signal and front edge of new Data Strobe signal to set properly next Data on the data lines. Calculate bus bandwidth for the Centronics parallel port: BW ( Centronics ) = _54.25_ KBytes / S (3) BW = 1Byte / ( ) us = KB / S Calculate volume of the FIFO-buffer for above interface controller, which can provide permanent data transmission via Centronics parallel port with the minimum interrupt signal period (from the controller to CPU) = 100 ms. V fifo = Kbytes (3) V fifo = KB / S x 100 ms = KB 5. Section: Computer Networks Question # 5.1 Shared media LAN can interconnect up to computers. There are 12 types of messages ( Request, Reply, Acknowledge, etc.) Data length in each message can vary from 0 byte to 64 K Bytes (with step = 1 Byte) Maximum length of the file to be transmitted = 4 G Bytes Maximum number of files to be transmitted in the buffer of the network card = 256 Fill blank spaces in the list of packet format fields (Table 5.1):

6 Table 5.1 (6) Field name Minimum number of bits Type of message 4 Length of the Data 16 Identifier 8 Fragment 16 Source Address 16 Destination Addr. 16 Identifier should generate ID for each of 256 files to be transmitted via buffer. Thus, Identifier field should have 8 bits. Fragment # = Maximum length of the file / Maximum length of message = 16 4 GB / 64 KB = = 2 Source / Destination Address fields = 16 bits because LAN can interconnect up to computers. Question # 5.2 In the table 5.2 is shown the packet format for switched media network. Cross the field in the packet, which is not necessary in this type of network. Table 5.2 (1) Field # Field name 1. Type of message 2. N/A Source address 3. Virtual Channel # 4. DATA 5. Check data

ELE 758 * DIGITAL SYSTEMS ENGINEERING * MIDTERM TEST * Circle the memory type based on electrically re-chargeable elements

ELE 758 * DIGITAL SYSTEMS ENGINEERING * MIDTERM TEST * Student name: Date: Example 1 Section: Memory hierarchy (SRAM, DRAM) Question # 1.1 Circle the memory type based on electrically re-chargeable elements