ID 220L: Hands-on Embedded Ethernet Design with an Open Source TCP/IP Stack

Transcription

1 ID 220L: Hands-on Embedded Ethernet Design with an Open Source TCP/IP Stack Renesas Electronics America Inc. Fatih Peksenar Senior Manager, Applications Engineering 12 October 2010 Version: 1.2 Embedded Ethernet has evolved over the years. It is now that MCU with Ethernet peripheral and all encompassing tools make it a realty to bring a coffee maker with Ethernet connectivity to the market. In this presentation and lab, I will show you that Open-Source TCP/IP stacks with freely available tools are now true enablers for less costly embedded Ethernet products. 1

2 Mr. Fatih Peksenar Manager, Applications Engineering Responsible for Ethernet Application development within the Renesas America Applications Group. Developed various Ethernet Application projects as examples and for customers. RX62N, SH7216, H8S2472 platforms PREVIOUS EXPERIENCE: Lead system designer for Allied Telesyn, ADC Telecom, Nortel, where I implemented 10/100/1000 Ethernet. MSEE from the University of Minnesota 2 2

3 Renesas Technology and Solution Portfolio Microcontrollers & Microprocessors #1 Market share worldwide * ASIC, ASSP & Memory Advanced and proven technologies Solutions for Innovation Analog and Power Devices #1 Market share in low-voltage MOSFET** * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 ** Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis). 3 In the session 110C, Renesas Next Generation Microcontroller and Microprocessor Technology Roadmap, Ritesh Tyagi introduces this high level image of where the Renesas Products fit. The big picture. 3

4 Renesas Technology and Solution Portfolio Microcontrollers & Microprocessors #1 Market share worldwide * ASIC, ASSP & Memory Advanced and proven technologies Solutions for Innovation Analog and Power Devices #1 Market share in low-voltage MOSFET** * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 ** Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis). 4 This is where our session, 220L Hands-on Embedded Ethernet Design with an Open Source TCP/IP Stack, is focused within the Big picture of Renesas Products 4

5 Microcontroller and Microprocessor Line-up Superscalar, MMU, Multimedia Up to 1200 DMIPS, 45, 65 & 90nm process Video and audio processing on Linux Server, Industrial & Automotive High Performance CPU, Low Power Up to 500 DMIPS, 150 & 90nm process 600uA/MHz, 1.5 ua standby Medical, Automotive & Industrial High Performance CPU, FPU, DSC Up to 165 DMIPS, 90nm process 500uA/MHz, 2.5 ua standby Ethernet, CAN, USB, Motor Control, TFT Display Legacy Cores Next-generation migration to RX General Purpose Up to 10 DMIPS, 130nm process 350 ua/mhz, 1uA standby Capacitive touch Ultra Low Power Up to 25 DMIPS, 150nm process 190 ua/mhz, 0.3uA standby Application-specific integration Embedded Security Up to 25 DMIPS, 180, 90nm process 1mA/MHz, 100uA standby Crypto engine, Hardware security 5 Here are the MCU and MPU Product Lines, I am not going to cover any specific information on these families, but rather I want to show you where this session is focused 5

6 Microcontroller and Microprocessor Line-up Superscalar, MMU, Multimedia Up to 1200 DMIPS, 45, 65 & 90nm process Video and audio processing on Linux Server, Industrial & Automotive High Performance CPU, Low Power Up to 500 DMIPS, 150 & 90nm process 600uA/MHz, 1.5 ua standby Medical, Automotive & Industrial High Performance CPU, FPU, DSC Up to 165 DMIPS, 90nm process 500uA/MHz, 2.5 ua standby Ethernet, CAN, USB, Motor Control, TFT Display RX Legacy Cores Next-generation migration to RX Ethernet, CAN, USB, UART, SPI, IIC General Purpose Up to 10 DMIPS, 130nm process 350 ua/mhz, 1uA standby Capacitive touch Ultra Low Power Up to 25 DMIPS, 150nm process 190 ua/mhz, 0.3uA standby Application-specific integration Embedded Security Up to 25 DMIPS, 180, 90nm process 1mA/MHz, 100uA standby Crypto engine, Hardware security 6 These are the products where this presentation applies 6

7 Innovation Internet Ethernet Ethernet Ethernet Ethernet 7 Ethernet innovation is everywhere. Especially in today's connected home. Let s look at the TV in my living room. I have ATT U-Verse. It is connected to my TV. The picture comes from over broadband Ethernet. Even HD content and sound. The U-verse box connected to my large screen TV and my home theater system. But, what can be cooler? Well, we all have busy schedule. I set up the U-Verse box to record the shows I want to watch later. I can even do that from my PC at work. You can see that I am a big soccer fan. The screen shot above is actually from my box. Of course, I have a high-speed internet access too. What else. I have a Netflix account. I can connect it and stream movies to my TV using my PlayStation. I can use my PlayStation as a media player as well. We can look at our digital pictures and listen MP3 music collection. What makes all this possible? Key contributing factor is Ethernet. 7

8 Our Ethernet Solution Renesas provides you a complete set of FREE tools and low cost MCUs with Ethernet peripheral. Embedded Ethernet connectivity is very easy to achieve when you have Renesas as a partner! 8 The perception in the market place is that embedded Ethernet is hard to achieve. The cost of TCP/IP stacks, development tools, and the time to learn the technology all make it very difficult to design products that talk to each other over Ethernet. However, with a low cost Ethernet enabled MCU and the software freely available in the Open Source community embedded Ethernet is very easy to achieve. Renesas has a complete set of solution for H8S/2472 Ethernet connectivity. 8

9 Agenda OSI network layers and RX62N RX62N Ethernet peripherals uip TCP/IP stack Freely available tools Lab Exercises Questions Feedback Form 9 9

10 Key Takeaways By the end of this session you will be able to: Identify the features of Renesas Ethernet peripherals Find out about freely available networking tools Understand pros an cons of uip TCP/IP stack Get a functional sample project to take home with you 10 10

11 OSI Networking Model 11 Physical Layer: Deals with elements involved with actual transmission and reception of signals on the communications medium. The exact nature of the devices implementing the physical layer is a function of the design of the communications channel and the physical medium itself. Data Link Layer: Provides reliable transit of data across a physical network link. Defines framing, physical addressing, network topology, error detection. Data link layer must separate (delimit) discrete message transmissions (frames) in the physical layer. Physical addressing (as opposed to network addressing) defines how devices are addressed at the data link layer. Network topology consists of the data link layer specifications that often define how devices are to physically connected such as in a bus or a ring topology. Error detection notifies upper layer protocols that a transmission error has occurred, and the sequencing of data frames reorders frames that are transmitted out of sequence. Finally, flow control moderates the transmission of data so that the receiving device is not overwhelmed with more traffic than it can handle at one time. Network Layer: While data link layer is concerned with the direct exchange of frames among stations on a single communications channel, the network layer is responsible for station-to-station data delivery across multiple data links. Transport Layer: Provides its clients with a perfect pipe : an error free, sequenced, guaranteed-delivery message service that allows end-to-end communications between stations across a network. Session Layer: Provides for the establishment of communications sessions process-to-process. It may deal with authentication and access control. Presentation Layer: Provides variety of coding and conversion functions that are applied to application layer data. These functions ensure that information sent from the application layer of one system would be readable by the application layer of another system. EBCDIC to ASCII conversions, standard encryption schemes are part of its responsibilities. Application Layer: is the OSI layer closest to the end user. 11

12 RX62N and OSI Network Model Layer RDKRX62N Open Source uip TCP/IP Stack Application Presentation Session Transport Network Data Link National DP8364 IEEE 1588 PHY RX62N MAC & Driver FW Physical 12 RX62N does not have an integrated physical interface. RSKRX62N uses SMSC LAN 8700i PHY chip to connect to physical medium. The interface between the RX62N and the PHY chip is Media Independent Interface (MII). R62N also supports Reduced Media Independent Interface (RMII) that reduces the number of pins required to connect a MAC layer device to a PHY layer device. At the Data link layer, the Ethernet peripheral (Ethernet controller and Ethernet Direct Memory Access Controller) provides Ethernet frame processing in accordance to IEEE specification. Layers 3 and above are implemented by the open source uip TCP/IP stack. 12

13 Ethernet Controller Ethernet and IEEE frames Type encapsulation Length encapsulation Automatic frame checksum 10 and 100 Mbps operation Half and full duplex modes PAUSE MAC layer flow control (IEEE 802.3x) When in full duplex mode Wake-On-LAN (WOL) Magic Packet Detection MII and RMII PHY layer interface 13 EtherC supports both the Ethernet (type encapsulation) and the IEEE (length encapsulation) frames. The Ethernet frame contains a field called TYPE. Depending on the value of TYPE field, rest of the frame can be interpreted differently. Type Encapsulation: TYPE values between 0x0600 to 0xFFFF. Common types are IPv4, IPv6, and ARP. Length Encapsulation: TYPE values between 0x0000 to 0x05DC (1500 the maximum length of DATA field). Although this is the original IEEE format, this encapsulation is not commonly used anymore. Length encapsulation can also carry other types of frames like Logical Link Control (LLC). EtherC is capable of 10/100 Mbps operation in half and full duplex. MAC features of Collision Sense Multiple Access (CSMA) are disabled for full duplex systems. A full duplex Ethernet interface does not detect collisions, and ignores carries sense for the purpose of deferring its transmission. A full duplex network therefore requires an explicit flow control mechanism to allow a device to throttle a congested end station. For that end, EtherC can automatically generate PAUSE frames in full duplex mode upon reaching a configurable receive threshold or manually by software control. Wake-On-LAN feature allows low power system operation. Upon detection of Magic Packets rest of the MCU is activated. Magic Packet is a broadcast frame with 16 repetitions of the destination node s MAC address. 13

14 Ethernet Direct Memory Access Controller E-DMAC Directly connected to Ethernet Controller Transfer data between Ethernet Controller and memory Block transfers for efficient system bus utilization Support single frame and multi-buffer operation No need for large single buffers Multiple buffers can handle longer frames Totally automated Transmit and receive buffer management Driver provided as part of the lab Descriptors to define and control the buffers 14 E-DMAC makes use of direct memory access controller and moves data between the EtherC and the memory reducing CPU load. E-DMAC is directly connected to EtherC. Received frames are transferred from EtherC to an area of RAM pointed by receive descriptors in the E-DMAC. A similar operation is performed for transmit frames by moving them from RAM into EtherC through E-DMAC. If a given frame fits into one buffer, it is called single frame operation. However, if the frame length is larger than the buffer size, E-DMAC performs multi-buffer operation to form the frame and process it. All these actions are automatically done by the E-DMAC and buffer pointers are updated as necessary. The driver in this lab uses 8 transmit and 8 receive buffers of 256 bytes each. Therefore 2KB is used for transmit and 2KB for receive buffers. These buffers are managed by 8 transmit and 8 receive descriptors (buffer pointers) and each descriptor points to the next and the last descriptor points to the first one forming a circular buffer construct. 14

15 Ethernet Direct Memory Access Controller E-DMAC Extensive information for buffer control On-chip or external buffers Circular buffers Automated operation 15 This slide shows how circular buffers are constructed for E-DMAC. Each transmit and receive descriptor has necessary information about its own buffer and a pointer to it. By linking these descriptors you form linked list of buffers. The last descriptor points back to the first one creating a circular buffer list. The descriptors and the buffers can either be on chip or external. Both big and little endian memory operation are supported by the driver software. 15

16 Ethernet Controller E-DMAC Working Together 16 Now that we have seen the two Ethernet peripherals that make up the Ethernet block, let s take a look at how they all work together. In this animation, system RAM is internal to the RX62N. if required however, RX62N can be used with an external RAM providing a larger receive and transmit buffers for high end applications. We also have seen in previous slide that E-DMAC can work with either internal or external RAM. When an Ethernet data is transmitted, software driver updates the transmit descriptor control information and writes the data into transmit buffers pointed by the transmit descriptors. (Click mouse) Depended on the length of data, one or more transmit buffers and descriptors are used. For example if the transmit buffers are 256 bytes long and the data length is 500 bytes, 2 transmit buffers are needed. E-DMAC then reads the descriptor control information and moves the data from transmit buffers into its transmit FIFO. (Click mouse) This operation is completely under the control of E-DMAC and the CPU is free to do other tasks. (Click mouse) Ethernet Controller takes transmit data from E-DMAC s transmit FIFO, creates a complete Ethernet frame and transmits it to physical device through Media Independent Interface. (Click mouse) Ethernet Controller confirms with IEEE Ethernet standard when transmitting the frame. Reception of an Ethernet frame is the same but in reverse. Received frame is checked against destination address and any CRC errors. If the destination address matches and there is no CRC error, frame is put into E-DMAC s receive FIFO. E-DMAC then moves the received data into receive buffers pointed by the receive descriptors. The length of received data determines the number of receive descriptors and receive buffers used. 16

17 Questions? True/False Ether Controller is responsible for moving Ethernet data to/from system memory False. This is done by E-DMAC. Main responsibility of Ethernet Controller is transmission and reception of Ethernet frames. E-DMAC can work with internal and external RAM True. There is no limitation on memory space for E-DMAC operations. Ethernet Controller and E-DMAC function together to reduce CPU load True. For example while Ethernet Controller is busy receiving data, E-DMAC can move them to system RAM without loading the CPU. Renesas Ethernet peripherals are almost the same across the different families True. This allows code re-use and easy migration to other Renesas Ethernet devices 17 17

18 Features of uip TCP/IP Stack Perfect solution for simple applications Small footprint Works on 8-bit to 32-bit MCUs Needs only a timer peripheral No RTOS required High-level applications supported ARP, IP, ICMP (ping), TCP, DHCP, Telnet, DNS Web server and client Supported by active community of developers Developed by Adam Dunkels at Swedish Institute of Computer Science Free to use and distribute 18 We used open source uip for the implementation of TCP/IP protocol stack in this lab. uip TCP/IP stack is a perfect solution for simple embedded Ethernet applications. It does not require an RTOS and it occupies very small flash and RAM size. Only additional peripheral needed is a simple timer for processing periodic events. uip supports various high level applications. Simple Web server and Web client applications are part of the standard uip distribution. DHCP is another application that comes with uip and it is utilized within the lab. Other high level applications are Address Resolution Protocol (ARP), Domain Name Server (DNS) and Simple Mail Transfer Protocol (SMTP). These applications can be easily included into exiting demonstration project or integrated with your own application. 18

19 Things to Consider with uip TCP/IP Stack Single TCP segment in flight Lower throughput with delayed ACK TCP receivers Fixes: Use uip-split module Disable delayed ACK at the receiver Single TCP and UDP application Only one TCP/UDP application supported Fixes: Add a multiplexer layer Service connections based on TCP/UDP ports Are these a problem? YOU DECIDE! 19 Some of thing to consider when using uip TCP/IP protocol are uip allows one TCP segment in flight at a given time and only one TCP and UDP applications are supported with the standard distribution. Due to the small RAM buffer design constraint, uip keeps only one TCP segment in transit and requires an immediate ACK for the segment just transmitted. If the TCP receiver on the other end is implementing delayed ACK algorithm, this immediate ACK will not be sent. ACKs from these receivers are usually sent after reception of 2 TCP segments or if no segment is received within a specific amount of time frame. This time frame is typically 200ms but can be as high as 500ms. One way to fix this issue is to use uip-split module that divides the maximum sized outgoing TCP segments into two. Another fix is to disable delayed ACK algorithm at the TCP receiver. Another consideration is that uip supports only one TCP and one UDP applications. For example this lab software supports a Web server and a DHCP client. Web server runs on TCP and DHCP on UDP. If you want to add another TCP or UDP application, a multiplexer layer based on the connection port number must be added. Of course none of the are a limitation of the RX62N but how the uip TCP/IP stack is implemented. 19

20 Questions? True/False uip works with 8-bit to 32-bit MCUs True. uip TCP/IP stack scales from low to high end MCUs. uip requires a DMA engine to run False. The only peripheral needed is a simple timer uip comes with several application layer software True. DHCP, Web server and client are some of them uip supports delayed ACK TCP segments False. Each TCP segment must be ACK ed before another transmitted

21 Freely Available Tools Wireshark De facto network protocol analyzer Extensive analysis of frames Freely available from Fping ICMP (ping) message tests the connectivity to another device Fping builds on DOS ping utility with more options Freely available from html 21 Wireshark is the industry standard network protocol analyzer. You will see in the lab that different protocols are color coded differently for easy identification. You can apply filters to zoom in on a specific MAC or IP address or a protocol you want to analyze. Fping (short for fast ping) is the other open source tool we will use in the lab. It sends ICMP (ping) messages and processes the responses received. Ping messages are network layer packets that test the connectivity to another node. Fping has a lot more features than the DOS ping command utility and the time between the two ping messages can be as short as 1ms as opposed to 1s in DOS ping. 21

22 Lab Exercises 22 22

23 General Notes on Lab Exercises Refer to lab handout There are questions in lab handout Answers to questions are at the end Total of 4 lab exercises About 15 minutes each 23 After this short summary and overview, it is time to start on lab exercises. Couple notes before we start the lab. All exercises except exercise 7 use LEDs to show which task is currently running. Since tasks switch in and out quickly LEDs may flicker and may not be fully bright. The more a task stays in running state the more its LED stays on. This way you can observe the LEDs and can get a feel for which ones are running and how much. Except exercise 7 all labs also collect run time statistics information that is printed out through HEW debug console every 10 seconds. You can compare you visual observation with this statistics. 23

24 Lab Exercises You can start the lab now 24 24

25 Innovation You create the innovation. Renesas is here to help. Let s build it together! 25 We work with FreeRTOS and port it to our MCU platforms. Several our solutions are already using FreeRTOS as an enabler for complex software applications. We also partner with various RTOS vendor companies and bring their solutions to you so you can build the next space shuttle! 25

26 Questions? 26 26

27 Thank You! 27 27

28 Renesas Electronics America Inc. 28