Indian Streams Research Journal
|
|
- Duane Wilkins
- 6 years ago
- Views:
Transcription
1 Vol 4 Issue 5 June 2014 ISSN No : ORIGINAL ARTICLE International Multidisciplinary Research Journal Indian Streams Research Journal Executive Editor Ashok Yakkaldevi Editor-in-Chief H.N.Jagtap
2 Welcome to ISRJ RNI MAHMUL/2011/38595 ISSN No Indian Streams Research Journal is a multidisciplinary research journal, published monthly in English, Hindi & Marathi Language. All research papers submitted to the journal will be double - blind peer reviewed referred by members of the editorial board.readers will include investigator in universities, research institutes government and industry with research interest in the general subjects. International Advisory Board Flávio de São Pedro Filho Federal University of Rondonia, Brazil Kamani Perera Regional Center For Strategic Studies, Sri Lanka Janaki Sinnasamy Librarian, University of Malaya Romona Mihaila Spiru Haret University, Romania Delia Serbescu Spiru Haret University, Bucharest, Romania Anurag Misra DBS College, Kanpur Titus PopPhD, Partium Christian University, Oradea,Romania Mohammad Hailat Dept. of Mathematical Sciences, University of South Carolina Aiken Abdullah Sabbagh Engineering Studies, Sydney Ecaterina Patrascu Spiru Haret University, Bucharest Loredana Bosca Spiru Haret University, Romania Fabricio Moraes de Almeida Federal University of Rondonia, Brazil George - Calin SERITAN Faculty of Philosophy and Socio-Political Sciences Al. I. Cuza University, Iasi Editorial Board Hasan Baktir English Language and Literature Department, Kayseri Ghayoor Abbas Chotana Dept of Chemistry, Lahore University of Management Sciences[PK] Anna Maria Constantinovici AL. I. Cuza University, Romania Horia Patrascu Spiru Haret University, Bucharest,Romania Ilie Pintea, Spiru Haret University, Romania Xiaohua Yang PhD, USA...More Pratap Vyamktrao Naikwade Iresh Swami ASP College Devrukh,Ratnagiri,MS India Ex - VC. Solapur University, Solapur R. R. Patil Head Geology Department Solapur University,Solapur Rama Bhosale Prin. and Jt. Director Higher Education, Panvel Salve R. N. Department of Sociology, Shivaji University,Kolhapur N.S. Dhaygude Ex. Prin. Dayanand College, Solapur Narendra Kadu Jt. Director Higher Education, Pune K. M. Bhandarkar Praful Patel College of Education, Gondia Sonal Singh Vikram University, Ujjain Rajendra Shendge Director, B.C.U.D. Solapur University, Solapur R. R. Yalikar Director Managment Institute, Solapur Umesh Rajderkar Head Humanities & Social Science YCMOU,Nashik S. R. Pandya Head Education Dept. Mumbai University, Mumbai Govind P. Shinde Bharati Vidyapeeth School of Distance Education Center, Navi Mumbai Chakane Sanjay Dnyaneshwar Arts, Science & Commerce College, Indapur, Pune Awadhesh Kumar Shirotriya Secretary,Play India Play,Meerut(U.P.) G. P. Patankar Alka Darshan Shrivastava S. D. M. Degree College, Honavar, Karnataka Shaskiya Snatkottar Mahavidyalaya, Dhar Maj. S. Bakhtiar Choudhary Director,Hyderabad AP India. S.Parvathi Devi Ph.D.-University of Allahabad Sonal Singh, Vikram University, Ujjain Rahul Shriram Sudke Devi Ahilya Vishwavidyalaya, Indore S.KANNAN Annamalai University,TN Satish Kumar Kalhotra Maulana Azad National Urdu University Address:-Ashok Yakkaldevi 258/34, Raviwar Peth, Solapur Maharashtra, India Cell : , Ph No: ayisrj@yahoo.in Website:
3 Indian Streams Research Journal ISSN Volume-4 Issue-5 June-2014 Available online at EFFICIENT DESIGN OF COMPUTATIONAL SYSTEM USING REVERSIBLE LOGIC ON FPGA Nitin B. Kodam and P. C. Bhaskar Mtech Student, Electronics Technology, Department of Technology, Shivaji University, Maharashtra, India. P.G Coordinator, Electronics Technology, Department of Technology, Shivaji University, Maharashtra, India. Abstract:The Conventional digital circuits dissipate (ktln2) joules of heat energy when losing one bit of information. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically because the energy dissipation in any conventional system is proportional to the number of bits lost during processing of bit. The reversible circuits do not lose any bits of information because there is one-to-one mapping between inputs and outputs. In the reversible logic we can, not only get the output from input but we can also retrieve input from output. Thus we designed an Efficient Computational system of reversible circuits for an acquisition of analogy data converting into digital data, computing the data and storing a data on FPGA. The system is based on reversible logic hence it dissipate less power than the conventional logical system. The system consist of ADC unit hence the real time data can be converted to digital data and further processed by ALU unit,the required data can be stored and retrieved into 64 bit designed memory unit. Hence this can be used in many day to day real life electronics application.such as Voice recording system, automation system, monitoring system, live video streaming system, etc. Keywords:Reversible Logic, Computational system, Data acquisition unit, ALU (Arithmetic and logical) unit, Memory unit. I.INTRODUCTION The reversible logic has gathered a great attention in these recent years because of its reducing power dissipation in many applications. The reversible logic can be used in many application such as in low power CMOS design, Quantum computing machines, communication, and optical communication nanotechnology and in many for applications. In the conventional digital circuits when one bit of information is loosed then it dissipate (ktln2) joules of heat energy[1] Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically because the amount of energy loss is exactly equal to the number of bit loosed. The reversible circuit do not loss any bit of information during computation of bits hence there will be no any loss of energy. In reversible circuit there is a one-to-one mapping between inputs and outputs. In order to achieve low power designs reversible circuits are used.an Efficient Computational system design of reversible circuits consist of a data acquisition, Computation and storage unit [2][3].A reversible data acquisition system consists of a reversible analog-to digital converter which will convert analog signal into digital form, were 8:3 reversible priority encoder encodes the 8 bit digital data into 3 bits [4][5].The Reversible Computation design is basically an ALU. In which various sub modules such as adder/subtractor, multiplier and a logical unit are designed. The storage unit is 64 bit were reversible logic designed D FF is used which is used to store the computation unit outputs. On the basis of control signal, the required result is provided at the output.[6]. REVERSIBLE GATE Reversible logic has the feature to generate one to one correspondence between its input and output and a reversible gate is an n n data stripe block which uniquely maps between input vectors Iv= (I0, I1,..., In) and output vector O v= (O0, O1,..., On) denoted as Iv O v Nitin B. Kodam and P. C. Bhaskar, EFFICIENT DESIGN OF COMPUTATIONAL SYSTEM USING REVERSIBLE LOGIC ON FPGA Indian Streams Research Journal Volume 4 Issue 5 June 2014 Online & Print 1
4 . Efficient Design Of Computational System Using Reversible Logic On Fpga Other Basic Reversible Gate NOT Gate, Feynman / CNOT, Toffoli Gate (TG), FeynmanDouble Gate (F2G), Reversible Toffoli gate (DPG), Peres Gate (PG), Fredkin Gate (FRG), Double Peres (Dperes) Gate [9]. 2.PROPOSED SYSTEM Figure 1. Proposed computational system The many existing irreversible circuits when losing one bit of information dissipates (ktln2) joules of heat energy similarly the traditional data acquisition system and Computational unit consume more power than reversible system. While designing these irreversible circuits we require more gates and almost all the millions of gates used to perform logical operations in a conventional computer are irreversible. So any lose of information will drastically increases power consumption in a conventional system. The increase in clock frequency to achieve greater speed and increase in number of transistors packed onto a chip to achieve complexity of a conventional system results in increased power consumption.these existing circuits also require more constant inputs and these circuits generate more garbage outputs than this reversible gates.to mitigate this problem we suggest the Reversible Computational system logic design which individually has less power dissipation and than the conventional system. The proposed work consist of designing data acquisition, Computational unit (ALU) and Storage system 4. HARDWARE IMPLEMENTATION The hardware designed on FPGA Spartan 3E and the system design incorporates three parts 1.Data acquisition unit 2. Computation (ALU) unit 3. Storage unit a)hardware for Computation system Here the Spartan 3E board has been used to develop the computational unit. The unit takes the input from a comparator circuit and do future reversible processing. Indian Streams Research Journal Volume 4 Issue 5 June
5 . Efficient Design Of Computational System Using Reversible Logic On Fpga Figure3. Computation circuit design. The Reversible system consists a comparator circuit that compares the analogy input provided by potentiometer with the reference voltage and generates eight bit binary output.and this output is further encoded by reversible priority encoder that encodes this data into three bits.for Further computation with this data in (ALU) the second three bit operand is provided by three sliding switches and the operation for computation is decided by next three sliding switch. The designed eight byte reversible memory stores this computational output in eight different locations. The system also consist of two more sliding switches in which one switch is used to show the priority encoded data on to the three of eight LEDs and the last sliding switch is use for generating clock or enable signal for the system. The computation output stored in differed memory location can be retrieve by sliding switch as per the corresponding memory location address 5.SOFTWARE IMPLEMENTATION For any hardware to work correctly as desired it is necessary to embed required code written in particular language using associated software. As in this system FPGA is incorporated, software s used to write code are namely Xilinx version is used. The design consists of three blocks manly data acquisition unit, ALU unit and memory unit. For designing this system different reversible logic gates are used and the individual gates have its quantum cost. Figure 2. Snapshot of RTL schematic of system 6.RESULT Indian Streams Research Journal Volume 4 Issue 5 June
6 . Efficient Design Of Computational System Using Reversible Logic On Fpga Figure 3. Behavioral simulation results of system To acquiring the results from designed computational system varies I/P are applied and required O/P is tested.here Structural modeling has been used for programming. Figure shows the simulated waveform for each and every input and output signals of the system.this results can be used by other developer for there future work.the system quantum cost is shown in table and power of utilisation of system is 0.082W which is analysed by Xpower estimator of xilinx tool Figure 4.Xpower estimator values 7. CONCLUSION Figure 5.Quantum cost of system The system consists of real time units such as analog to digital converter, ALU and memory unit. As this system is design based on reversible logic it minimize the power dissipation, so this unit in and all can be used in many real time applications such as Video recording, digital Cameras, mobiles, and in wide variety of applications domains like Nanotechnology, Digital signal, processing, Cryptography, Communications. Optical computing, advanced computing 8.REFERENCES 1.Landauer R., (1961) Irreversibility and heat generation in the computing process. IBM J. Research and Development, 5(3): Lafifa Jamal, Farah Sharmin,Md. Abdul Mottalib, Hafiz Md. Hasan Babu Design and Minimization of Reversible Circuits for a Data Acquisition and Storage System IJET Volume 2 No. 1, January, 2012 Indian Streams Research Journal Volume 4 Issue 5 June
7 . Efficient Design Of Computational System Using Reversible Logic On Fpga 3. Jun-Chao Wang I, Yu Pang I, Yang Xia A Bcd Priority Encoder Designed By Reversible Logic National Natural Science Foundation of China under the grant No , and by the Natural Science Foundation of Chongqing under the grant No. CSTC 2011 BB 2142 and No. KJl Majid Haghparast, Somayyeh Jafarali Jassbi, Keivan Navi and Omid Hashemipour,' Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology World Applied Sciences Journal 3 (6): , 2008 ISSN IDOSI Publications, Raghava Garipelly, P.Madhu Kiran, A.Santhosh Kumar,' A Review on Reversible Logic Gates and their Implementation. Volume 3, Issue 3, March Md. Sazzad Hossain, Md. Rashedul Hasan Rakib, Md. Motiur Rahman,A. S. M. Delowar Hossain and Md. Minul Hasan A New Design Technique Of Reversible BCD adder Based On Nmos Withpass Transistor Gates 7.Lafifa Jamal,2Farah Sharmin,3Md. Abdul Mottalib,4Hafiz Md. Hasan BabuDesign and Minimization of Reversible Circuits for a Data Acquisition and Storage System, International Journal of engineering and Technology Volume 2 No. 1, January, Md. Saiful Islam, Muhammad Mahbubur Rahman, Zerina begum, and Mohd. Zulfiquar Hafiz Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry- Skip Adders, MASAUM Journal of Basic and Applied Sciences, Vol. 1, No. 3, October Reversible Logic Gates and their Implementation ISSN , ISO 9001:2008 Certified Journal, Volume 3, Issue 3, March Saiful Islam and Rafiqul Islam Minimization of Reversible Adder circuits, Asian Journal of Information Technology4 (12) , Rangaraju H G et al, Low Power Reversible Parallel Binary Adder/Subtractor, International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September Himanshu Thapliyal and M B Srinivas, Novel Design and Reversible Logic Synthesis of Multiplexer Based Full Adder and Multipliers, Forty Eight Midwest Symposium on Circuits and Systems, vol. 2, pp Yingtao Jiang, Abdulkarim Al-Sheraidah, Yuke Wang, Edwin Sha, and Jin-Gyun Chung, A Novel Multiplexer-Based Low-Power Full Adder, IEEE Transactions on circuits and systems -II: express briefs,vol. 51,No. 7 July Dmitri Maslov and Gerhard W. Dueck, Reversible Cascades With Minimal Garbage, IEEE Transaction on computeraided design of integrated circuits and systems, vol. 23, No. 11, November Alberto Nannarelli and Tom {s Lang, Low-Power Divider, IEEE Transaction on computers, vol... 48, No. 1, January Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, and John P. Hayes, Synthesis of Reversible Logic Circuits,IEEE Transaction on computer-aided design of integrated circuits and systems, vol.22, No. 6, June William C. Athas, Lars J,Svensson, Jeffrey G. koller, Nestoras Tzartzanis, and Eric Ying Chin Chou, Low-power Digital Systems based on Adiabatic-Switching principle, IEEE Transactions on VLSI systems, Vol. 2, No. 4, December Rekha K James, Shahana T K, K Poulose Jacob, and Sreela Sasi, A New Look at Reversible Logic Implementation of Decimal Adder, the International Symposium on System-On-Chip, Lihui Ni, Zhijin Guan, and Wenying Zhu, A General Method of Constructing the Reversible Full-Adder, Third International Symposium on Intelligent Information Technology and Security Informatics, pp , T Toffoli, Reversible Computing, Technical MemoMIT/LCS/TM-151, MIT Lab for Computer Science, 1980.[20]. Bart Desoete, Alexis De Vos A reversible carry-look-ahead adder using control gates, Science direct, INTEGRATION, the VLSI journal 33 (2002) Indian Streams Research Journal Volume 4 Issue 5 June
8 Publish Research Article International Level Multidisciplinary Research Journal For All Subjects Dear Sir/Mam, We invite unpublished Research Paper,Summary of Research Project,Theses,Books and Book Review for publication,you will be pleased to know that our journals are Associated and Indexed,India International Scientific Journal Consortium OPEN J-GATE Associated and Indexed,USA Google Scholar EBSCO DOAJ Index Copernicus Publication Index Academic Journal Database Contemporary Research Index Academic Paper Databse Digital Journals Database Current Index to Scholarly Journals Elite Scientific Journal Archive Directory Of Academic Resources Scholar Journal Index Recent Science Index Scientific Resources Database Directory Of Research Journal Indexing Indian Streams Research Journal 258/34 Raviwar Peth Solapur ,Maharashtra Contact Website :
EFFICIENT DESIGN OF COMPUTATIONAL SYSTEM USING REVERSIBLE LOGIC ON FPGA
Indian Streams Research Journal ORIGINAL ARTICLE ISSN:-2230-7850 EFFICIENT DESIGN OF COMPUTATIONAL SYSTEM USING REVERSIBLE LOGIC ON FPGA Nitin B. Kodam and P. C. Bhaskar Mtech Student, Electronics Technology,
More informationGolden Research Thoughts
Vol Issue 8 Feb 205 ISSN No :223-5063 ORIGINAL ARTICLE International Multidisciplinary Research Journal Golden Research Thoughts Chief Editor DrTukaram Narayan Shinde ublisher MrsLaxmi Ashok Yakkaldevi
More informationReview Of Research Journal
Vol 7 Issue 3 Dec 2017 ISSN No : 2249-894X ORIGINAL ARTICLE Monthly Multidisciplinary Research Journal Review Of Research Journal Chief Editors Ashok Yakkaldevi A R Burla College, India Ecaterina Patrascu
More informationNovel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format Himanshu Thapliyal, Saurabh Kotiyal and M.B Srinivas Center for VLSI and Embedded System Technologies, International Institute
More informationReview Of Research Journal
Vol 4 Issue 4 Jan 2015 ISSN No : 2249-894X ORIGINAL ARTICLE Monthly Multidisciplinary Research Journal Review Of Research Journal Chief Editors Ashok Yakkaldevi A R Burla College, India Flávio de São Pedro
More informationDesign And Development of Efficient Reversible Floating Point Arithmetic unit
2015 Fifth International Conference on Communication Systems and Network Technologies Design And Development of Efficient Reversible Floating Point Arithmetic unit Jenil Jain Electronics Engineering Department,
More informationPrachi Sharma 1, Rama Laxmi 2, Arun Kumar Mishra 3 1 Student, 2,3 Assistant Professor, EC Department, Bhabha College of Engineering
A Review: Design of 16 bit Arithmetic and Logical unit using Vivado 14.7 and Implementation on Basys 3 FPGA Board Prachi Sharma 1, Rama Laxmi 2, Arun Kumar Mishra 3 1 Student, 2,3 Assistant Professor,
More informationPower Optimized Programmable Truncated Multiplier and Accumulator Using Reversible Adder
Power Optimized Programmable Truncated Multiplier and Accumulator Using Reversible Adder Syeda Mohtashima Siddiqui M.Tech (VLSI & Embedded Systems) Department of ECE G Pulla Reddy Engineering College (Autonomous)
More informationDesign And Implementation Of Reversible Logic Alu With 4 Operations
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p-ISSN: 2278-8735 PP 55-59 www.iosrjournals.org Design And Implementation Of Reversible Logic Alu With 4 Operations
More informationA Novel Implementation of Reversible Multiplexer Design Using MZI
A Novel Implementation of Reversible Multiplexer Design Using MZI Abstract: Atluri Sarath Raja M.Tech, Usha Rama Engineering College, Telaprolu, Vijayawada, Andhra Pradesh. Reversible logic; transforms
More informationDesign and Simulation of Power Optimized 8 Bit Arithmetic Unit using Gating Techniques in Cadence 90nm Technology
Design and Simulation of Power Optimized 8 Bit Arithmetic Unit using Gating Techniques in Cadence 90nm Technology Umashree.M.Sajjanar 1, Maruti.Lamani 2, Mr.Mahesh.B.Neelagar 3 1 PG Scholar, Dept of PG
More informationImplementation of Pipelined Architecture for AES Algorithm using Reversible Logic
International Journal of Emerging Engineering Research and Technology Volume 3, Issue 12, December 2015, PP 138-145 ISSN 2349-4395 (Print) & ISSN 2349-4409 (Online) Implementation of Pipelined Architecture
More informationReview Of Research Journal
Vol III Issue XII Sept 2014 ISSN No : 2249-894X ORIGINAL ARTICLE Monthly Multidisciplinary Research Journal Review Of Research Journal Chief Editors Ashok Yakkaldevi A R Burla College, India Flávio de
More informationKeywords: throughput, power consumption, area, pipeline, fast adders, vedic multiplier. GJRE-F Classification : FOR Code:
Global Journal of Researches in Engineering: F Electrical and Electronics Engineering Volume 14 Issue 6 Version 1.0 Type: Double Blind Peer Reviewed International Research Journal Publisher: Global Journals
More informationREALIZATION OF AN 8-BIT PROCESSOR USING XILINX
REALIZATION OF AN 8-BIT PROCESSOR USING XILINX T.Deepa M.E (Applied Electronics) Department of Electronics and Communication Engineering, Sri Venkateswara College of Engineering, Sriperumbudur, Chennai,
More informationKeywords: Soft Core Processor, Arithmetic and Logical Unit, Back End Implementation and Front End Implementation.
ISSN 2319-8885 Vol.03,Issue.32 October-2014, Pages:6436-6440 www.ijsetr.com Design and Modeling of Arithmetic and Logical Unit with the Platform of VLSI N. AMRUTHA BINDU 1, M. SAILAJA 2 1 Dept of ECE,
More informationRobust Reversible Multiplexer Design using. Mach-Zehnder Interferometer
Robust Reversible Multiplexer Design using Mach-Zehnder Interferometer M.Zaheer Ahmed #1, S.Md.Imran Ali #2, P.Nagashyam #3,T.S.D.V.Subbarao #4 # Assistant Professor, # Assitant Professor, # UG student,
More informationDesign of Double Precision Floating Point Multiplier Using Vedic Multiplication
Design of Double Precision Floating Point Multiplier Using Vedic Multiplication 1 D.Heena Tabassum, 2 K.Sreenivas Rao 1, 2 Electronics and Communication Engineering, 1, 2 Annamacharya institute of technology
More informationIntroduction. M Krishna* et al. ISSN: [IJESAT] [International Journal of Engineering Science & Advanced Technology]
Electronic Model of Human Brain using Verilog M.Krishna 1 M. umarani 2 1 & 2: Assistant Professor,Department of ECE,Geethanjali College of Engineering and Technology Abstract: Reversible logic has become
More informationDesign and Analysis of Kogge-Stone and Han-Carlson Adders in 130nm CMOS Technology
Design and Analysis of Kogge-Stone and Han-Carlson Adders in 130nm CMOS Technology Senthil Ganesh R & R. Kalaimathi 1 Assistant Professor, Electronics and Communication Engineering, Info Institute of Engineering,
More informationDesign, Analysis and Processing of Efficient RISC Processor
Design, Analysis and Processing of Efficient RISC Processor Ramareddy 1, M.N.Pradeep 2 1M-Tech., VLSI D& Embedded Systems, Dept of E&CE, Dayananda Sagar College of Engineering, Bangalore. Karnataka, India
More informationDesign of 2-Bit ALU using CMOS & GDI Logic Architectures.
Design of 2-Bit ALU using CMOS & GDI Logic Architectures. Sachin R 1, Sachin R M 2, Sanjay S Nayak 3, Rajiv Gopal 4 1, 2, 3 UG Students, Dept. of ECE New Horizon College of Engineering, Bengaluru 4 Asst.
More informationDESIGN AND IMPLEMENTATION OF ADDER ARCHITECTURES AND ANALYSIS OF PERFORMANCE METRICS
International Journal of Electronics and Communication Engineering and Technology (IJECET) Volume 8, Issue 5, September-October 2017, pp. 1 6, Article ID: IJECET_08_05_001 Available online at http://www.iaeme.com/ijecet/issues.asp?jtype=ijecet&vtype=8&itype=5
More informationLow Power Circuits using Modified Gate Diffusion Input (GDI)
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 5, Ver. II (Sep-Oct. 2014), PP 70-76 e-issn: 2319 4200, p-issn No. : 2319 4197 Low Power Circuits using Modified Gate Diffusion Input
More informationLVCMOS IO Standards Based Processor Specific Green Comparator Design
LVCMOS IO Standards Based Processor Specific Green Comparator Design 1 Chandrashekhar Patel, 2 Parth Gautam, 3 Priyanka Mehra, 4 Ankita Pundir, 5 Shivani Sharma 1,2,3,4,5 Dev Sanskriti Vishvavidyalaya
More informationDesigning an Improved 64 Bit Arithmetic and Logical Unit for Digital Signaling Processing Purposes
Available Online at- http://isroj.net/index.php/issue/current-issue ISROJ Index Copernicus Value for 2015: 49.25 Volume 02 Issue 01, 2017 e-issn- 2455 8818 Designing an Improved 64 Bit Arithmetic and Logical
More informationISSN Vol.02, Issue.11, December-2014, Pages:
ISSN 2322-0929 Vol.02, Issue.11, December-2014, Pages:1208-1212 www.ijvdcs.org Implementation of Area Optimized Floating Point Unit using Verilog G.RAJA SEKHAR 1, M.SRIHARI 2 1 PG Scholar, Dept of ECE,
More informationDesign and Implementation of Arbiter schemes for SDRAM on FPGA
Design and Implementation of Arbiter schemes for SDRAM on FPGA Priyanka C. Sankpal, Arun S. Tigadi, Dr. Hansraj Guhilot Abstract Memories are the storage devices, which typically work with single processing
More informationDesign and Analysis of 64 bit Multiplier using Carry Look Ahead Logic for Low Latency and Optimized Power Delay Product
Design and Analysis of 64 bit Multiplier using Carry Look Ahead Logic for Low Latency and Optimized Power Delay Product Gaurav Vashisht 1, Puneeta Dadhich 2 Dept. of VLSI, ACSD, C-DAC, Mohali, India 1
More informationArea-Time Efficient Square Architecture
AMSE JOURNALS 2015-Series: Advances D; Vol. 20; N 1; pp 21-34 Submitted March 2015; Revised Sept. 21, 2015; Accepted Oct. 15, 2015 Area-Time Efficient Square Architecture *Ranjan Kumar Barik, **Manoranjan
More informationReview on Floating Point Adder and Converter Units Using VHDL
Review on Floating Point Adder and Converter Units Using VHDL Abhishek Kumar 1, Mayur S. Dhait 2 1 Research Scholar, Agnihotri College of Engineering, Nagthana Road, Wardha (M.S), India 2 Professor, Department
More informationA Novel Architecture of Parallel Multiplier Using Modified Booth s Recoding Unit and Adder for Signed and Unsigned Numbers
International Journal of Research Studies in Science, Engineering and Technology Volume 2, Issue 8, August 2015, PP 55-61 ISSN 2349-4751 (Print) & ISSN 2349-476X (Online) A Novel Architecture of Parallel
More informationDESIGN AND PERFORMANCE ANALYSIS OF CARRY SELECT ADDER
DESIGN AND PERFORMANCE ANALYSIS OF CARRY SELECT ADDER Bhuvaneswaran.M 1, Elamathi.K 2 Assistant Professor, Muthayammal Engineering college, Rasipuram, Tamil Nadu, India 1 Assistant Professor, Muthayammal
More informationImplementation of FFT Processor using Urdhva Tiryakbhyam Sutra of Vedic Mathematics
Implementation of FFT Processor using Urdhva Tiryakbhyam Sutra of Vedic Mathematics Yojana Jadhav 1, A.P. Hatkar 2 PG Student [VLSI & Embedded system], Dept. of ECE, S.V.I.T Engineering College, Chincholi,
More informationRevLib: An Online Resource for Reversible Functions and Reversible Circuits
RevLib: An Online Resource for Reversible Functions and Reversible Circuits Robert Wille 1 Daniel Große 1 Lisa Teuber 1 Gerhard W. Dueck 2 Rolf Drechsler 1 1 Institute of Computer Science, University of
More informationPerformance Analysis of 64-Bit Carry Look Ahead Adder
Journal From the SelectedWorks of Journal November, 2014 Performance Analysis of 64-Bit Carry Look Ahead Adder Daljit Kaur Ana Monga This work is licensed under a Creative Commons CC_BY-NC International
More informationPipelined High Speed Double Precision Floating Point Multiplier Using Dadda Algorithm Based on FPGA
RESEARCH ARTICLE OPEN ACCESS Pipelined High Speed Double Precision Floating Point Multiplier Using Dadda Algorithm Based on FPGA J.Rupesh Kumar, G.Ram Mohan, Sudershanraju.Ch M. Tech Scholar, Dept. of
More informationVLSI Based 16 Bit ALU with Interfacing Circuit
Available online at www.ijiere.com International Journal of Innovative and Emerging Research in Engineering e-issn: 2394-3343 p-issn: 2394-5494 VLSI Based 16 Bit ALU with Interfacing Circuit Chandni N.
More informationPublished in: Proceedings of the 3rd International Symposium on Environment-Friendly Energies and Applications (EFEA 2014)
Aalborg Universitet SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA Bansal, Neha; Bansal, Meenakshi; Saini, Rishita; Pandey, Bishwajeet; Kalra, Lakshay; Hussain, Dil muhammed
More informationDesign of Parallel Self-Timed Adder
Design of Parallel Self-Timed Adder P.S.PAWAR 1, K.N.KASAT 2 1PG, Dept of EEE, PRMCEAM, Badnera, Amravati, MS, India. 2Assistant Professor, Dept of EXTC, PRMCEAM, Badnera, Amravati, MS, India. ---------------------------------------------------------------------***---------------------------------------------------------------------
More informationImplementation of Optical Reversible Multiplexer Using Mach-Zehnder Interferometer
Implementation of Optical Reversible Multiplexer Using Mach-Zehnder Interferometer Nuwairah Abdul Azeez M.Tech, Jyothishmati Institute of Technology & Science, Karimnagar, Telangana. Abstract: With the
More informationVLSI Implementation of High Speed and Area Efficient Double-Precision Floating Point Multiplier
VLSI Implementation of High Speed and Area Efficient Double-Precision Floating Point Ramireddy Venkata Suresh 1, K.Bala 2 1 M.Tech, Dept of ECE, Srinivasa Institute of Technology and Science, Ukkayapalli,
More informationImplementation of Optimized ALU for Digital System Applications using Partial Reconfiguration
123 Implementation of Optimized ALU for Digital System Applications using Partial Reconfiguration NAVEEN K H 1, Dr. JAMUNA S 2, BASAVARAJ H 3 1 (PG Scholar, Dept. of Electronics and Communication, Dayananda
More information[Sahu* et al., 5(7): July, 2016] ISSN: IC Value: 3.00 Impact Factor: 4.116
IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY SPAA AWARE ERROR TOLERANT 32 BIT ARITHMETIC AND LOGICAL UNIT FOR GRAPHICS PROCESSOR UNIT Kaushal Kumar Sahu*, Nitin Jain Department
More informationHigh Performance and Area Efficient DSP Architecture using Dadda Multiplier
2017 IJSRST Volume 3 Issue 6 Print ISSN: 2395-6011 Online ISSN: 2395-602X Themed Section: Science and Technology High Performance and Area Efficient DSP Architecture using Dadda Multiplier V.Kiran Kumar
More informationDesign and simulation of 4-bit ALU Design using GDI Technique for Low Power Application on Microwind 2.6K
Design and simulation of 4-bit ALU Design using GDI Technique for Low Power Application on Microwind 2.6K Mr.Arshadali Rahut Department of Electronics & Communication Engineering B.V.B College of Engineering
More informationMODULO 2 n + 1 MAC UNIT
Int. J. Elec&Electr.Eng&Telecoms. 2013 Sithara Sha and Shajimon K John, 2013 Research Paper MODULO 2 n + 1 MAC UNIT ISSN 2319 2518 www.ijeetc.com Vol. 2, No. 4, October 2013 2013 IJEETC. All Rights Reserved
More informationDesign and Development of Vedic Mathematics based BCD Adder
International Journal of Applied Information Systems (IJAIS) ISSN : 229-0868 Volume 6 No. 9, March 201 www.ijais.org Design and Development of Vedic Mathematics based BCD Adder C. Sundaresan School of
More informationDESIGN AND IMPLEMENTATION OF APPLICATION SPECIFIC 32-BITALU USING XILINX FPGA
DESIGN AND IMPLEMENTATION OF APPLICATION SPECIFIC 32-BITALU USING XILINX FPGA T.MALLIKARJUNA 1 *,K.SREENIVASA RAO 2 1 PG Scholar, Annamacharya Institute of Technology & Sciences, Rajampet, A.P, India.
More informationHemraj Sharma 1, Abhilasha 2
FPGA Implementation of Pipelined Architecture of Point Arithmetic Core and Analysis of Area and Timing Performances Hemraj Sharma 1, Abhilasha 2 1 JECRC University, M.Tech VLSI Design, Rajasthan, India
More informationA Modified Radix2, Radix4 Algorithms and Modified Adder for Parallel Multiplication
International Journal of Emerging Engineering Research and Technology Volume 3, Issue 8, August 2015, PP 90-95 ISSN 2349-4395 (Print) & ISSN 2349-4409 (Online) A Modified Radix2, Radix4 Algorithms and
More informationDesign of 16 bit Arithmetic and Logical Unit Using Vivado 14.7 and Implementation on Basys 3 FPGA Board
2016 IJSRSET Volume 2 Issue 5 Print ISSN: 2395-1990 Online ISSN : 2394-4099 Themed Section: Engineering and Technology Design of 16 bit Arithmetic and Logical Unit Using Vivado 14.7 and Implementation
More informationDesign of a Pipelined 32 Bit MIPS Processor with Floating Point Unit
Design of a Pipelined 32 Bit MIPS Processor with Floating Point Unit P Ajith Kumar 1, M Vijaya Lakshmi 2 P.G. Student, Department of Electronics and Communication Engineering, St.Martin s Engineering College,
More information32-bit Signed and Unsigned Advanced Modified Booth Multiplication using Radix-4 Encoding Algorithm
2016 IJSRSET Volume 2 Issue 3 Print ISSN : 2395-1990 Online ISSN : 2394-4099 Themed Section: Engineering and Technology 32-bit Signed and Unsigned Advanced Modified Booth Multiplication using Radix-4 Encoding
More informationArea Efficient, Low Power Array Multiplier for Signed and Unsigned Number. Chapter 3
Area Efficient, Low Power Array Multiplier for Signed and Unsigned Number Chapter 3 Area Efficient, Low Power Array Multiplier for Signed and Unsigned Number Chapter 3 3.1 Introduction The various sections
More informationFPGA-BASED DATA ACQUISITION SYSTEM WITH RS 232 INTERFACE
FPGA-BASED DATA ACQUISITION SYSTEM WITH RS 232 INTERFACE 1 Thirunavukkarasu.T, 2 Kirthika.N 1 PG Student: Department of ECE (PG), Sri Ramakrishna Engineering College, Coimbatore, India 2 Assistant Professor,
More informationA 4-bit Arithmetic and Logical Unit with fault detection capability using an informal testing process and tested using CPLD EPM7128SLC84-15
A 4-bit Arithmetic and Logical Unit with fault detection capability using an informal testing process and tested using CPLD EPM7128SLC84-15 1 Abhishek Singh, 2 Mohd. Arif, 3 Kalpita Agrawal, 4 Anshita
More informationHARDWARE IMPLEMENTATION OF LOSSLESS LZMA DATA COMPRESSION ALGORITHM
HARDWARE IMPLEMENTATION OF LOSSLESS LZMA DATA COMPRESSION ALGORITHM Parekar P. M. 1, Thakare S. S. 2 1,2 Department of Electronics and Telecommunication Engineering, Amravati University Government College
More informationNovel Design of Dual Core RISC Architecture Implementation
Journal From the SelectedWorks of Kirat Pal Singh Spring May 18, 2015 Novel Design of Dual Core RISC Architecture Implementation Akshatha Rai K, VTU University, MITE, Moodbidri, Karnataka Basavaraj H J,
More informationMach-Zehnder Interferometer Based All Optical Reversible NOR Gates
2012 IEEE Computer Society Annual Symposium on VLSI Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates Saurabh Kotiyal, Himanshu Thapliyal and Nagarajan Ranganathan Department of Computer
More informationDesign and Verification of Serial Peripheral Interface 1 Ananthula Srinivas, 2 M.Kiran Kumar, 3 Jugal Kishore Bhandari
Design and Verification of Serial Peripheral Interface ISSN: 2321-9939 Design and Verification of Serial Peripheral Interface 1 Ananthula Srinivas, 2 M.Kiran Kumar, 3 Jugal Kishore Bhandari 1,3 MTech Student,
More informationI. Introduction. India; 2 Assistant Professor, Department of Electronics & Communication Engineering, SRIT, Jabalpur (M.P.
A Decimal / Binary Multi-operand Adder using a Fast Binary to Decimal Converter-A Review Ruchi Bhatt, Divyanshu Rao, Ravi Mohan 1 M. Tech Scholar, Department of Electronics & Communication Engineering,
More informationDESIGN AND IMPLEMENTATION OF VLSI SYSTOLIC ARRAY MULTIPLIER FOR DSP APPLICATIONS
International Journal of Computing Academic Research (IJCAR) ISSN 2305-9184 Volume 2, Number 4 (August 2013), pp. 140-146 MEACSE Publications http://www.meacse.org/ijcar DESIGN AND IMPLEMENTATION OF VLSI
More informationDesign of Vedic Multiplier for Digital Signal Processing Applications R.Naresh Naik 1, P.Siva Nagendra Reddy 2, K. Madan Mohan 3
Design of Vedic for Digital Signal Processing Applications R.Naresh Naik 1, P.Siva Nagendra Reddy 2, K. Madan Mohan 3 1 P.G. Scholar (M. Tech), Dept. of ECE, Intell Engineering College, Anantapur 2 P.G.
More informationAn Efficient Design of Vedic Multiplier using New Encoding Scheme
An Efficient Design of Vedic Multiplier using New Encoding Scheme Jai Skand Tripathi P.G Student, United College of Engineering & Research, India Priya Keerti Tripathi P.G Student, Jaypee University of
More informationINTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) ISSN 0976 6464(Print) ISSN 0976 6472(Online) Volume 4, Issue 6, November - December, 2013, pp. 85-92 IAEME: www.iaeme.com/ijecet.asp
More informationDYNAMIC CIRCUIT TECHNIQUE FOR LOW- POWER MICROPROCESSORS Kuruva Hanumantha Rao 1 (M.tech)
DYNAMIC CIRCUIT TECHNIQUE FOR LOW- POWER MICROPROCESSORS Kuruva Hanumantha Rao 1 (M.tech) K.Prasad Babu 2 M.tech (Ph.d) hanumanthurao19@gmail.com 1 kprasadbabuece433@gmail.com 2 1 PG scholar, VLSI, St.JOHNS
More informationINTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY
INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY A PATH FOR HORIZING YOUR INNOVATIVE WORK DESIGN OF QUATERNARY ADDER FOR HIGH SPEED APPLICATIONS MS. PRITI S. KAPSE 1, DR.
More informationVLSI Implementation of Fast Addition Using Quaternary Signed Digit Number System
VLSI Implementation of Fast Addition Using Quaternary Signed Digit Number System JYOTI R HALLIKHED M.Tech student, VLSI Design & Embedded Systems APPA Institute of Engineering & Technology Gulbarga, Karnataka,
More informationDESIGN AND IMPLEMENTATION OF 8 BIT AND 16 BIT ALU USING VERILOG LANGUAGE
DESIGN AND IMPLEMENTATION OF 8 BIT AND 16 BIT USING VERILOG LANGUAGE MANIT KANTAWALA Dept. of Electronic & Communication Global Institute of Technology, Jaipur Rajasthan, India Abstract: In this Paper
More informationFPGA based Simulation of Clock Gated ALU Architecture with Multiplexed Logic Enable for Low Power Applications
IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 04, 2015 ISSN (online): 2321-0613 FPGA based Simulation of Clock Gated ALU Architecture with Multiplexed Logic Enable for
More informationDESIGN, LAYOUT AND SIMULATION OF 8 BIT ARITHMETIC AND LOGIC UNIT USING C5 PROCESS TECHNOLOGY
DESIGN, LAYOUT AND SIMULATION OF 8 BIT ARITHMETIC AND LOGIC UNIT USING C5 PROCESS TECHNOLOGY Priyal Grover 1, Assist. Prof. HemantVerma 2 1,2 Department of Electronics and Communication Engineering Technocrats
More informationThe Fast Fourier Transform Algorithm and Its Application in Digital Image Processing
The Fast Fourier Transform Algorithm and Its Application in Digital Image Processing S.Arunachalam(Associate Professor) Department of Mathematics, Rizvi College of Arts, Science & Commerce, Bandra (West),
More informationDESIGN & PERFORMANCE ANALYSIS OF 16 BIT RAM USING QCA TECHNOLOGY Sunita Rani 1, Naresh Kumar 2, Rashmi Chawla 3 1
DESIGN & PERFMANCE ANALYSIS OF 16 BIT RAM USING QCA TECHNOLOGY Sunita Rani 1, Naresh Kumar 2, Rashmi Chawla 3 1 Deptt.of Electronics & Communication Engg., BPSMV, Khanpur Kalan, Sonepat, Haryana, India
More informationIMPLEMENTATION OF LOW POWER AREA EFFICIENT ALU WITH LOW POWER FULL ADDER USING MICROWIND DSCH3
IMPLEMENTATION OF LOW POWER AREA EFFICIENT ALU WITH LOW POWER FULL ADDER USING MICROWIND DSCH3 Ritafaria D 1, Thallapalli Saibaba 2 Assistant Professor, CJITS, Janagoan, T.S, India Abstract In this paper
More informationInternational Journal of Advance Engineering and Research Development
Scientific Journal of Impact Factor (SJIF): 4.14 International Journal of Advance Engineering and Research Development Volume 3, Issue 11, November -2016 e-issn (O): 2348-4470 p-issn (P): 2348-6406 Review
More informationDesigning a RISC CPU in Reversible Logic
211 41st IEEE International Symposium on Multiple-Valued Logic Designing a RISC CPU in Reversible Logic Robert Wille Mathias Soeken Daniel Große Eleonora Schönborn Rolf Drechsler Institute of Computer
More informationVLSI ARCHITECTURE FOR NANO WIRE BASED ADVANCED ENCRYPTION STANDARD (AES) WITH THE EFFICIENT MULTIPLICATIVE INVERSE UNIT
VLSI ARCHITECTURE FOR NANO WIRE BASED ADVANCED ENCRYPTION STANDARD (AES) WITH THE EFFICIENT MULTIPLICATIVE INVERSE UNIT K.Sandyarani 1 and P. Nirmal Kumar 2 1 Research Scholar, Department of ECE, Sathyabama
More informationLOW POWER SRAM CELL WITH IMPROVED RESPONSE
LOW POWER SRAM CELL WITH IMPROVED RESPONSE Anant Anand Singh 1, A. Choubey 2, Raj Kumar Maddheshiya 3 1 M.tech Scholar, Electronics and Communication Engineering Department, National Institute of Technology,
More informationVLSI DESIGN OF REDUCED INSTRUCTION SET COMPUTER PROCESSOR CORE USING VHDL
International Journal of Electronics, Communication & Instrumentation Engineering Research and Development (IJECIERD) ISSN 2249-684X Vol.2, Issue 3 (Spl.) Sep 2012 42-47 TJPRC Pvt. Ltd., VLSI DESIGN OF
More informationA Novel Design of 32 Bit Unsigned Multiplier Using Modified CSLA
A Novel Design of 32 Bit Unsigned Multiplier Using Modified CSLA Chandana Pittala 1, Devadas Matta 2 PG Scholar.VLSI System Design 1, Asst. Prof. ECE Dept. 2, Vaagdevi College of Engineering,Warangal,India.
More informationDEVELOPMENT OF FPGA MICROBLAZE PROCESSOR AND GSM BASED HEART RATE MONITORING SYSTEM
DEVELOPMENT OF FPGA MICROBLAZE PROCESSOR AND GSM BASED HEART RATE MONITORING SYSTEM P. K. Gaikwad Department of Electronics, Willingdon College, Sangli, (M.S.), INDIA pawangaikwad2003@yahoo.co.in Abstract
More informationAn Efficient Hybrid Parallel Prefix Adders for Reverse Converters using QCA Technology
An Efficient Hybrid Parallel Prefix Adders for Reverse Converters using QCA Technology N. Chandini M.Tech student Scholar Dept.of ECE AITAM B. Chinna Rao Associate Professor Dept.of ECE AITAM A. Jaya Laxmi
More informationPERFORMANCE ANALYSES OF SPECULATIVE VIRTUAL CHANNEL ROUTER FOR NETWORK-ON-CHIP
PERFORMANCE ANALYSES OF SPECULATIVE VIRTUAL CHANNEL ROUTER FOR NETWORK-ON-CHIP Amit Kumar Lamba, M-tech Student Bharati B Sayankar Assistant professor Pankaj Agrawal Associate Professor Department of E
More informationMZI Implementation of Reversible Logic Gates, Multiplexers, Standard Functions and CLA Using Verilog HDL
MZI Implementation of Reversible Logic Gates, Multiplexers, Standard Functions and CLA Using Verilog HDL Mr.Rama Krishna A M-Tech Student, Department of ECE, Godavari Institute of Engineering and Technology,
More informationExact Template Matching using Graphs
Exact Template Matching using Graphs by Md. Mazder Rahman, Gerhard W. Dueck, and Joe Horton TR 13-224, April, 2013 Faculty of Computer Science University of New Brunswick Fredericton, NB, E3B 5A3 Canada
More informationPRIYANKA DAYAL 11/1 Shastari Nagar, Nakodar Road, Jalandhar, India.
PRIYANKA DAYAL 11/1 Shastari Nagar, Nakodar Road, Jalandhar, India. CELL 9465623550 E-MAIL priyanka23dayal@gmail.com, priyanka_dayal@ymail.com PROFILE Self-motivated when succeed, Optimistic, able to work
More informationDesign and Implementation of VLSI 8 Bit Systolic Array Multiplier
Design and Implementation of VLSI 8 Bit Systolic Array Multiplier Khumanthem Devjit Singh, K. Jyothi MTech student (VLSI & ES), GIET, Rajahmundry, AP, India Associate Professor, Dept. of ECE, GIET, Rajahmundry,
More informationPerformance of Constant Addition Using Enhanced Flagged Binary Adder
Performance of Constant Addition Using Enhanced Flagged Binary Adder Sangeetha A UG Student, Department of Electronics and Communication Engineering Bannari Amman Institute of Technology, Sathyamangalam,
More informationUNIT II - COMBINATIONAL LOGIC Part A 2 Marks. 1. Define Combinational circuit A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination
More informationDESIGN OF QUATERNARY ADDER FOR HIGH SPEED APPLICATIONS
DESIGN OF QUATERNARY ADDER FOR HIGH SPEED APPLICATIONS Ms. Priti S. Kapse 1, Dr. S. L. Haridas 2 1 Student, M. Tech. Department of Electronics, VLSI, GHRACET, Nagpur, (India) 2 H.O.D. of Electronics and
More informationDesign and Implementation of CVNS Based Low Power 64-Bit Adder
Design and Implementation of CVNS Based Low Power 64-Bit Adder Ch.Vijay Kumar Department of ECE Embedded Systems & VLSI Design Vishakhapatnam, India Sri.Sagara Pandu Department of ECE Embedded Systems
More informationDesign of a Floating-Point Fused Add-Subtract Unit Using Verilog
International Journal of Electronics and Computer Science Engineering 1007 Available Online at www.ijecse.org ISSN- 2277-1956 Design of a Floating-Point Fused Add-Subtract Unit Using Verilog Mayank Sharma,
More informationPerformance Analysis and Designing 16 Bit Sram Memory Chip Using XILINX Tool
Performance Analysis and Designing 16 Bit Sram Memory Chip Using XILINX Tool Monika Solanki* Department of Electronics & Communication Engineering, MBM Engineering College, Jodhpur, Rajasthan Review Article
More informationAn Efficient Designing of I2C Bus Controller Using Verilog
American International Journal of Research in Science, Technology, Engineering & Mathematics Available online at http://www.iasir.net ISSN (Print): 2328-3491, ISSN (Online): 2328-3580, ISSN (CD-ROM): 2328-3629
More informationISSN: (Online) Volume 2, Issue 10, October 2014 International Journal of Advance Research in Computer Science and Management Studies
ISSN: 2321-7782 (Online) Volume 2, Issue 10, October 2014 International Journal of Advance Research in Computer Science and Management Studies Research Article / Survey Paper / Case Study Available online
More informationHIGH PERFORMANCE QUATERNARY ARITHMETIC LOGIC UNIT ON PROGRAMMABLE LOGIC DEVICE
International Journal of Advances in Applied Science and Engineering (IJAEAS) ISSN (P): 2348-1811; ISSN (E): 2348-182X Vol. 2, Issue 1, Feb 2015, 01-07 IIST HIGH PERFORMANCE QUATERNARY ARITHMETIC LOGIC
More informationDESIGN AND IMPLEMENTATION OF FAST DECIMAL MULTIPLIER USING SMSD ENCODING TECHNIQUE
RESEARCH ARTICLE OPEN ACCESS DESIGN AND IMPLEMENTATION OF FAST DECIMAL MULTIPLIER USING SMSD ENCODING TECHNIQUE S.Sirisha PG Scholar Department of Electronics and Communication Engineering AITS, Kadapa,
More informationAn Area Efficient Mixed Decimation MDF Architecture for Radix. Parallel FFT
An Area Efficient Mixed Decimation MDF Architecture for Radix Parallel FFT Reshma K J 1, Prof. Ebin M Manuel 2 1M-Tech, Dept. of ECE Engineering, Government Engineering College, Idukki, Kerala, India 2Professor,
More informationOptimization of power and area using majority voter based fault tolerant VLSI circuits
Optimization of power and area using majority voter based fault tolerant VLSI circuits Kalpana 1, Umesh Pal Singh 2 1,2 Seth Jai Parkas Mukand Lal Institute of Engineering and Technology Radaur (YNR),
More information