Optimization of power and area using majority voter based fault tolerant VLSI circuits

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1 Optimization of power and area using majority voter based fault tolerant VLSI circuits Kalpana 1, Umesh Pal Singh 2 1,2 Seth Jai Parkas Mukand Lal Institute of Engineering and Technology Radaur (YNR), India Abstract This paper proposes a new voter circuit for tolerating stuck-at-faults in digital circuits. We consider in this paper single stuck-at type faults, occurring at a gate input. A stuck-at-fault may adversely affect on the functionality of the user implemented design. A novel fault tolerant design based on hardware redundancy (replication) is presented here for single fault model to tolerate faults. The design is also suitable to be used for highly dependable systems implemented by means of FPGAs (Field Programmable Gate Array) at RTL (Resistor Transfer Level). The circuit presented here demonstrates the fault tolerance capability of the design and is implemented for a single bit full subtractor circuit but can be generalized for any other digital circuit. The functioning of all the three full subtractors can be easily verified. In case of occurrence of stuckat-faults, the circuit will configure itself to select the other fault free outputs. We proposed a circuit which is more optimized than NFTVC (novel fault tolerant voter circuit). We have also presented and compared the results of NFTVC method with proposed circuit. The circuit is synthesized and tested for Xilinx s XS3S500E (Spartan-3E) FPGA starter kit. Index Terms fault tolerance, NFTVC, FPGA, low power and area fault tolerance. In the traditional fault prevention approach, the objective is to increase the reliability by a priori elimination of all faults. Since this is almost impossible to achieve in practice, the goal of fault prevention is to reduce the probability of a system failure to an acceptable low value. In the fault tolerance approach, faults are expected to occur during computation, but their effects are automatically countered by incorporating redundancy i.e., additional resources, so that valid computation can continue even in the presence of faults.tmr (triple modular redundant) use the concept by triplicate the CUT then use majority voter circuit which gives the output according to the majority of the inputs. If any fault occurs at any one circuit it will select the output from the majority of the rest of two circuits. Basically [5] NFTVC uses the priority encoder and multiplexer in places of the majority voter circuit. The proposed circuit which is further gives the optimized results as compare to the NFTVC. The circuit is optimized in terms of power and area. The proposed circuit uses the ex-or gates and multiplexers. I. INTRODUCTION Redundancy techniques such as NMR (N-tuple modular redundancy) is now widely used to correct faulty behavior and achieve high reliability. NMR consists of N + 1 components: N replicas of the module M and a voter MAJ. NMR systems require a voter in order to decide the final output. This paper presents a novel technique to tolerate stuck at faults at the outputs of any digital CUT (circuit under test) [14]. If there is a fault at one of the outputs then circuit itself detects the fault and configures to provide the fault free output. In place of the voter circuit we have used a novel circuit consisting of ex-or gates, priority encoder and multiplexer to produce fault free output at any moment of time. This approach allows achieving fault tolerance with respect to faults. There are two fundamentally different approaches that can be taken to increase the reliability of computing systems. The first approach is called fault prevention (also known as fault intolerance) and the second, II. NOVAL FAULT TOLERANT VOTER CIRCUIT The NFTVC uses hardware redundancy which replaces the voter circuit of the classical TMR circuit for tolerating faults. NFTVC is constructed using ex-or gates, priority encoder and multiplexers to produce fault free output. In a fault-tolerant voter named NFTVC [5] is proposed as shown in Figure 1. The circuit contains a priority encoder designed to output a selecting signal for the multiplexer. With A = B = C = 0, if any of the nodes in the voter is stuck to 1, the circuit will still produce the correct output as 0. if I1 = 0, then sel = 0 and A (equals to B) is going to be selected as the output. if I2 = 0, then sel = 1 and C (equals to B) is the selected output. Kalpana, is with Electronics and Communication engineering, JMIT Radaur, Kurukshetra University, India ( Kalpanaldw@gmail.com). 10

2 corresponds to logic value C. According to the scheme, this relation is respected because S = A ex-or B = 1. Fig.1.Noval Fault tolerant voter circuit (NFTVC) The CUT which is taken as the full subtractor has been triplicated.the outputs of the functional units are given to the ex-or gates and outputs of the ex-or gates are fed to the priority encoders. The output from the priority encoders is given as a select signal to the multiplexers. The two multiplexers give the correct output difference and borrow respectively. NFTVC with full subtractor is shown in Figure 2. Fig.3. Proposed circuit The proposed majority voter circuit is optimized (power and area) circuit over the NFTVC. Optimization is the basic need of the any digital circuit. The implementation of this proposed circuit with full subtractor is shown in the Figure 4. Fig.2. Full subtractor circuit with NFTVC Fig.4. Full subtractor circuit with proposed circuit III. PROPOSED CIRCUIT In this work we propose an alternative scheme for majority voting presented in Figure 3. We can see that this structure is fault-tolerant following the analysis below: In the proposed circuit we basically use the ex-or gates multiplexer. The output of ex-or gate acts as the select line of the multiplexer. If all input are same then output is same as input. Case 1 (C is faulty): The logic signals A and B are the same and S = A ex-or B = 0. So, the multiplexer s output will be signal B which represents the majority value. Case 2 (A or B is faulty): The logic signals A and B are different and the majority must be the logic value, which 11 IV. SIMULATION AND SYNTHESIS RESULTS The functionality of the design for both NFTVC and proposed majority voter circuit for one bit full subtractor was verified and simulated using Isim 0.61xd Simulator [9] as shown in Fig.5 & Fig.6. Synthesis was done using the Xilinx s synthesizer tool (XST) of ISE Foundation series 13.2, The design of the fault tolerance ability of the system has been tested and verified by means of VHDL simulation programs. Simulation results show that even after injecting the faults at the input of the subtractor circuit, the fault free output is obtained. The Power and Area calculations have been done using Xilinx s power extimator-11.1[4].

3 Fig.5(A). Simulation result for NFTVC The simulation can be done for the fault insertion. The fault can be inserted at the input. It has been found that we get still the fault free output. Fig.6(A).Simulation result for Proposed circuit Fig.5(B). Simulation result after fault insertion in NFTVC Fig.6(B). Simulation result for proposed circuit after fault insertion The power and performance results of the NFTVC and proposed scheme are compared and depicted in Table I. 12

4 Table I. Comparison of NFTVC and proposed circuit in terms of Power and Area Tolerant scheme NFTVC Power dissipation (mw) No. of LUT s Proposed circuit The RTL schematic of NFTVC and proposed circuit is shown in Fig. 7 and Fig. 8 respectively. International Journal of Research in Management, Science & Technology (E-ISSN: ) V. IMPLEMENTATION RESUTS A typical FPGA application uses a single non-volatile memory to store configuration images. To demonstrate new Spartan-3E FPGA capabilities, the starter kit board has three different configuration memory sources that all need to function well together. The extra configuration functions make the starter kit board more complex than typical [10,11] Spartan-3E FPGA applications. The starter kit board also includes an on-board USB-based JTAG programming interface. The on-chip circuitry simplifies the device programming experience. The FPGA implementation for Full subtractor is shown on figure 9 and 10. Fig 9.FPGA implementation of full subtractor in Spartan-3 kit Fig. 7. RTL Schematic of NFTVC Fig. 8. RTL Schematic of proposed circuit 13 Fig.10. FPGA implementation of full subtractor in Spartan-3 kit under fault insertion

5 Implementation of Full subtractor is done using Xilinx Spartan-3E FPGA board [11]. Spartan-3 FPGAs are applicable to a wide range of consumer electronics applications due to their exceptionally low cost. Up to 232 user-i/o pins, 320-pin FPGA package, Over 10,000 logic cells. The Spartan-3E FPGA Starter Kit board has four slide switches but we require extra five switches because of total nine inputs are used. V. CONCLUSION In this paper, we presented an alternative architecture for majority voter to be used in NFTVC scheme. The proposed solution is robust to single fault and exceeds those previous ones in terms of optimization. Furthermore, it saves area, power dissipation. The concept of proposed circuit was studied and it was understood that it is efficient in configuring and locating faults in the system. The proposed circuit was designed to achieve fault tolerance with respect to stuck-atfaults. The proposed circuit was simulated and synthesis was carried out using Isim (0.61xd) Simulator and Xilinx s 13.2 Synthesizer PlanAhead Tool respectively. The results of proposed circuit were compared with that of NFTVC in terms of power and area. The system was tested in both simulation level using ISim and implementation is done using Spartan- 3E kit. International Journal of Research in Management, Science & Technology (E-ISSN: ) [14] Tian Ban and Lirida A. B. Naviner, Optimized Robust Digital Voter in TMR Designs. REFERENCES [1] R.V.Kshirsagar, R.M.Patrikar, A Novel Fault Tolerant Design and an Algorithm for Tolerating Faults in Digital Circuits, IEEE Proceeding, [2] Monica Alderighi, Sergio D'Angelo1, Cecilia Metra2 and Giacomo R. Sechi1, Novel Fault-Tolerant Adder Design for FPGA-Based Systems, IEEE International On-Line Testing Workshop,Volume 7,pp.54-58, [3] F. Lima., C. Carmichaell, I. Fabula, R Padovanil, R. Reis, A Fault Injection Analysis of Virtex FPGA TMR Design Methodology,IEEE Proceding. [4] Xilinx(2011), X-Power Estimator (XPE) user guide. Available: Spartan-3E- XPE-11.1.XLS. [5] Deepa Jose1, Dr P Nirmal Kumar, A.David Naveen Dhas, Implementation of Power optimized VLSI Designs for Reliable Processing using Majority circuit,annual IEEE India Conference(INDICON), [6] H. Sandi, Functional Triple Modular Redundancy (FTMR) VHDL Design Methodology for Redundancy in Combinatorial and Sequential Logic," European Space Agency Contract Report, Gaisler Research, Sweden,Rep /01/NL/FM(SC) CCN-3, Dec [7] M. Alderighi, S. D. Angelol, C. Metra and G. R.Sechi, Novel fault tolerant adder design for FPGA based systems," in proc. IEEE On Line Testing Workshop, Taormina, 2001, pp [8] R.V. Kshirsagar and R.M. Patrikar, Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits, Microelectronics Reliability, vol. 49, no. 12, 2009, pp [9] XILINX Inc (2011), PlanAhead User Guide 13.2 [Online].Available: sw-manuals xilinx 13.2/PlanAhead_User Guide.pdf [10] XilinxInc (2013). DS312 Spartan-3E FPGA: Spartan-3E FPGA Family: Introduction and Ordering Information [Online]. Available [11] Xilinx (2011).Spartan-3E FPGA Starter Kit Board User Guide.Available: /support/documentation/ sw-manuals xilinx 13.2/spartan3- hdl.pdf [12] Sobeeh Almukhaizim, Ozgur Sinanoglu, A Hazard-free Majority Voter for TMR-Based Fault Tolerant in Asynchonous Circuits,IEEE,2007. [13] Edward Stott, Pete Sedcole, Peter Y. K. Cheung, FAULT TOLERANT METHODS FOR RELIABILITY IN FPGAs, IEEE 2008,pg.no