Design and Implementation of on-board satellite encryption with SEU error detection & correction code on FPGA

Transcription

1 68 Int'l Conf. Security and Management SAM'16 Design and Implementation of on-board satellite encryption with SEU error detection & correction code on FPGA Samah Mohamed, Khaled A.Shehata, Hanady H.Issa Abstract Nabil Hamdy Shaker Earth Observation (EO) satellites in Low Earth Orbit (LEO) provide earth with data required for both military and civilian applications. Satellite manufactures are realizing that security is essential issue in satellite communications. Advanced Encryption Standard (AES) is one of the important candidates to secure satellite communications. Harsh radiation is the main feature of LEO environment which causes Single Event Upsets (SEUs). On-board encryption processor needs to be robust enough for faults in order to avoid transmission of erroneous data to ground. The presented algorithm in this paper combines AES with Hamming error detection and correction code to protect the on-board encryption process from SEU. The proposed fault tolerant algorithm is designed using the Hardware Description Language (HDL) design entry and implemented on Xilinx Field Programmable Gate Arrays (FPGAs) virtex6. Keywords- AES, SEU, Hamming Error Detection and Correction Code, VHDL, FPGA. i. Introduction and background The science of cryptography started from the times of ancient Egyptians till today and its importance is increasing day by day. In recent years, with the explosive advancement in technology, the need for data security becomes essential especially in free space satellite applications [1]. (Arab Academy For Science & Technology (AAST) (Misr International University (MIU)) immunity of encryption process against faults is very essential in satellites [4]. The induced faults due to harsh environments cause SEU which leads to erroneous data transmitted to ground. SEU fault detection is not enough for space applications but fault correction is more important [5]. Realizing security through various Encryption Algorithms and solving the SEU problem in satellite have been addressed in many references. In [3,6], combining of AES with Hamming Code (12,8) was presented without any detailed design. They implemented the system on Virtex2 (XCV2V1000) from XILINX with a maximum frequency of 25MHz. In [7] combining of Data Encryption Standard (DES) and Turbo code was presented without any hardware implementation. The main weaknesses of the system were the low level of security and small data block size as a result of using DES Algorithm. In [8] combining AES with Hamming code (12,8) was also presented but without any hardware implementation. This paper presents combining both Hamming error detection and correction code with AES in a single algorithm. The algorithm is implemented on an FPGA and tested against SEU by injecting random faults. ii- The System Architecture Of the Proposed Algorithm This section describes a new approach of fault tolerant model. It combines both AES 128-bit block cipher and (12,8) Hamming code. The AES 128-bit block cipher output has 128-bit plaintext input and 128-bit session key as present in figure 1. AES is considered as security candidate well suited for resource constrained satellites platforms because of its simplicity, flexibility, ease of implementation and high throughput. In order to meet the requirement for high data rate processing demanded by present EO satellites, hardware implementation is considered as the preferred choice in satellites imaging payloads [2,3]. Field Programmable Gate Arrays (FPGAs) is well suited platform because of its flexibility of design, shorter timeto-market, remote configurability etc. So it is suitable for use in small satellite on-board systems. Increasing the

2 Int'l Conf. Security and Management SAM'16 69 matrix [9]. Hamming error detection and correction operates on byte level in each AES state transformation matrix of all rounds [2,3,4]. Hamming encoding is performed after each transformation to get 192 bits while decoding is performed before the next transformation to get the corrected 128 bits (16 bytes) due to any SEU in its bytes. The main purpose of the combining AES with Hamming is to make sure that data transferred between two successive encryption transformations is error free, with no negative effect on the encryption process [3,4,8,9]. iii. AES transformation module design. The system is designed using Matlab, before starting the hardware implementation, for verification purposes. For hardware implementation the Hardware Description Language (VHDL) design entry is used for the whole system design. Both the pre-routing and post-routing simulations of the proposed design are then performed using Modelsim 6.3a tools from Mentor Graphics. The following subsections show the pre-routing simulation of each AES transformation individually. Figure 1. AES 10 Rounds Block Diagram The used AES has 10 rounds, each round composes of four transformations named, Subbytes, Shift row, Mix column and Add round key. Subbytes transformation Figure 3 presents the pre-routing simulation of subbytes transformation. The results are compared with Matlab results to indicate the proper operation of the subbyte transformation based on S-Box table. The S-Box contains a permutation of all possible 256 of 8-bit values. In this transformation each individual byte of state matrix is mapped into a new byte. Figure 2. One round of AES combined with Hamming Figure 2 shows one round architecture of the proposed design. Hamming code (12,8) is inserted in the path of AES as an error detection and correction. It is added between transformations interconnects and is implemented 16 times in parallel in each 16 bytes state Figure 3. Subbytes pre-routing simulation of first Round

3 70 Int'l Conf. Security and Management SAM'16 Shiftrow transformation The input of this transformation is the output from the subbytes transformation. ShiftRows transformation causes diffusion of bits over multiple rounds by cyclically shifts the rows of the state over different offsets. Row number 0 in the matrix is not shifted, row 1 is shifted left by one byte, row 2 is shifted left by two bytes, and row 3 is shifted left by three bytes constructing the new state matrix. Figure 4 shows that the simulation results of the transformation outputs are identical to those from Matlab. This indicates the proper operation of the shiftrow transformation. Figure 5. Mixcolumn pre-routing simulation of first round AddRound Key Figure 6 presents the pre-routing simulation based on XORing between the Mixcolumn output state matrix and key expansion of each specific round. Figure 4. Shiftrow pre-routing simulation of first round Mixcolumn transformation The input of this transformation is the output from the shiftrow transformation. This linear transformation operates on the state matrix column by column. The matrix obtained from the ShiftRow step i.e. [C ij ], is multiplied by a standard matrix to produce a new output matrix [d ij ]. 1 Figure 5 shows a coincidence between Matlab input /output results and pre-routing simulation result of this transformation Figure 6. AddRound Key pre-routing simulation of first round

4 Int'l Conf. Security and Management SAM'16 71 In figure 6, Number 1 shows the ShiftRow output state matrix in the first AES round. Number2 in the same figure indicates Mixcolumn output state matrix in first AES round. Number3 indicates Input key state matrix. Number 4 shows input plaintext state matrix. Number 5 displays the final output state matrix resulted from XORing mixcolumn output with the the first round key expansion output. iv. Simulation Results of the Proposed System This section concerns both the post and pre-routing simulations of the proposed design. Figure 7 shows the final cipher output of the proposed system as a prerouting simulation. Figure 8 Propose system post routing simulation 4 cycles / round Figure 9 shows the whole encryption process containing the 10 rounds. The whole operation lasts 40 clock cycles. The system is pipelined which allows the inputs to be applied in each clock cycle. This figure shows that the design corrects any SEU fault in different rounds and different transformations inside the round. Cipher output after correction Original Subbyte Figure 7. Pre-routing simulation results of fault free system As shown in figure 7 the plaintext "plaintext_in" is (3243f6a8885a308d313198a2e ) h.. The key input "key in" is(2b7e151628aed2a6abf cf4f3c) h. The fault free output of the AES encryption process cipher output is named "plaintext_out" which is ( d02dc09fbdc a0b32) h. The corrected output with a single bit injected error in each byte is noted as plaintext_out which is: ( d02dc09fbdc a0b32) h. The injection of faults is forced inside the different AES rounds at different transformation state matrix of any round. The corrected output is identical to the expected output. This means the system detects all single-bit-error in any byte and corrects them during the encryption process. Figure 8 shows the post-routing simulation of the proposed system. The maximum delay of the output is 15ns which enable the system to run at 66MHz. Corrupted Subbyte Figure 9 Propose System post routing simulation with v. Proposed error correction System Faults Injection v. Proposed System Faults Injection The proposed system is simulated and tested through injecting faults randomly in different rounds, transformations and bytes. The main constrain is in injection of a maximum 1 bit fault in each byte to get proper error correction. In each simulation, the error is corrected as long as injecting only one bit-error in each byte. All results after fault correction are verified with Matlab simulation results [9]. The system corrects all cases of fault injection. Figure 10 shows the injection of faults in three interconnect locations between AES transformations simultaneously; keeping in our consideration injecting of only 1 bit fault in any byte. The first interconnect location is between output of subbyte transformation and input of shiftrow presented by letter (A). The second interconnect

5 72 Int'l Conf. Security and Management SAM'16 location is between output of shiftrow and input of Mixcolumn transformation presented by letter (B). The third interconnect location is between output of Mixcolumn and input of AddRound Key transformation presented by the letter (C). Figure 12: Part (A) Detailed explanation from Figure 11 Letter (B) in figure 11 shows the 2 nd Round ShiftRow matrix after fault injection as displayed in figure 13. Faults injected in specific matrix locations as follows:- Figure 10 Faults injection in Second Round of AES Transformations Figure 11 shows the three faulty matrices in the above interconnects which are indicated by letters A,B and C. The circled digits indicate the fault existence as shown in figure 10. In bit no.(7) of byte no.(8) In bit no.(4) of byte no.(11) The table in figure 13 indicates the injection of faults in 192 bits simultinously, the faulty bits are circled. Figure 13: Part (B) Detailed explanation from Figure 11 Letter (C) in figure 11 shows the 2 nd Round Mixcolumn matrix after fault injection as displayed in figure 14. Faults injected in specific matrix locations as follows:- Figure 11: Inject 1 bit fault in a byte in more than one transformation in Second Round Letter (A) in figure 11 shows the 2 nd Round Subbytes matrix after fault injection as displayed in figure 12. Faults injected in specific matrix locations are as follows:- In bit no.(7) of byte no.(8) In bit no.(4) of byte no.(11) The table in figure 14 indicates the injection of faults in 192 bits, the faulty bits are circled. In all cases the faults are detected and corrected. In bit no.(7) of byte no.(8) In bit no.(4) of byte no.(11) Lower table in figure 12 indicates the injection of faults in 192 bits. These faulty bits are circled. Figure 14: Part (C) Detailed explanation of Figure 11

6 Int'l Conf. Security and Management SAM'16 73 vi. FPGA implementation of the proposed system AES is efficient for hardware based implementation to meet the requirement of high throughput [9,10]. In most EO satellites high throughput fault tolerant encryption process is required to satisfy high data rate transmission. The VHDL is used as a design entry for the hardware design. Synthesis is carried out using Xilinx ISE tool version13. It generates a map reports which shows the FPGA utilization of the proposed design. The target FPGA used for hardware implementation is Xilinx XC6VLX240 IFFG1156 and the FPGA Evaluation kit model ML605 is used. The hardware measurement is displayed on PC after the end of each encryption and decryption process to verify the correct output data. The throughput of the fault tolerant AES implementation is calculated using the equation below: where n is the number of clock cycles required to encrypt a single block of 128 bits. The system needs 4 clock cycles for each round and extra 2 clock cycles to prepare the session key. Accordingly, the total clock cycles n is (4*10)+2=42 clock cycles. The maximum system operating frequency f is 66MHz. So, the calculated throughput is equal to 201Mbps. But, due to pipelining of our designed system, which allows applying of 128 bits every clock cycle, the calculated throughput is 128 bit * 66MHz = Gb/s. Table1 presents the utilization of vertix6 FPGA. Table 1. FPGA Utilization Report Target FPGA is Xilinx XC6VLX240 & f= 66MHz Item Used Available Utilization Occupied 1,150 37,680 3% slices IOB s % Peak 680 MB Memory usage No. of LUT Slice 2, ,720 1% vii. Conclusion In this paper, we propose a hardware design for fault tolerant system combining AES with Hamming error detection and correction code. It protects the on-board satellites data during encryption process against SEU. The proposed design is implemented on Vertix6 FPGA. The utilization is 3% of the chip. The maximum operating speed is 66MHz with a throughput of Gb/s which satisfies the satellite requirements. Varies Harsh environment simulations are performed for test purposes, which simulates the LEO Harsh environment. The proposed system detects and corrects a one SEU in each data byte of state matrix. viii. References [1] Pradeep Kumar Singh and Prof. Dipti Patil, Comparative Study of Satellite Image Encryption Algorithm, International Journal of Infinite Innovations in Technology (IJIIT), Volume-I, Issue- II,Paper-08, India, pp. 1-23, October [2] Ashkan Masoomi and Roozbeh Hamzehiyan, A New Approach for Detecting and Correcting Errors in the Satellite Communications Based on Hamming Error Correcting Code, International Journal of Computer Theory and Engineering(IJCTE), Vol.5, No.2, Iran, pp , April [3] Roohi Banu and Tanya Vladimirova, Fault-Tolerant Encryption for Space Applications, IEEE Conference of Electronic Engineer, Surrey Space Center (SSC), VOL.45, NO.1, India & Russia, pp ,January [4] Nahid Farhady Ghalaty, Aydin Aysu and Patrick Schaumont, Analyzing and Eliminating the Causes of Fault Sensitivity Analysis,IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE), USA, PP.1-6, [5] Hoda Pahlevanzadeh, Jaya Dofe, and Qiaoyan Yu, Assessing CPA Resistance of AES with Different Fault Tolerance Mechanisms, IEEE conference of 21 st Asia and South Pacific Design Automation Conference (ASP-DAC),USA, pp , [6] Roohi Banu and Tanya Vladimirova, On-Board Encryption in Earth Observation Small Satellites,IEEE Conference of Electronic Engineering, Surrey Space Center (SSC),United Kingdom, pp , October [7] Rajashri Khanai, Dr. G. H. Kulkarni and Dattaprasad A.Torse, Neural Crpto-Coding as DES : Turbo over Land Mobil Satellite (LMS) Channel, IEEE, International Conference in Communications and Signal Processing(ICCSP), India, pp , 3-5 April [8] C. Jeba Nega Cheltha and Prof. R.Velayutham, A novel Error-Tolerant Method in AES for Satellite Images, IEEE International Conference in Emerging Trends in Electrical and Computer Technology (ICETECT),India, pp , March [9] Samah Mohamed, KhaledA.Shehata, HanadyH.Issa and Nabil Hamdy Shaker FPGA Implementation of a combined Hamming AES error tolerant algorithm for on board satellite,ieee Conference of Electronics Engineer, The World Congress on Information Technology and Computer Applications (WCITCA 2015), Hammamet, Tunisia, pp. 1-4, June [10]C.Thamilarasi and K.Shanmugapriya, A HIGH THROUGHPUT AND ERROR TOLERANT AES DESIGN,International Journal of Advanced Research in in Electronics and Communication Engineering (IJARECE), Volume 2, Issue 4, pp , April 2013.