Outline. The demand The San Jose NAP. What s the Problem? Most things. Time. Part I AN OVERVIEW OF HARDWARE ISSUES FOR IP AND ATM.
|
|
|
- Sara Palmer
- 6 years ago
- Views:
Transcription
1 Outline AN OVERVIEW OF HARDWARE ISSUES FOR IP AND ATM Name one thing you could achieve with ATM that you couldn t with IP! Nick McKeown Assistant Professor of Electrical Engineering and Computer Science Stanford University nickm@ee.stanford.edu Part I The need Trends in ATM switches Trends in IP routers Merging of the two Part II Some key technologies Summary 2/25: Merging IP and ATM What s the Problem? The demand The San Jose NAP Most things Aggregate bandwidth (Mbps) Time Feb Mar Apr May Jun Jul Aug Sep Oct Nov 3/25: Merging IP and ATM 4/25: Merging IP and ATM Source:
2 The supply Why we need faster routers Router Performance (packets/second) packets/second Demand Supply /25: Merging IP and ATM The race is on... 6/25: Merging IP and ATM Trends in ATM switches Generic ATM Switch: packets/second Demand VC lookup Signaling Processor Output Scheduler Supply Ascend (Netstar), Ipsilon, Toshiba, BBN, [Cisco, Bay, Juniper, Torrent]?... 7/25: Merging IP and ATM 8/25: Merging IP and ATM
3 Trends in IP routers Merging of IP & ATM Generic IP Router: Routing Processor Forwarding Engine Output Scheduler Header processing time Copy Arrival Min back-to-back packet size Packet size 9/25: Merging IP and ATM Merging of IP & ATM 0/25: Merging IP and ATM Trends in IP routers Trend : Move CPU off forwarding path Most routers do this poorly! 2 CPU Copy CPU Header processing time Arrival HW CACHE Min back-to-back packet size Packet size HW Most routers today use caching CACHE /25: Merging IP and ATM 2/25: Merging IP and ATM
4 Trends in IP routers Trend 2: AVOID SHARED BUS Consequence 2 ROUTER A LINE CPU TAG TABLE LINE TAG TABLE IP Switching Tag Switching 3/25: Merging IP and ATM 4/25: Merging IP and ATM The fundamental hardware difference between IP & ATM Claim 24 VCI ENTRY PER ACTIVE FLOW 32-64K If we could do FAST longest prefix matches Then we wouldn t be here! 32 IP DA FWD TABLE ENTRY PER DEST. SUBNET 50-00K BUT: ATM VCI 6 bits AND we get to choose! 5/25: Merging IP and ATM 6/25: Merging IP and ATM
5 Merging of IP & ATM Why? If you could get the whole IP forwarding table in fast memory (and update it invisibly!) then who needs ATM? Removing IP forwarding engine from the datapath is one thing: but still need Quality Processor on the critical path. Large number of individual flows (ISMP Flow Type ) => aggregation onto coarser src-dest flows (Type 2) => need reassembly/frame-mode switches Some key hardware technologies Memory bandwidth Serial link technology Special-purpose memories CPU vs special-purpose processors 7/25: Merging IP and ATM Memory Bandwidth 8/25: Merging IP and ATM Trends in ATM switches Memory Size How fast can this architecture go? Shared Memory 5ns SRAM Memory Speed SRAM DRAM Time Output queueing running out of steam! VC translation How fast can a 6 port switch ope with this architecture? r cell per port cell Time 9/25: Merging IP and ATM 20/25: Merging IP and ATM
6 2/25: Merging IP and ATM Serial link technology wires are becoming a scarce resource Line card Standard interfaces are a bottleneck: 00 Mbit/sec per pin is tough. 00 signal pins for 0 Gbit/sec. Large chip packages and board connectors drive up costs. Memory Serial interfaces are efficient: Gbit/sec per pin. 0 signal pins for 0 Gbit/sec. Special purpose memories Problems with High Speed Links Precise timing needed Hard to determine which bit is which. Distributed clocks have skew ( ns/bit time at Gb/s). Solution: recover timing from data. High speed signals Need to transmit and receive Gb/s. Solutions: low swing signals, good terminations on transmission lines. 22/25: Merging IP and ATM Serial link technology Much ongoing R&D in this area. CPU vs. special-purpose processor FIFOs Cache Interface 2 Programmable FIFOs Chip ChipN 2 Packets Data Data copy Packets Header Forwarding Tables e.g. BayBridge 23/25: Merging IP and ATM 24/25: Merging IP and ATM
7 Summary Trends in switching Single-stage shared memory and busses are running out of steam. Combined I/O Queueing and/or multistage switches are require. Trends in routing Removal of CPUs from forwarding path. Quality Processor still on the main forwarding path. Key Technologies Memory Bandwidth Serial link technology Special-purpose memory Special-purpose processors 25/25: Merging IP and ATM
Multi-gigabit Switching and Routing
Multi-gigabit Switching and Routing Gignet 97 Europe: June 12, 1997. Nick McKeown Assistant Professor of Electrical Engineering and Computer Science nickm@ee.stanford.edu http://ee.stanford.edu/~nickm
Router Construction. Workstation-Based. Switching Hardware Design Goals throughput (depends on traffic model) scalability (a function of n) Outline
Router Construction Outline Switched Fabrics IP Routers Tag Switching Spring 2002 CS 461 1 Workstation-Based Aggregate bandwidth 1/2 of the I/O bus bandwidth capacity shared among all hosts connected to
Professor Yashar Ganjali Department of Computer Science University of Toronto.
Professor Yashar Ganjali Department of Computer Science University of Toronto yganjali@cs.toronto.edu http://www.cs.toronto.edu/~yganjali Today Outline What this course is about Logistics Course structure,
EECS 122: Introduction to Computer Networks Switch and Router Architectures. Today s Lecture
EECS : Introduction to Computer Networks Switch and Router Architectures Computer Science Division Department of Electrical Engineering and Computer Sciences University of California, Berkeley Berkeley,
Computer Networks. Instructor: Niklas Carlsson
Computer Networks Instructor: Niklas Carlsson Email: niklas.carlsson@liu.se Notes derived from Computer Networking: A Top Down Approach, by Jim Kurose and Keith Ross, Addison-Wesley. The slides are adapted
CSE 3214: Computer Network Protocols and Applications Network Layer
CSE 314: Computer Network Protocols and Applications Network Layer Dr. Peter Lian, Professor Department of Computer Science and Engineering York University Email: peterlian@cse.yorku.ca Office: 101C Lassonde
Generic Architecture. EECS 122: Introduction to Computer Networks Switch and Router Architectures. Shared Memory (1 st Generation) Today s Lecture
Generic Architecture EECS : Introduction to Computer Networks Switch and Router Architectures Computer Science Division Department of Electrical Engineering and Computer Sciences University of California,
Routers: Forwarding EECS 122: Lecture 13
Routers: Forwarding EECS 122: Lecture 13 epartment of Electrical Engineering and Computer Sciences University of California Berkeley Router Architecture Overview Two key router functions: run routing algorithms/protocol
TOC: Switching & Forwarding
TOC: Switching & Forwarding Why? Switching Techniques Switch Characteristics Switch Examples Switch Architectures Summary TOC Switching Why? Direct vs. Switched Networks: n links Single link Direct Network
Routers: Forwarding EECS 122: Lecture 13
Input Port Functions Routers: Forwarding EECS 22: Lecture 3 epartment of Electrical Engineering and Computer Sciences University of California Berkeley Physical layer: bit-level reception ata link layer:
Routers Technologies & Evolution for High-Speed Networks
Routers Technologies & Evolution for High-Speed Networks C. Pham Université de Pau et des Pays de l Adour http://www.univ-pau.fr/~cpham Congduc.Pham@univ-pau.fr Router Evolution slides from Nick McKeown,
Network layer (addendum) Slides adapted from material by Nick McKeown and Kevin Lai
Network layer (addendum) Slides adapted from material by Nick McKeown and Kevin Lai Routers.. A router consists - A set of input interfaces at which packets arrive - A set of output interfaces from which
TOC: Switching & Forwarding
TOC: Switching & Forwarding Why? Switching Techniques Switch Characteristics Switch Examples Switch Architectures Summary Why? Direct vs. Switched Networks: Single link Switches Direct Network Limitations:
CMSC 332 Computer Networks Network Layer
CMSC 332 Computer Networks Network Layer Professor Szajda CMSC 332: Computer Networks Where in the Stack... CMSC 332: Computer Network 2 Where in the Stack... Application CMSC 332: Computer Network 2 Where
Network Superhighway CSCD 330. Network Programming Winter Lecture 13 Network Layer. Reading: Chapter 4
CSCD 330 Network Superhighway Network Programming Winter 2015 Lecture 13 Network Layer Reading: Chapter 4 Some slides provided courtesy of J.F Kurose and K.W. Ross, All Rights Reserved, copyright 1996-2007
Chapter 4 Network Layer
Chapter 4 Network Layer Computer Networking: A Top Down Approach Featuring the Internet, 3 rd edition. Jim Kurose, Keith Ross Addison-Wesley, July 2004. Network Layer 4-1 Chapter 4: Network Layer Chapter
CSC 401 Data and Computer Communications Networks
CSC 401 Data and Computer Communications Networks Network Layer Overview, Router Design, IP Sec 4.1. 4.2 and 4.3 Prof. Lina Battestilli Fall 2017 Chapter 4: Network Layer, Data Plane chapter goals: understand
CMPE 150/L : Introduction to Computer Networks. Chen Qian Computer Engineering UCSC Baskin Engineering Lecture 11
CMPE 150/L : Introduction to Computer Networks Chen Qian Computer Engineering UCSC Baskin Engineering Lecture 11 1 Midterm exam Midterm this Thursday Close book but one-side 8.5"x11" note is allowed (must
The Network Layer and Routers
The Network Layer and Routers Daniel Zappala CS 460 Computer Networking Brigham Young University 2/18 Network Layer deliver packets from sending host to receiving host must be on every host, router in
CSCD 330 Network Programming
CSCD 330 Network Programming Network Superhighway Spring 2018 Lecture 13 Network Layer Reading: Chapter 4 Some slides provided courtesy of J.F Kurose and K.W. Ross, All Rights Reserved, copyright 1996-2007
Sizing Router Buffers
Sizing Router Buffers Sachin Katti, CS244 Slides courtesy: Nick McKeown Routers need Packet Buffers It s well known that routers need packet buffers It s less clear why and how much Goal of this work is
Topics for Today. Network Layer. Readings. Introduction Addressing Address Resolution. Sections 5.1,
Topics for Today Network Layer Introduction Addressing Address Resolution Readings Sections 5.1, 5.6.1-5.6.2 1 Network Layer: Introduction A network-wide concern! Transport layer Between two end hosts
Network Processors and their memory
Network Processors and their memory Network Processor Workshop, Madrid 2004 Nick McKeown Departments of Electrical Engineering and Computer Science, Stanford University nickm@stanford.edu http://www.stanford.edu/~nickm
CSE 123A Computer Networks
CSE 123A Computer Networks Winter 2005 Lecture 8: IP Router Design Many portions courtesy Nick McKeown Overview Router basics Interconnection architecture Input Queuing Output Queuing Virtual output Queuing
INF5050 Protocols and Routing in Internet (Friday ) Subject: IP-router architecture. Presented by Tor Skeie
INF5050 Protocols and Routing in Internet (Friday 9.2.2018) Subject: IP-router architecture Presented by Tor Skeie High Performance Switching and Routing Telecom Center Workshop: Sept 4, 1997. This presentation
Chapter 4. Computer Networking: A Top Down Approach 5 th edition. Jim Kurose, Keith Ross Addison-Wesley, sl April 2009.
Chapter 4 Network Layer A note on the use of these ppt slides: We re making these slides freely available to all (faculty, students, readers). They re in PowerPoint form so you can add, modify, and delete
CSC 4900 Computer Networks: Network Layer
CSC 4900 Computer Networks: Network Layer Professor Henry Carter Fall 2017 Villanova University Department of Computing Sciences Review What is AIMD? When do we use it? What is the steady state profile
HWP2 Application level query routing HWP1 Each peer knows about every other beacon B1 B3
HWP2 Application level query routing HWP1 Each peer knows about every other beacon B2 B1 B3 B4 B5 B6 11-Feb-02 Computer Networks 1 HWP2 Query routing searchget(searchkey, hopcount) Rget(host, port, key)
Router Architectures
Router Architectures Venkat Padmanabhan Microsoft Research 13 April 2001 Venkat Padmanabhan 1 Outline Router architecture overview 50 Gbps multi-gigabit router (Partridge et al.) Technology trends Venkat
Module 17: "Interconnection Networks" Lecture 37: "Introduction to Routers" Interconnection Networks. Fundamentals. Latency and bandwidth
Interconnection Networks Fundamentals Latency and bandwidth Router architecture Coherence protocol and routing [From Chapter 10 of Culler, Singh, Gupta] file:///e /parallel_com_arch/lecture37/37_1.htm[6/13/2012
EE 122: Router Design
Routers EE 22: Router Design Kevin Lai September 25, 2002.. A router consists - A set of input interfaces at which packets arrive - A set of output interfaces from which packets depart - Some form of interconnect
HW3 and Quiz. P14, P24, P26, P27, P28, P31, P37, P43, P46, P55, due at 3:00pm with both soft and hard copies, 11/11/2013 (Monday) TCP), 20 mins
HW3 and Quiz v HW3 (Chapter 3): R1, R2, R5, R6, R7, R8, R15, P14, P24, P26, P27, P28, P31, P37, P43, P46, P55, due at 3:00pm with both soft and hard copies, 11/11/2013 (Monday) v Quiz: 10/30/2013, Wednesday,
The IP Data Plane: Packets and Routers
The IP Data Plane: Packets and Routers EE 122, Fall 2013 Sylvia Ratnasamy http://inst.eecs.berkeley.edu/~ee122/ Material thanks to Ion Stoica, Scott Shenker, Jennifer Rexford, Nick McKeown, and many other
Topic 4a Router Operation and Scheduling. Ch4: Network Layer: The Data Plane. Computer Networking: A Top Down Approach
Topic 4a Router Operation and Scheduling Ch4: Network Layer: The Data Plane Computer Networking: A Top Down Approach 7 th edition Jim Kurose, Keith Ross Pearson/Addison Wesley April 2016 4-1 Chapter 4:
Cell Format. Housekeeping. Segmentation and Reassembly AAL 3/4
Housekeeping 1 st Project Handout ue Friday Oct 5 Quiz: Friday Sept 21 Material covered so far 1 st Test October 12 Cell Format User-Network Interface (UNI) 4 8 16 3 1 GFC VPI VCI Type CLP 8 HEC (CRC-8)
Cell Switching (ATM) Commonly transmitted over SONET other physical layers possible. Variable vs Fixed-Length Packets
Cell Switching (ATM) Connection-oriented packet-switched network Used in both WAN and LAN settings Signaling (connection setup) Protocol: Q2931 Specified by ATM forum Packets are called cells 5-byte header
CS 552 Computer Networks
CS 55 Computer Networks IP forwarding Fall 00 Rich Martin (Slides from D. Culler and N. McKeown) Position Paper Goals: Practice writing to convince others Research an interesting topic related to networking.
P51: High Performance Networking
P51: High Performance Networking Lecture 6: Programmable network devices Dr Noa Zilberman noa.zilberman@cl.cam.ac.uk Lent 2017/18 High Throughput Interfaces Performance Limitations So far we discussed
Packet Switch Architectures Part 2
Packet Switch Architectures Part Adopted from: Sigcomm 99 Tutorial, by Nick McKeown and Balaji Prabhakar, Stanford University Slides used with permission from authors. 999-000. All rights reserved by authors.
Internet Routers Past, Present and Future
Internet Routers Past, Present and Future Nick McKeown Stanford University British Computer Society June 2006 Outline What is an Internet router? What limits performance: Memory access time The early days:
Switching. An Engineering Approach to Computer Networking
Switching An Engineering Approach to Computer Networking What is it all about? How do we move traffic from one part of the network to another? Connect end-systems to switches, and switches to each other
Key Network-Layer Functions
Network Layer: Routing & Forwarding Instructor: Anirban Mahanti Office: ICT 745 Email: mahanti@cpsc.ucalgary.ca Class Location: ICT 121 Lectures: MWF 12:00 12:50 hours Notes derived from Computer Networking:
The iflow Address Processor Forwarding Table Lookups using Fast, Wide Embedded DRAM
Enabling the Future of the Internet The iflow Address Processor Forwarding Table Lookups using Fast, Wide Embedded DRAM Mike O Connor - Director, Advanced Architecture www.siliconaccess.com Hot Chips 12
Lecture 24: Scheduling and QoS
Lecture 24: Scheduling and QoS CSE 123: Computer Networks Alex C. Snoeren HW 4 due Wednesday Lecture 24 Overview Scheduling (Weighted) Fair Queuing Quality of Service basics Integrated Services Differentiated
EE384Y: Packet Switch Architectures Part II Scaling Crossbar Switches
High Performance Switching and Routing Telecom Center Workshop: Sept 4, 997. EE384Y: Packet Switch Architectures Part II Scaling Crossbar Switches Nick McKeown Professor of Electrical Engineering and Computer
Parallelism in Network Systems
High Performance Switching Telecom Center Workshop: and outing Sept 4, 997. Parallelism in Network Systems Joint work with Sundar Iyer HP Labs, 0 th September, 00 Nick McKeown Professor of Electrical Engineering
Broadband Rate Design for Public Benefit
Broadband Rate Design for Public Benefit The transition from service-based rates to loop rates on Chelan PUD s Broadband Network Dec.19, 2016 No action required today Today s Presentation Loop Rates Final
Outline. Circuit Switching. Circuit Switching : Introduction to Telecommunication Networks Lectures 13: Virtual Things
8-5: Introduction to Telecommunication Networks Lectures : Virtual Things Peter Steenkiste Spring 05 www.cs.cmu.edu/~prs/nets-ece Outline Circuit switching refresher Virtual Circuits - general Why virtual
Themes. The Network 1. Energy in the DC: ~15% network? Energy by Technology
Themes The Network 1 Low Power Computing David Andersen Carnegie Mellon University Last two classes: Saving power by running more slowly and sleeping more. This time: Network intro; saving power by architecting
CSCI Computer Networks
CSCI-1680 - Computer Networks Link Layer III: LAN & Switching Chen Avin Based partly on lecture notes by David Mazières, Phil Levis, John Jannotti, Peterson & Davie, Rodrigo Fonseca Today: Link Layer (cont.)
Core-Stateless Fair Queueing: Achieving Approximately Fair Bandwidth Allocations in High Speed Networks. Congestion Control in Today s Internet
Core-Stateless Fair Queueing: Achieving Approximately Fair Bandwidth Allocations in High Speed Networks Ion Stoica CMU Scott Shenker Xerox PARC Hui Zhang CMU Congestion Control in Today s Internet Rely
This report is based on sampled data. Jun 1 Jul 6 Aug 10 Sep 14 Oct 19 Nov 23 Dec 28 Feb 1 Mar 8 Apr 12 May 17 Ju
0 - Total Traffic Content View Query This report is based on sampled data. Jun 1, 2009 - Jun 25, 2010 Comparing to: Site 300 Unique Pageviews 300 150 150 0 0 Jun 1 Jul 6 Aug 10 Sep 14 Oct 19 Nov 23 Dec
CSCE 463/612 Networks and Distributed Processing Spring 2018
CSCE 463/612 Networks and Distributed Processing Spring 2018 Network Layer Dmitri Loguinov Texas A&M University March 29, 2018 Original slides copyright 1996-2004 J.F Kurose and K.W. Ross 1 Homework #3
Chapter 4: network layer. Network service model. Two key network-layer functions. Network layer. Input port functions. Router architecture overview
Chapter 4: chapter goals: understand principles behind services service models forwarding versus routing how a router works generalized forwarding instantiation, implementation in the Internet 4- Network
CSCI-1680 Link Layer Wrap-Up Rodrigo Fonseca
CSCI-1680 Link Layer Wrap-Up Rodrigo Fonseca Based partly on lecture notes by David Mazières, Phil Levis, John Janno< Administrivia Homework I out later today, due next Thursday, Sep 25th Today: Link Layer
Network layer overview
Network layer overview understand principles behind layer services: layer service models forwarding versus rou:ng how a router works rou:ng (path selec:on) broadcast, mul:cast instan:a:on, implementa:on
CMPE 150/L : Introduction to Computer Networks. Chen Qian Computer Engineering UCSC Baskin Engineering Lecture 18
CMPE 150/L : Introduction to Computer Networks Chen Qian Computer Engineering UCSC Baskin Engineering Lecture 18 1 Final project demo Please do the demo THIS week to the TAs. Or you are allowed to use
Chapter 4: network layer
Chapter 4: network layer chapter goals: understand principles behind network layer services: network layer service models forwarding versus routing how a router works routing (path selection) broadcast,
NetFPGA Hardware Architecture
NetFPGA Hardware Architecture Jeffrey Shafer Some slides adapted from Stanford NetFPGA tutorials NetFPGA http://netfpga.org 2 NetFPGA Components Virtex-II Pro 5 FPGA 53,136 logic cells 4,176 Kbit block
Network Performance: Queuing
Network Performance: Queuing EE 122: Intro to Communication Networks Fall 2006 (MW 4-5:30 in Donner 155) Vern Paxson TAs: Dilip Antony Joseph and Sukun Kim http://inst.eecs.berkeley.edu/~ee122/ Materials
CSCI-1680 Link Layer Wrap-Up Rodrigo Fonseca
CSCI-1680 Link Layer Wrap-Up Rodrigo Fonseca Based partly on lecture notes by David Mazières, Phil Levis, John Jannotti Today: Link Layer (cont.) Framing Reliability Error correction Sliding window Medium
IV. PACKET SWITCH ARCHITECTURES
IV. PACKET SWITCH ARCHITECTURES (a) General Concept - as packet arrives at switch, destination (and possibly source) field in packet header is used as index into routing tables specifying next switch in
Routing, Routers, Switching Fabrics
Routing, Routers, Switching Fabrics Outline Link state routing Link weights Router Design / Switching Fabrics CS 640 1 Link State Routing Summary One of the oldest algorithm for routing Finds SP by developing
CS144 An Introduc8on to Computer Networks
CS144 An Introduc8on to Computer Networks Packet Switching Philip Levis Oct 11, 2017 Packet Switching A Source R1 R2 R3 B Des8na8on R4 - Packets are routed individually, by looking up address in router
Emerging DRAM Technologies
1 Emerging DRAM Technologies Michael Thiems amt051@email.mot.com DigitalDNA Systems Architecture Laboratory Motorola Labs 2 Motivation DRAM and the memory subsystem significantly impacts the performance
PARALLEL ALGORITHMS FOR IP SWITCHERS/ROUTERS
THE UNIVERSITY OF NAIROBI DEPARTMENT OF ELECTRICAL AND INFORMATION ENGINEERING FINAL YEAR PROJECT. PROJECT NO. 60 PARALLEL ALGORITHMS FOR IP SWITCHERS/ROUTERS OMARI JAPHETH N. F17/2157/2004 SUPERVISOR:
Networking hierarchy Internet architecture
Networking hierarchy Internet architecture Physical layer lasers, fibers, RF, antennas, modulation, demodulation Datalink layer Ethernet, SONET Network layer IP Transport layer TCP, UDP LANs (ACES building)
Lecture 18: DRAM Technologies
Lecture 18: DRAM Technologies Last Time: Cache and Virtual Memory Review Today DRAM organization or, why is DRAM so slow??? Lecture 18 1 Main Memory = DRAM Lecture 18 2 Basic DRAM Architecture Lecture
The Evolution Path from Frames to Services
The Evolution Path from Frames to Services Alberto Degradi Manager Systems Engineering Core Technology HPSR Turin 26th June 1 Agenda Market Trends Lan Switching Evolution Routing evolution 2 Agenda Market
Last Lecture: Network Layer
Last Lecture: Network Layer 1. Design goals and issues 2. Basic Routing Algorithms & Protocols 3. Addressing, Fragmentation and reassembly 4. Internet Routing Protocols and Inter-networking 5. Router design
CSCI-1680 Link Layer Wrap-Up Rodrigo Fonseca
CSCI-1680 Link Layer Wrap-Up Rodrigo Fonseca Based partly on lecture notes by David Mazières, Phil Levis, John Jannotti Administrivia Homework I out later today, due next Thursday Today: Link Layer (cont.)
Chapter 1. Introduction
Chapter 1 Introduction In a packet-switched network, packets are buffered when they cannot be processed or transmitted at the rate they arrive. There are three main reasons that a router, with generic
Polycom Advantage Service Endpoint Utilization Report
Polycom Advantage Service Endpoint Utilization Report ABC Company 9/1/2018-9/30/2018 Polycom, Inc. All rights reserved. SAMPLE REPORT d This report is for demonstration purposes only. Any resemblance to
Polycom Advantage Service Endpoint Utilization Report
Polycom Advantage Service Endpoint Utilization Report ABC Company 3/1/2016-3/31/2016 Polycom, Inc. All rights reserved. SAMPLE REPORT d This report is for demonstration purposes only. Any resemblance to
Chapter 4 Network Layer: The Data Plane
Chapter 4 Network Layer: The Data Plane A note on the use of these Powerpoint slides: We re making these slides freely available to all (faculty, students, readers). They re in PowerPoint form so you see
Switch and Router Design. Packet Processing Examples. Packet Processing Examples. Packet Processing Rate 12/14/2011
// Bottlenecks Memory, memory, 88 - Switch and Router Design Dr. David Hay Ross 8b dhay@cs.huji.ac.il Source: Nick Mckeown, Isaac Keslassy Packet Processing Examples Address Lookup (IP/Ethernet) Where
Network Processors. Nevin Heintze Agere Systems
Network Processors Nevin Heintze Agere Systems Network Processors What are the packaging challenges for NPs? Caveat: I know very little about packaging. Network Processors What are the packaging challenges
Chapter 3 Packet Switching
Chapter 3 Packet Switching Self-learning bridges: Bridge maintains a forwarding table with each entry contains the destination MAC address and the output port, together with a TTL for this entry Destination
CSE 473 Introduction to Computer Networks. Exam 1. Your name: 9/26/2013
CSE 473 Introduction to Computer Networks Jon Turner Exam 1 Your name: 9/26/2013 1. (10 points). A user in Chicago, connected to the internet via a 100 Mb/s (b=bits) connection retrieves a 250 KB (B=bytes)
CS 43: Computer Networks Switches and LANs. Kevin Webb Swarthmore College December 5, 2017
CS 43: Computer Networks Switches and LANs Kevin Webb Swarthmore College December 5, 2017 Ethernet Metcalfe s Ethernet sketch Dominant wired LAN technology: cheap $20 for NIC first widely used LAN technology
Network Layer Introduction
Network Layer Introduction Tom Kelliher, CS 325 Apr. 6, 2011 1 Administrivia Announcements Assignment Read 4.4. From Last Time Congestion Control. Outline 1. Introduction. 2. Virtual circuit and datagram
CS 356: Computer Network Architectures. Lecture 14: Switching hardware, IP auxiliary functions, and midterm review. [PD] chapter 3.4.1, 3.2.
![CS 356: Computer Network Architectures. Lecture 14: Switching hardware, IP auxiliary functions, and midterm review. [PD] chapter 3.4.1, 3.2.](/thumbs/85/92708725.jpg "CS 356: Computer Network Architectures. Lecture 14: Switching hardware, IP auxiliary functions, and midterm review. [PD] chapter 3.4.1, 3.2.")
CS 356: Computer Network Architectures Lecture 14: Switching hardware, IP auxiliary functions, and midterm review [PD] chapter 3.4.1, 3.2.7 Xiaowei Yang xwy@cs.duke.edu Switching hardware Software switch
Scaling routers: Where do we go from here?
Scaling routers: Where do we go from here? HPSR, Kobe, Japan May 28 th, 2002 Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University nickm@stanford.edu www.stanford.edu/~nickm
Cluster Computing. Interconnect Technologies for Clusters
Interconnect Technologies for Clusters Interconnect approaches WAN infinite distance LAN Few kilometers SAN Few meters Backplane Not scalable Physical Cluster Interconnects FastEther Gigabit EtherNet 10
Introduction to Routers and LAN Switches
Introduction to Routers and LAN Switches Session 3048_05_2001_c1 2001, Cisco Systems, Inc. All rights reserved. 3 Prerequisites OSI Model Networking Fundamentals 3048_05_2001_c1 2001, Cisco Systems, Inc.
The Link Layer and LANs: Ethernet and Swiches
The Link Layer and LNs: Ethernet and Swiches EECS3214 2018-03-21 Link layer, LNs: outline 6.1 introduction, services 6.2 error detection, correction 6.3 multiple access protocols 6.4 LNs addressing, RP
DPDK Roadmap. Tim O Driscoll & Chris Wright Open Networking Summit 2017
DPDK Roadmap Tim O Driscoll & Chris Wright Open Networking Summit 2017 Agenda Overview: What is DPDK? What problems does it solve? Open source community and transition to Linux Foundation: Why is this
Network Performance: Queuing
Network Performance: Queuing EE 122: Intro to Communication Networks Fall 2007 (WF 4-5:30 in Cory 277) Vern Paxson TAs: Lisa Fowler, Daniel Killebrew & Jorge Ortiz http://inst.eecs.berkeley.edu/~ee122/
QoS Services with Dynamic Packet State
QoS Services with Dynamic Packet State Ion Stoica Carnegie Mellon University (joint work with Hui Zhang and Scott Shenker) Today s Internet Service: best-effort datagram delivery Architecture: stateless
High Performance Interconnect and NoC Router Design
High Performance Interconnect and NoC Router Design Brinda M M.E Student, Dept. of ECE (VLSI Design) K.Ramakrishnan College of Technology Samayapuram, Trichy 621 112 brinda18th@gmail.com Devipoonguzhali
CS250 VLSI Systems Design Lecture 9: Patterns for Processing Units and Communication Links
CS250 VLSI Systems Design Lecture 9: Patterns for Processing Units and Communication Links John Wawrzynek, Krste Asanovic, with John Lazzaro and Yunsup Lee (TA) UC Berkeley Fall 2010 Unit-Transaction Level
CS344 - Build an Internet Router. Nick McKeown, Steve Ibanez (TF)
CS344 - Build an Internet Router Nick McKeown, Steve Ibanez (TF) Generic Packet Switch Data H Lookup Address Update Header Queue Packet Destination Address Egress link Forwarding Table Buffer Memory CS344,
Tracking the Internet s BGP Table
Tracking the Internet s BGP Table Geoff Huston Telstra December 2000 Methodology! The BGP table monitor uses a router at the boundary of AS1221 which has a default-free ebgp routing table 1. Capture the
CS 43: Computer Networks. 20: The Network Layer November 5, 2018
CS 43: Computer Networks 20: The Network Layer November 5, 2018 Last Class: TCP Rate and Flow Control TCP has mechanisms to control sending rate: Flow control: don t overload receiver Congestion control:
A Single Chip Shared Memory Switch with Twelve 10Gb Ethernet Ports
A Single Chip Shared Memory Switch with Twelve 10Gb Ethernet Ports Takeshi Shimizu, Yukihiro Nakagawa, Sridhar Pathi, Yasushi Umezawa, Takashi Miyoshi, Yoichi Koyanagi, Takeshi Horie, Akira Hattori Hot
Processor Architectures At A Glance: M.I.T. Raw vs. UC Davis AsAP
Processor Architectures At A Glance: M.I.T. Raw vs. UC Davis AsAP Presenter: Course: EEC 289Q: Reconfigurable Computing Course Instructor: Professor Soheil Ghiasi Outline Overview of M.I.T. Raw processor
Cisco IOS Switching Paths Overview
This chapter describes switching paths that can be configured on Cisco IOS devices. It contains the following sections: Basic Router Platform Architecture and Processes Basic Switching Paths Features That
Data Communication & Networks G Session 7 - Main Theme Networks: Part I Circuit Switching, Packet Switching, The Network Layer
Data Communication & Networks G22.2262-001 Session 7 - Main Theme Networks: Part I Circuit Switching, Packet Switching, The Network Layer Dr. Jean-Claude Franchitti New York University Computer Science
Overview Computer Networking What is QoS? Queuing discipline and scheduling. Traffic Enforcement. Integrated services
Overview 15-441 15-441 Computer Networking 15-641 Lecture 19 Queue Management and Quality of Service Peter Steenkiste Fall 2016 www.cs.cmu.edu/~prs/15-441-f16 What is QoS? Queuing discipline and scheduling
Lecture 14: Cache Innovations and DRAM. Today: cache access basics and innovations, DRAM (Sections )
Lecture 14: Cache Innovations and DRAM Today: cache access basics and innovations, DRAM (Sections 5.1-5.3) 1 Reducing Miss Rate Large block size reduces compulsory misses, reduces miss penalty in case