NetFPGA Hardware Architecture

Transcription

1 NetFPGA Hardware Architecture Jeffrey Shafer Some slides adapted from Stanford NetFPGA tutorials

2 NetFPGA 2

3 NetFPGA Components Virtex-II Pro 5 FPGA 53,136 logic cells 4,176 Kbit block RAM 2 x PowerPC cores (not used) Gigabit Ethernet ports - 4 Memory SRAM 4.5MB (2 parallel banks - 18Mbit / 2.25 MByte) DDR2 DRAM 64 MBytes PCI Bus Interface 32 bits / 33 MHz / 166 Mbit/s bandwidth Spartan FPGA used as PCI controller Multi-gigabit I/O (2 SATA ports) Allows multiple NetFPGAs within a PC to be chained together More Details? Tech specs: Schematic: How does the NetFPGA board become a router? 3

4 Reference Designs NetFPGA design team has provided Reference NIC 4 port Ethernet NIC Reference Router 4 port IP router What factors influenced these designs? Simple architecture (for use in education) Fits on the FPGA and meets timing constraints These designs do not necessarily model a commercial NIC or router We ll talk about real devices later this semester We ll give you the NIC design, and you will turn it into a switch and IP router 4

5 Router Tasks (Per Packet) Receive packet on incoming port Read destination Where is packet going? Lookup destination in forwarding table Determine next hop address and outgoing port If not found, use ICMP to handle error Lookup link-layer address of next hop (e.g. Ethernet ) If not found, use ARP to resolve address Manipulate IP header Decrement TTL and update header checksum Manipulate link-layer header This is only a partial list of router tasks (Real routers, and your project, do more!) Modify link-layer source and destination address, update CRC Buffer packet in the output queue Transmit packet onto outgoing link 5

6 Generic Datapath Architecture Header Processing Data Hdr Data Hdr Lookup Dst IP Address Update Header Queue Packet IP Address Next Hop Forwarding Table Buffer Memory 6

7 NetFPGA IP Router Management & CLI Exception Processing Forwarding Table Routing Protocols Routing Table Switching Software Hardware Control Plane Linux user-level processes Datapath FPGA on PCI board 7

8 NetFPGA Block Diagram NetFPGA PCI Board Four Gigabit Ethernet Interfaces 1GE PHY 1GE PHY 1GE PHY 1GE PHY 1GE 1GE 1GE 1GE FIFO packet buffers Virtex-II Pro 5 FPGA Custom Router Router Pipeline Composed of: of: Verilog Verilog source source code code Xilinx Xilinx Cores Cores Spartan Spartan FPGA FPGA PCI PCI Interface Interface 18Mb SRAM 64MB DDR2 SDRAM 18Mb SRAM 3 Gb SATA Board to Board Interconnect Host Computer Linux OS - NetFPGA Kernel driver User-defined software networking applications 8

9 Router Pipeline Five stages Input Input Arbitration Routing Decision and packet modification Output Queuing Input Arbiter Output Port Lookup Output Packet-based module interface Output Queues Pluggable design 9

10 Inter-module Communication Data (64 bits) Ctrl (8 bits) wr rdy 1

11 Inter-module Communication Headers are appended to packet Ctrl Word (8 bits) x y x1 Data Word (64 bits) Module Hdr Last Module Hdr Start of Ethernet Header Start of IP Header Last word of packet Router control data such as packet length, input port, output port, Packet being routed (including its headers) Ctrl x = Packet Ctrl x1 = End of packet 11

12 Exploring the Pipeline Input Arbiter Output Port Lookup Output Queues 12

13 Rx Queue (port ) Eth Hdr: Dst = (), Ethertype = IP IP Hdr: IP Dst: , TTL: 64, Csum:x3ab4 Data 13

14 Rx Queue (port ) xff Pkt length, input port = Eth Hdr: Dst = (), Ethertype = IP IP Hdr: IP Dst: , TTL: 64, Csum:x3ab4 Data 14

15 Input Arbiter Pkt Pkt Pkt 15

16 Output Port Lookup 16

17 Output Port Lookup 1- Check input port consistent with Dst 2- Check TTL, checksum 3- Lookup next hop IP & output port (LPM) 4- Lookup next hop address (ARP) xff xff Pkt length, Input Pkt length, port =, Output input port = 4 EthHdr: EthHdr: Dst Dst = nexthop = Src Src = port = x, 4, Ethertype = IP IP Hdr: IP Dst: , TTL: 64, 63, Csum:x3ab4 Csum:x3ac2 Data 5- Update header with output port(s) 6- Modify Dst and Src addresses 7-Decrement TTL and update checksum 17

18 Output Queues OQ OQ4 OQ7 18

19 Tx Queue 19

20 Tx Queue x4 xff output port = 4 Pkt length, input port = EthHdr: Dst = nexthop Src = port 4, Ethertype = IP IP Hdr: IP Dst: , TTL: 64, 63, Csum:x3ab4 Csum:x3ac2 Data 2

21 Any Questions About Pipeline? Input Arbiter Output Port Lookup Output Queues 21

22 Course Projects You have to build the Output Port Lookup module shown in the preceding slides The initial version provided is a simple NIC Directly connects input port A to output port A No intelligence! You will build Output Port Lookup modules to accomplish Ethernet Hub Learning Ethernet Switch IP Router 22

23 What is Each Group Provided? Monitoring Software Control Software User Space Linux Kernel PCI VI VI VI VI NetFPGA Router Hardware GE GE GE GE 23

24 Per-Group Network Topology 24

25 Next Three Fridays (16 th, 23 rd, 3 th ) Meet in Lab (Abercrombie A123) Goals Learn about NetFPGA library and basic reference NIC design Write Verilog Turn the NIC into an Ethernet Hub Build hardware bitfile Simulate design Test design on real hardware 25

26 Assignment Before Friday s tutorial: Go to Tutorials page at Follow the link to Hardware Initial Setup (under the Hardware Tutorial section) Complete all tasks (5 minutes) Setting environment variables for tools 26