Static Round-Robin Dispatching Schemes for Clos-Network Switches'

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1 Static RounRobin Dispatching Schemes for ClosNetwork Switches' Konghong Pun Mounir Hami Department of Computer Science Hong Kong University of Science an Technology Clear Water Bay, Kowloon, Hong Kong Abstracf The Closnetwork is wiely recognize as a scalable architecture for highperformance switches an routers. One of the key challenges in esigning a Closnetwork switch for a highspee environment is the esign of the ispatchinglscheuling so as to be efficient for a wie range of traffic patterns, yet practical to be implemente in harware. Base on the Static RounRobin scheuling technique, we propose the SRRD cell ispatching algorithm an its variants for Closnetwork switches in this paper. Our algorithms are base on the requestgrantaccept (RGA) hanshaking scheme, which can be implemente using simple istribute arbiters at the input an output of the Closnetwork. The intuition behin our SRRD schemes is to esynchronize the pointers of the arbiters in a static way an by to use a rotatingsearch technique to improve the performance uner nonuniform traffic. Our simulation results will emonstrate that our algorithms achieve the lowest elay an highest throughput among all other relate schemes. In aition, their harware implementations seem to be even simpler than that of relate algorithms. I. INTRODUCTION Most hghperformance Internet backbone routers toay are built base on a crossbar switch with a centralize scheuler. Several practical an effective crossbar switches along with the appropriate scheuling have been propose [7] [8]. However, the complexity of switching harware an scheuling algorithms usually epens on the square of the number of switch ports. This makes them ifficult to scale to a large size in a costeffective way. As a result, switch architectures base on the threestage Closnetwork are very attractive ue to their moularity an scalability. But one of the challenges is how to esign a istribute scheuling algorithm. Closnetwork switch architectures can be categorize into two types. The first one has buffers in the seconstage, such as the WUGS architecture in [2]. The function of the buffers is to resolve contention among cells from ifferent firststage moules. However, cells may be missequence at the output ports. It requires a resequence function, which is ifficult to implement when the port spee increases. The secon type of architecture has no buffers in the seconstage, such as the ATLANTA switch in [3]. This approach is more promising an will be consiere in this paper. The concurrent ispatching (CD) in the ATLANTA switch is a ranombase scheuling algorithm [3] [4]. It can fully istribute traffic evenly to the central moules but the contention cannot be avoie. This is similar to the PIM algorithm for crossbar switches [7]. In particular, the CD algorithm cannot achieve a high throughput unless the internal banwith is expane. In crossbar switches, rounrobin arbitration has been evelope to overcome the throughput limitation of the PIM algorithm, such as FIRM an SLIP [8]. Similarly, the concurrent rounrobin ispatching (CRRD) an the concurrent masterslave ispatching (CMSD) schemes have been recently propose for Closnetwork switches in [5] an [6]. They have been shown to achieve 100% throughput uner uniform traffic with no buffers an no banwith expansion in the seconstage moules. Recently, a novel scheuling algorithm terme Static RounRobin (SRR) has been propose for crossbar switches [I]. The SRR has been shown to consierably improve the performance of most rounrobin arbiters in crossbar switches using an even simpler harware implementation. Base on this technique, we propose the Static RounRobin Dispatching (SRRD) algorithm an its variants for Closnetwork switches in this paper. The intuition behin the SRR esign is to esynchronize the arbiters' pointers in a static way an to use a rotatingsearch technique to improve the performance uner nonuniform traffic. The rest of this paper is organize as follows. Section I1 introuces some backgroun knowlege, incluing the switch moel, CD, CRRD an CMSD schemes. Section 111 escribes three SRRDbase scheuling algorithms. Section IV analyzes the performance of the propose algorithms an their harware implementation. Finally, we conclue this paper in section V. 11. BACKGROUND KNOWLEDGE A. Switch Moel The switch architecture use in this paper is base on [3], an is shown in Figure 1. The input an output stages are both compose of sharememory moules, each with n port interfaces. They are fully interconnecte through a central stage that consists of bufferless crossbars of size k x k. In the switch, there are k input moules (IM), m central moules (CM), an k output moules (OM). An OMG;) has n buffere output ports, OPG;,h). Each output port buffer can receive at most m cells from m central moules an sen at most one cell to the output line at one timeslot. An lm(i) has nk virtual output queues, VOQ(i,j,h), for storing cells that go from IM(i) to 0Pfi.h) at OM@. Each virtual output queue can receive at most n cells from n input ports an sen one cell to the central moule. An IM() has m output links, LI(,r), connecting to each CM(r). An CM(r) has k output links, LC(rj), connecting to each OM@. ' This research work was partly supporte by a grant from the Hong Kong Research Grant Council uner the grant HKUST6181/01E. 329

2 IP(I.01 + vw1i.0.01 lp"'ho VOO(l.k4.hl) OM (il Figure 1. The Closnetwork Switch Moel B. Concurrent Dispatching (CO) m=.. m The istribute architecture implies the presence of multiple contention points in the switch. The ATLANTA switch propose the CD algorithm with highly istribute nature [3]. It works as follows. In each timeslot, each IM ranomly selects up to m VOQs an ranomly sens the requests to CMs. If there is more than one request for the same output link in a CM, it grants one request ranomly. Finally, the grante VOQs will sen to the corresponing OP in the next timeslot. The original CD algorithm in [3] applies a backpressure mechanism in the ispatching process. We only escribe its basic concept an characteristic in this paper. We also assume that the buffer size in IMs an OMS is large enough to avoi cell loss. Hence we can focus the iscussion on the properties of the ispatching algorithms. C. Concurrent RounRobin Dispatching (CRRD) The CRRD has been propose in [5] to overcome the throughput limitation of the CD. It is base on the requestgrantaccept (RGA) hanshaking scheme. In Phase 1, it employs an iterative matching between VOQs an output links in each IMs. Phase 2 then performs contention control for the output links in CMs. Initialization: Each VOQ(i,j,h) is associate with an arbiter V(i,j,h) with pointer PV(i,j,h). Each Ll(i.r) is associate with an arbiter L(i,r) with pointer PL(i,r). Each LC(r,j) is associate with an arbiter C(r,j) with pointer PC(rJ). VOQs are arrange in an orer of VOQ(i.v), where v = hk+j. Set PV(i,j,h) = PL(i.r) = PC(rj) = 0. Step 7: Request. Each unmatche, nonempty VOQ(ij,h) sens a request to every output link arbiter L(i,r). Step 2: Grant. Each output link arbiter L(i,r) search one request in a rounrobin fashion starting from pointer PL(i.r) an sens the grant to the selecte VOQ. Step 3: Accept. Each VOQ arbiter V(i,j,h) search one grant in a rounrobin fashion starting from pointer PV(i,j.h) an sens the accept to the selecte output link Ll(i,r). Phase 2: Matching between IM an CM: Step 7: Request. Each IM output link Ll(i,r), who was accepte by a VOQ(i,j,h) in Phase 1, sens the request to the CM output link arbiter C(r,j). Step 2: Grant. Each CM output link arbiter C(r,j) search one request in a rounrobin fashion starting from pointer PC(r,j). It then sens the grant to the selecte IM an upate the pointer PC(r,j) to one position beyon the grant one. Step 3: Accept. If the IM receives the grant from the CM, it sens the hea cell from the matche VOQs in next timeslot an the matche pointers PL(i.r) an PV(i,j,h) are upate to one position beyon the matche one. As escribe above, CRRD uses three sets of rounrobin arbiters to resolve the contentions in IMs an CMs. The esynchronization effect of the rounrobin pointers in CRW works exactly as in islip for crossbar switches. D. Concurrent MasterSlave Dispatching (CMSD) The CMSD is an improve version of the CRRD by reucing the interconnection complexity of ispatching scheulers an hence the ispatching time [6]. CMSD employs two sets of arbiters in IM, the master an the slave one. They operate concurrently in a hierarchal rounrobin manner. The CMSD iffers from the CRRD only on the iterative matching process in Phase 1. Initialization: Each VOQ(i,j,h) is associate with an arbiter V(i,j,h) with pointer PV(i,j,h). Each Ll(i,r) is associate with a master arbiter ML(i,r) with pointer PML(i,r), an also associate with a slave arbiter SL(i,j.r) with pointer PSL(ij,r). Each LC(rj) is associate with an arbiter C(rJ) with pointer PC(r,j). Set PV(i,j,h) = PML(i,r) = PSL(i,j,r) = PC(rj) = 0. Step 7: Request. Each unmatche, nonempty VOQ(i,j,h) sens a request to every slave output link arbiter SL(i,j,r). At same time, each VOQ Group G(i,j) that has at least one unmatche, nonempty VOQ sens a request to every master output link arbiter ML(i,r). Step 2: Grant. Each slave arbiter SL(i,j,r) search one VOQ's request in a rounrobin fashion starting from pointer PSL(i,,j,r). At same time, each master arbiter ML(i,r) search one VOQ Group's request in a rounrobin fashion starting from pointer PML(i,r). Finally, SL(i$,r) sens the grant to VOQ(i,j,h) only if j has been selecte by ML(i,r). Step 3: Accept. Each VQQ(i,j,h) search one grant in ii rounrobin fashion starting from pointer PV(i,j,h) an sens the accept to the selecte output link Ll(i,r). Phase 2: Matching between IM an CM: These Operations are the same as CRRD, except that the pointers PSL(i,j,r) an, PML(i,r), instea of PL(i,r), are upate to the one position beyon the matche one SRRD SCHEMES A. Static RounRobin Dispatching (SRRD) The esynchronization effect of pointers in the rounrobin arbiters plays an important role in the performance of the switch scheuling algorithms [l]. The more esynchronize the pointers are, the lower is the elay of the switch. As a result, by using the static esynchronize rounrobin pointers, we can improve the CMSD scheme with following changes. 330

3 Initialization: These oointers are the same as CMSD. excedt that their values are set to PV(i,j,h) = h, PSL(i,j,r) = r, PML(i,r) = (i+r) % k, PC(r,j) = i if (PML(i,r)==j). These Operations are the same as CMSD. Phase 2: Matching between IM an CM: These Operations are the same as CMSD, except that the pointers PML(i,r) & PC(rj) are always incremente by one (mo k) an PSL(ij,r) an PV(i,j.h) remain unchange, no matter there is a match or not. The novelty of our SRRD is emonstrate by the initial configuration of the rounrobin pointers as shown in Figure 2. All pointers are artificially set to be esynchronize to resolve the contention points. This allows the maximum matching from IPS to OPs if all VOQs have a cell available. In other wors, SRRD will always achieve 100% throughput uner uniform traffic. Our SRRD will not introuce any starvation in VOQs uner any traffic pattern. This is because the pointers PML(i,r) & PC(rj) are incremente uring each timeslot an. Hence Each VOQ will be ispatche at least once within a roun. Note that PSL(i,j,h) & PV(i,j,h) are kept constant. Consequently, all cells in VOQ(i,j,h) will be primarily scheule through CMP). This will not affect the elay performance or the fairness. B. SRRDrl: Rotating Directe by Time The performance of SRRD is expecte to be egrae uner unbalance traffic. This is because several arbiters may grant to the same request at the same time. It can be solve by rotating the search irections of the rounrobin arbiters [I]. In fact, all conventional arbiters search in clockwise irection. Now, we will allow the rounrobin arbiters to search the requests in clockwise irection as well as in anticlockwise irection. The SRRDrl algorithm is a variant of SRRD such that the arbiters will search the requests in clockwise irection an anticlockwise irection alternatively, each for one time slot. Practically, we can keep track of time by a 0/1 counter, which will increment by one (mo 2) in each cell time. All counters are initialize to 0 at cell time 0. The SRRDrl is the same as the SRRD except in the Step 2 of Phase 1: If (counter == 0), ML(i.r) search one request in clockwise rounrobin fashion. If (counter == I), ML(i,r) search one request in anticlockwise rounrobin fashion. C. SRRDr2: Rotating Directe ly Moule Number Although the SRRDr1 scheme will serve nonempty requests before an after the pointer with an equal chance, it will only grant one of them. This will egrae the system performance when the traffic is nonuniform an the number of ports is large. We introuce another improve scheme, SRRDr2. In each time slot, half of the pointers will rotate in clockwise irection, an another half will rotate in anticlockwise irection, epening on the central moule number r. The SRRDr2 is similar to the CRRDrl except: Initialize the counter in ML(i,r) to 0 if r is even, to 1 if r is o. Iv. ANALYSIS OF SRRD SCHEMES A. Performance uner Balance Trafic In this section, we compare the elay performance of the various algorithms. The relative elay is obtaine by iviing the average total elay by the elay prouce by an outputqueue switch, which is known as the ieal V0Qli.i.h) Arbiters Ll(i,r) Slave Arbiters L1li.r) Master Arbiters LC(i,r) Arbiters Figure 2. Initial Configuration of SRRD Arbiter Pointers (n=k=m=3) 331

4 L switch an hence is use for reference. We use the Closnetwork setting of m=n=k=8, which correspons to a port size of N=64. Figure 3(a) shows the comparison uner Uniform trafic, in which ceil arrival follows a Bernoulli 1.i.. process. Figure 3 (b). shows the comparison uner Bursty trafic, in which cell arrives in each time slot uring the busy perio an no cell arrives in the ile perio. The results show that all algorithms acheve 100% throughput uner Uniform traffic an Bursty traffic, except the CD algorithm. The elay of the CRRD is lower than the CMSD in the high loa region uner uniform traffic, but the situation is reverse uner Bursty traffic. This is because the master arbiter of CMSD can choose a VOQ group, which affects the matching more seriously. As expecte, the performance of the SRRDbase algorithms is significantly better than the other algorithms. This is ue to the full esynchronization of the SRRD pointers. Hence the contentions in the CM an the OM are almost minimize for uniform incoming traffic. Figure 3 emonstrates that one iteration is sufficient to achieve 100% throughput for all rounrobin scheuling algorithms. The number of iterations in Phase 1 just improves the elay performance. But the elay of SRRD almost converges for only two iterations. B. Perfomzance uner Unbalance Traflc The first type of unbalance traffic we consier is the BiDiagonal trafic. In which, input i has cells only Sor output j = i or (i+z) mo N. Its loa matix is escribe as follows, where p enotes the normalize loa. if j=i if j = (i + 1) mo N otherwise This type of traffic is more ifficult to scheule compare with uniform traffic. As shown in Figure 4 (a), the basic SRRD has the worst performance even when compare with CRRD or CMSD. However, both rotating schemes of SRRD can achieve 100% throughput uner the BiDiagonal traffic. Their elay performances are also very close to the outputqueue switches. We efine another type of unbalance traffic, Trans Diagonal trafic with following loa matrix. For each input i, half of the traffic is going to output i, an the remaining traffic is uniformly istribute among other outputs. * CRRD * CMSD SRRD SRRDrl SRRDrZ (a) Uniform Traffic CMSD SRRD SRRDrl (a) BiDiagonal Traffic Namalire Loa Nmali2B Loa (b) Bursty Traffic 10' (b) TransOiagonal Trafflc h P 2 10' 5 P D a" to' Namakze Loa Numalize Loa Figure 3. Comparison in Balance Traffic Figure 4. Comparison in Unbalance Traffic 332

5 P 12 Pi,i = { p 12(N 1) if j=i otherwise This type of traffic is particularly ifficult to scheule in the Closnetwork switches. As shown in Figure 4 (b), no algorithm is able to acheve 100% throughput. However, in terms of maximum achievable throughput, our SRRDbase algorithms are still better than the others In all types of traffic, our secon variant, SRRDr2, achieve the lowest elay an highest throughput. C. Harware Implementation Rounrobin arbiters are use in the implementation of SRRDbase schemes. In our SRRDbase schemes, the pointers associate with SL(ij,r) an V(ij,h) remain unchange all the time, an the pointers associate with ML(i,r) an C(rj) are always upate by one in each cell time. This requires no information transfer uring the scheuling. As a result, our rounrobin scheulers are much simpler than those use in SLIP. Figure 5 epicte the scheuler architecture in each IM. The state memory uses nk bits to recor whether a VOQ is empty or nonempty, an k bits to recor whether a VOQ Group is empty or nonempty. These bit vectors are representing Step 1: Request. The master arbiters an slave arbiters implementing Step 2: Grant. Each slave arbiter SL(i,j,r) search one VOQ s request in a rounrobin fashion starting from pointer PSL(i,,j,r). At the same time, each master arbiter ML(i,r) searches one VOQ Group s request. Then SL(i,j,r) sens the grant to VOQ(i,j,h) only ifj has been selecte by ML(i,r). Finally, each VOQ(i,j,h) search one grant in a rounrobin fashion starting from pointer PV(i,j,h), implementing Step 3: Accept. The ecision is then save in the ecision register which will be fe back to each master arbiter for the next iteration s arbitration. One rawback of our switch moel in Figure 1 is that the input an output stages arc both compose of sharememory moules. This is associating a memory speeup of n in each IM an m in each OM. However, these speeup problems can be solve by replacing them with inputqueue switches, for example. V. CONCLUSION The Closnetwork architecture is wiely recognize as a very scalable architecture for highspee switching system. So far, only limite success has been reporte in the esign of practical istribute scheuling schemes for the Closnetwork. The ATLANTA switch is an example of a commercially successful Closnetwork switch. But it requires internal banwith speeup. Recently, the CRRD an CMSD algorithms have been propose in orer to overcome the throughput limitation an implementation complexity problem. In this paper, we introuce three improve algorithms base on the Static RounRobin technique. Uner various traffic moels, we have shown by simulation that our algorithms achieve the lowest elay an the highest throughput among all other relate schemes. In aition, their harware implementations seem to be even simpler than that of relate algorithms. I / I W1 Counter REFERENCES Y. Jiang an M. Hami, A fully esynchronize rounrobin matching scheuler for a VOQ packet switch architecture, IEEE Workshop on High Performance Switching an Routing, pp I, May T. Cheney, J.A. Fingerhurt, M. Flucke an J.S. Tumer, Design of a gigabit ATM switch, Proceeings of IEEE Infocom 97, vol. 1, pp. 211, April F.M. Chiussi, J.G. Kneuer an V.P. Kumar, Lowcost scalable switching solutions for broaban networking: the ATLANTA architecture an chipset, IEEE Communication Magazine, vol. 35, no.3, pp. 4453, December F.M. Chiussi, an A. Francini, A istribute scheuling architecture for scalable packet switches, IEEE Journal on Selecte Areas in Communications, vol. 18, no. 12, pp , December E. Oki, Z. Jing, R. RojasCessa, an J. Chao, Concurrent rounrobin ispatching scheme in a closnetwork switch, IEEE International Conference on Communications, vol. 1, pp , June2001. E. Oki, Z. Jing, R. RojasCessa, an J. Chao, Concurrent rounrobinbase ispatching schemes for closnetwork switches, unpublishe. T. Anerson, S. Owicki, J. Saxe, an C. Thacker, High spee switch scheuling for local ara networks, ACM Transaction on Computer Systems, vol. 1 I, no. 4, pp , November N. McKeown, The SLIP scheuling algorithm for inputqueue switches, IEEE/ACM Transactions on Networking, vol. 7, no. 2, pp , April