THE ASYNCHRONOUS transfer mode (ATM) has been

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1 60 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 1, FEBRUARY 1999 Analysis of Nonblocking ATM Switches with Multiple Input Queues Ge Nong, Student Member, IEEE, Jogesh K Muppala, Member, IEEE, Mounir Hamdi, Member, IEEE Abstract An analytical model the permance analysis of a multiple input queued asynchronous transfer mode (ATM) switch is presented in this paper The interconnection network of the ATM switch is internally nonblocking each input port maintains a separate queue of cells each output port The switch uses parallel iterative matching (PIM) [7] to find the maximal matching between the input output ports of the switch A closed-m solution the maximum throughput of the switch under saturated conditions is derived It is found that the maximum throughput of the switch exceeds 99% with just four iterations of the PIM algorithm Using the tagged input queue approach, an analytical model evaluating the switch permance under an independent identically distributed Bernoulli traffic with the cell destinations unimly distributed over all output ports is developed The switch throughput, mean cell delay, cell loss probability are computed from the analytical model The accuracy of the analytical model is verified using simulation Index Terms Analytical modeling, ATM switch, computer simulation, permance evaluation I INTRODUCTION THE ASYNCHRONOUS transfer mode (ATM) has been recommended by CCITT as an integrated transport technique future broad-b ISDN As a result, there is a growing interest in identifying suitable switching architectures ATM Virtually all proposals of switching fabric architectures ATM networks are based on self-routing structures in which each packet autonomously find its path through the interconnection network to the desired output port [1] [3] This feature enables the design of switching fabrics characterized by a very high throughput, on the order of gigabits per second These design proposals were based on various types of queueing strategies: input queueing, dedicated internal queueing, shared internal queueing, or output queueing [2], [3] Each of these queueing strategies is characterized by certain advantages drawbacks The simplest approach, however, is input queueing In this architecture, each input port maintains a first-in-first-out (FIFO) queue of cells, only the first cell in the queue is eligible transmission during a given time slot The drawback of FIFO queueing is that, when the cell at the Manuscript received July 21, 1997; revised March 2, 1998; approved by IEEE/ACM TRANSACTIONS ON NETWORKING Editor H J Chao This work was supported in part by the Hong Kong Research Grant Council under Grant RGC/HKUST 6026/97E The authors are with the Department of Computer Science, The Hong Kong University of Science Technology, Clear Water Bay, Kowloon, Hong Kong ( nong@csusthk; muppala@csusthk; hamdi@csusthk) Publisher Item Identifier S (99) head of the queue is blocked, all cells behind it in the queue are prevented from being transmitted, even when the output port they need is idle This is called head-of-line (HOL) blocking It was shown through mathematical analysis computer simulation that HOL blocking limits the throughput of each input port to a maximum of 586% under unim rom traffic, much lower than that bursty traffic [4], [5] Various approaches have been proposed to overcome the problems associated with FIFO input queueing: adopting a switch expansion, a windowing technique, or a channel grouping technique [2] In the mer case, the internal switch bwidth is exped, using replication example, so that it can transmit more than one cell to an output port in a single time slot Windowing is a technique conceived to relieve the HOL blocking by also allowing non-hol cells to contend the switch output ports In particular, adopting a window of depth means that if a cell in position,,( identifies the HOL position) is blocked owing to a conflict the switch output port, a chance is given to the cell in position until a search of depth has been completed Channel grouping is another technique that can be used with input queueing to improve the switch throughput In this technique, the switch output ports are subdivided into groups of size each cells address groups, not single links of a group Such arrangement is typical of a transit environment in which the switch interfaces a limited number of downstream switches with links to each of them Implementing channel groups in an ATM switch is a nontrivial task given the high rates of the links, since in each slot not only we have to guarantee the absence of external conflicts, but also to allocate at the transmission time each output port in a group to a specific input port addressing that group with its HOL cell Of particular interest to us in this paper is a recent technique termed parallel iterative matching (PIM) variations of PIM, that are used to reduce the HOL blocking [7], [9] [12] In this technique each input port maintains a separate queue each output port During a single time slot, a maximum of one cell per input port can be transferred, a maximum of one cell per output port can be received The switch operation is based on a parallel iterative matching algorithm to find the maximal matching between the inputs outputs of the switch It is shown that the number of iterations needed to find a maximal matching is in the worst case, in the average case However, it was shown through computer simulation, that with as few as four iterations, the throughput of a switch exceeds 99% [7] As a result, this switch architecture has received a lot of attention from the research /99$ IEEE

2 NONG et al: ANALYSIS OF NONBLOCKING ATM SWITCHES 61 community, many commercial experimental ATM switches based on this queueing technique have already been built, such as the DEC Systems AN2 switch the Tiny Tera switch [7], [8] So far, the permance evaluation of PIM switches appearing in the literature have been based on simulation The main reason that is the fact that mathematically analyzing PIM ATM switches is difficult The inventors of PIM switches acknowledge this fact by saying, In general, it is difficult to mathematically analyze the permance of a PIM switch, even the simplest traffic models The problem lies in the evolution interdependence of the state of each arbiter their dependence on arriving traffic [7], [9] To the best of our knowledge, the research work in this paper is the first attempt at analytical modeling of the permance of the PIM switches Permance parameters such as throughput, mean cell delay, cell loss probability are important to evaluate the permance of an ATM switch For example, a cell loss probability requirement of 10 is not uncommon [14] As a result, estimating the rare cell loss probability by simulation is inefficient sometimes impossible [17] Consequently, analytical models are of great importance in solving these problems The contribution of this paper is twofold First, we analyze the permance of the PIM ATM switch under saturated conditions [23], ie, assuming that none of the input queues is empty, so as to give the maximum throughput of the switch With this assumption, a recursive closed-m expression computing the maximum throughput of the switch is derived Using this expression, we show that one iteration, the maximum throughput of the switch converges to 0632 as the size of the switch increases, which agrees with the results given in [7] We also show that the maximum throughput a switch of any size exceeds 99% with just four iterations of the PIM scheduling algorithm It is worth noting that a 100% throughput can be achieved with the same architecture using a maximum weight bipartite matching algorithm [25] Another algorithm in [9] can also achieve 100% throughput with this same architecture We then develop an analytical model of the PIM switch with finite input buffers using the tagged queue approach [6], [15], [16] Assuming an independent identically distributed Bernoulli input traffic with the cell destinations distributed unimly over all the outputs, we compute interesting permance measures the PIM switch including throughput, mean cell delay, cell loss probability as a function of the offered load switch size The accuracy of our analytical model has been verified using simulation The results from the analytical model match closely with the simulation results This model will be extended in the future under more realistic traffic assumptions such as bursty correlated traffic This will render our mathematical analysis more complex We consider the results of this paper as the foundation solving the more difficult problem involving bursty correlated traffic [24] The remainder of this paper is organized as follows Section II introduces the switch model PIM scheduling algorithm The next two sections present the analytical Fig 1 Architecture of the multiple input queues ATM switch (N 2 N) model of PIM switches both under saturated conditions, iid Bernoulli traffic In particular, Section III presents recursive equations the maximum throughput of the switch Section IV develops the analytical model based on the tagged queuing approach Equations computing interesting permance measures including throughput, mean cell delay, mean cell loss probability are derived in this section Numerical results obtained from the analytical model are presented switches of different sizes in Section V, compared with the results from simulation Finally conclusions are presented in Section VI II THE SWITCH MODEL AND PIM SCHEDULING In this section, we present an overview of the PIM ATM switch architecture define the switch scheduling algorithm (ie, PIM) Interested readers may refer to [7], [9] further details A The Switch Model The ATM switch under consideration is an nonblocking switch, ie, the inputs are connected to the outputs via a nonblocking interconnection network (eg, crossbar switch) A cell may be sent from any input to any output, provided that no more than one cell is sent from the same input no more than one cell is received by the same output Each input queue of the switch is a rom access buffer This rom access buffer can be used to construct FIFO queues, each of which is used to store the cells that are destined one of the output ports The architecture of this switch is shown in Fig 1 The first cell in each queue can be selected transmission across the switch in each time slot, with the following constraints: 1) only one cell from any of the queues in an input port can be transmitted in each time slot; 2) only one cell can be transmitted from the input ports to an output port of the switch at any given time slot In other words, at most one cell could be received by a single output port

3 62 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 1, FEBRUARY 1999 As mentioned above, the reason using a rom-access buffer instead of a conventional FIFO queue is to avoid the HOL blocking Two criteria must be considered designing the switch: 1) the switch must route as many cells among the ones that arrived at its inputs as possible to the appropriate outputs to maximize the throughput; 2) the switch must solve the output contention problem (ie, more than one cell can be destined the same output port) As a result, the switch scheduling algorithm that decides, each time slot, which inputs transmit their queued cells to which outputs is of paramount importance One such effective algorithm is PIM [7], [9] B PIM For switches used in high-permance ATM networks, the switch scheduling algorithm must be able to provide high throughput, low latency, graceful degradation under heavy traffic loads Anderson et al [7] considered the architecture of a nonblocking switch with rom access buffers (as shown in Fig 1), cast the switch scheduling problem as a bipartite matching problem of finding conflict-free pairing of inputs to outputs [13] The high throughput low latency of an ATM switch dictates that the scheduling algorithm must be able to find a matching of as many conflict-free pairings as possible, using as little time as possible Note that a maximum matching is a matching with the maximum number of paired inputs outputs, while maximal matching is one in which no unmatched input has a queued cell destined an unmatched output (ie, no parings can be trivially added) Untunately, all of the conventional bipartite maximum matching algorithms have high time complexity with regard to the time constraint imposed by 53-byte ATM cells gigabit per second links As a solution, Anderson et al [7] proposed an algorithm, called parallel iterative matching, to find a maximal matching The algorithm proposed by Anderson et al uses parallelism, romness, iteration to find a maximal matching between the inputs that have queued cells transmission the outputs that have queued cells (at the inputs) destined them Maximal matching is used to determine which inputs transmit cells over the nonblocking switch to which outputs in the current time slot Specifically, their matching algorithm iterates the following three steps until a maximal matching is found or until a fixed number of iterations is permed Request: Each unmatched input sends a request to every output which it has a queued cell Grant: If an unmatched output receives any requests, it grants to one by romly selecting a request unimly over all requests Accept: If an input receives grants, it accepts one by selecting an output among those that granted to this input By considering only unmatched inputs outputs, each iteration only considers connections not made by earlier iterations Note that in step two above, the independent output schedulers romly select a request among contending requests This has three effects First, Anderson et al [7] show that each iteration will match or eliminate on average at 3/4 of the remaining possible connections thus the algorithm will converge to a maximal match in (log N) iterations Second, it ensures that all requests will eventually be granted Consequently, no input queue is starved Third, it means that no memory or state is used to keep track of how recently a connection was made in the past To facilitate the mathematical analysis in the rest of the paper, we modify the above PIM algorithm However, the modified PIM algorithm is logically equivalent to the original PIM algorithm As a result, the permance analysis of the modified PIM algorithm is exactly applicable to the original PIM algorithm The modified PIM algorithm iterates the following two steps until a maximal matching is found, or until a fixed number of iterations are permed: 1) each unmatched input chooses an output unimly over all unmatched outputs which it has queued cells sends a request to it; 2) if an unmatched output receives any requests, it chooses one unimly over all requests to grant notifies each requesting input The logical equivalence between the modified PIM algorithm the original PIM algorithm can be easily derived from the above description of the modified PIM algorithm If we regroup the queues according to their destination outputs instead of being grouped by the inputs, the original PIM algorithm is now mapped into its modified counterpart The modified algorithm can thus be viewed as a mirror image of the original PIM algorithm, with the roles of the input output ports switched For the modified algorithm, the input selects among all unmatched outputs which it has cells queued This is similar to the grant step of the original algorithm Similarly, step two of our algorithm is equivalent to the accept step of the original algorithm In the rest of the paper, we will not distinguish between the original PIM the modified PIM since they are essentially the same III MAXIMUM THROUGHPUT OF MULTIPLE ITERATIONS PIM First, the ATM switch with one iteration PIM is analyzed Then, a recursive mula the throughput of the switch with multiple iterations PIM is derived Under saturated conditions, all the queues at each input will have at least one cell An output selects one unimly among the input requests A Throughput of One Iteration The throughput of an ATM switch with one iteration PIM scheduling is equal to the probability that an output gets matched after the first iteration Since each output selects unimly from all of the input requests, the probability of an

4 NONG et al: ANALYSIS OF NONBLOCKING ATM SWITCHES 63 input request being accepted by an output Then (1) Let be the probability that inputs (outputs) get matched output remains unmatched after the first iteration, then (2) where is the stirling number of the second kind which gives the number of ways of partitioning a set of elements into nonempty subsets It can be computed by the closedm expression [22] Fig 2 Maximum throughput as a function of switch size number of iterations iteration scheduling This is given in a recursive m by In (2), accounts the number of possible cases in which inputs contend the given outputs with the condition that each output is requested by at least one input Let denote the probability that inputs (outputs) remain unmatched after the first iteration with the condition that output remains unmatched, then where Using (3), the throughput of be derived as follows: (3) iteration PIM scheduling can B Throughput of Multiple Iterations The throughput of two iterations PIM scheduling is equal to the sum of the probability that output gets matched in the second iteration, that is output iteration gets matched in the second Similarly, we can derive the throughput of three iterations PIM scheduling as follows: output iteration get matched in the third To derive the throughput of iterations PIM scheduling, we first derive the expression the probability that there are inputs (outputs) remaining unmatched after the th Fig 2 shows the results the maximum throughput of a PIM switch as a function of switch size number of iterations As shown in this figure, the maximum throughput of an ATM switch with one iteration PIM scheduling converges to 063 [which corresponds to (1)] when the switch size grows Furthermore, the throughput increases significantly after each iteration of PIM scheduling Four iterations are sufficient achieving maximum throughput of about 99% a switch of any size IV QUEUEING MODEL AND ANALYSIS OF MULTIPLE ITERATIONS PIM In this section, we model the ATM switch with PIM scheduling using queueing theory analyze the underlying Markov chain Our method uses the concept of tagged queues in modeling the PIM switch leading to a smaller state space The concept of tagged input queue has been successfully used to evaluate the FIFO input-queued switch model [6], [15], [16] These switches involve a single stage of contention resolution On the other h, the switch with PIM scheduling, the contention resolution process consists of two stages As

5 64 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 1, FEBRUARY 1999 are ordered in a lexicographic order, ie, The set of states Fig 3 An example of the queueing model the PIM switch observed from the algorithm descriptions of PIM, a HOL cell in an input queue will contend transmission not only with the HOL cells of the same input, but also the HOL cells destined the same output As a result, the corresponding model is more complicated than the FIFO input-queued switch We make the following assumptions in developing the PIM switch model: 1) the switch operates synchronously; 2) every input queue has the same buffer size, namely ; 3) cells arrive at the inputs according to an iid Bernoulli process with parameter ( ) The destinations of the cells are unimly distributed over all the outputs Only one cell can arrive at each input in a time slot For an switch, if an input s load is, then every queue at this input has an offered load of ; 4) new cells arrive only at the beginning of the time slots, cells depart only at the end of the time slots Under the above assumptions, all the input queues will exhibit the same behavior when the system attains steady-state A queue at input with output as the destination is denoted by Fig 3 shows an example of the queueing model the PIM switch In this example, the occupancy of is taken as the tagged input queue, the number of HOL cells at input 1 is represented by the 1st HOL input queue, the number of HOL cells addressed output 1 is denoted by the 1st HOL output queue Both the HOL input queue the HOL output queue are virtual queues which do not exist in a real PIM switch, but are useful our mathematical analysis A Markov Model Analyzing the queueing model of the PIM switch requires the construction of the underlying Markov chain The states of the Markov chain are sampled at the end of the time slots can be expressed as a triplet, where,, refer to the lengths of the tagged input queue, virtual HOL input queue, virtual HOL output queue, respectively The state-space of this three-dimensional Markov chain is will be labeled as states in level of the Markov chain (Note that when the tagged input queue is empty, we are not interested in the lengths of the HOL input queue the HOL output queue Thus all states with are collapsed into a single state, ie, we are not explicitly keeping track of the state of the HOL input queue the HOL output queue when the tagged input queue is empty) This Markov chain has two important attributes, namely: 1) in moving from the state ( ) to a state ( ),, the chain must visit all intermediate levels at least once 2) this Markov chain is a quasi birth death (QBD) process, with block-partitioned m of transition probability matrix These attributes enable us to solve the Markov chain in an recursive way as we will show in the Appendix The transition probability matrix of the Markov chain is defined as follows: where Let, is a column vector of ones of length denote the probability that the HOL cell of the tagged input queue is blocked, denote the probability that the HOL cell of the tagged input queue is transmitted given that the remaining HOL cells at the end of the last time slot is, the remaining HOL cells at the end of the current time slot is there is a new cell arrival (is no new cell arrival) at the tagged input queue at the beginning of the current time slot For the first case (there is a new arrival cell at the tagged input queue at the beginning of the current time slot), we define three matrices,, as (4) (6), shown at the bottom of the next page In case there is no new cell arrival at the tagged input queue at the beginning of current time slot, we define three matrices, similar to as,, by replacing in with, in

6 NONG et al: ANALYSIS OF NONBLOCKING ATM SWITCHES 65 with in with, respectively By using the above equations, the element matrices in the transition probability matrix can be computed as Fig 4 Transition of the virtual HOL queues The remaining subsections will cover the computation of the success blocking probabilities we defined above, ie,,,,, respectively Provided that these probabilities are computed, the transition probability matrix can be constructed Once the transition probability matrix is known, it is a routine matter to derive the steady-state equations by utilizing the properties of Markov chains, solving the equations to obtain the steady-state probability vector The steadystate probability vector of the Markov chain is given by, where every element is a row vector of size, is a scalar Detailed procedures to obtain the steady-state probabilities are presented in the Appendix B Computing the Blocking Success Probabilities We now derive the equations computing the blocking probability the success probability The transition of the state of the virtual HOL input/output queues from the state to state is a two-step process 1) First, we account the newly arriving HOL cells to the virtual HOL input/output queues 2) Then, we consider the transition from the intermediate state to the final state after applying the PIM algorithm This process is illustrated in Fig 4 1) Arriving Cells at Virtual HOL Queues: Let denote the number of newly arriving HOL cells at the tagged input queue/virtual HOL input/virtual HOL output queues ( new arrivals to the tagged input queue/virtual HOL input/virtual HOL output queue), at the beginning of current time slot Note that since only one cell can arrive to an input in any time slot, then denotes the numbers of remaining HOL cells at the virtual HOL input/output queue ( is length of virtual HOL input/output queue), at the end of the previous time slot Let Define, Let be the probability that an input queue is empty in a time slot, where, let Two different cases need to be explicitly considered: a) when the tagged input queue is nonempty b) when is empty Case (a): Since the tagged input queue is nonempty, both If the current state is,( ) input queues of input ( ) th input queues of other inputs will be empty In the following, let denote that no cell arrives to the tagged input queue in the current time slot, let denote that a cell arrives to the tagged input queue Hence, Case (b): As stated earlier, when the tagged input queue is empty, we do not explicitly keep track of the state of the virtual HOL input queues HOL output queues In this case, all such states are collapsed into the single state with (4) (5) (6)

7 66 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 1, FEBRUARY 1999 When a cell arrives into the empty tagged input queue, we have to explicitly restore the states of the virtual HOL queues This is accomplished as follows A cell that arrives at when is empty will observe that another input queue at input is nonempty with probability Similarly the cell will observe that a th input queue at other input ports is nonempty, with probability TABLE I TRANSITIONS FROM (h i ;h o) TO (w 0 i ;w0 o) Q(i; j) (w 0 i ;w0 o ) Probability blocked: (h i ;h o ) P blo 00jH(h ;h ) (h i ;h o 0 1) P blo 01jH(h ;h ) (h i 0 1; h o ) P blo 10jH(h ;h ) (h i 0 1; h o 0 1) P blo 11jH(h ;h ) successful: (h i 0 1; h o 0 1) P sucjh(h ;h ) In this case, we reinterpret the as if they represent the number of arrivals into the virtual HOL input output queues in order to restore the states of the corresponding HOL queues Then 2) Transition to : Having determined the number of cell arrivals to the virtual HOL queues, we now consider the transition from the intermediate state to the final state after applying the PIM algorithm Given that the tagged input queue is nonempty, the inputs excluding input are divided into two subsets according to whether the th queue of the inputs is empty or not The cardinality of these sets are, respectively The state of sets set will affect the transitions of virtual HOL input queue virtual HOL output queue For the HOL cell of the tagged input queue, its contention process can be split into two stages In the first stage, the tagged input queue contends with other nonempty queues at the same input If it succeeds in the first stage contention, it joins the second stage contention with all successful th queues from other inputs Let be the successful queue at input if is blocked in the first contention stage Given, the possible values of in terms of are The last case can result from two situations: 1) when the HOL cell from the tagged input queue gets successfully matched or 2) another queue gets successfully matched, the output gets successfully matched to another input We define the following probabilities associated with the above transitions: the HOL cell at the tagged input queue gets blocked, given the HOL cell at the tagged input queue gets blocked, given the HOL cell at the tagged input queue gets blocked, given the HOL cell at the tagged input queue gets blocked, given the HOL cell at the tagged input queue gets transmitted, given Table I summarizes the transitions their corresponding probabilities With respect to whether there is a new arrival at the tagged input queue or not, the two blocking probabilities of are computed as follows Given, the blocking probability is computed as shown in (7), at the bottom of the next page, in which (8) (9) (10) represents the average number of input queues that contain only one buffered cell, with condition that there is a new arrival cell at the tagged input queue in (8) is the probability that the length of a queue of the input queues of input is equal to one (there is only one buffered cell in this input queue) during a time slot Similarly, / represents the average number of th input queues that contain only one buffered cell given that is nonempty/empty at the beginning of the current time slot in (9) (10) are the probabilities that the length of a queue of the th queues is equal to one in these two cases The three probabilities of,, are thus given by For there is no new cell arrival at the tagged input queue The blocking probability can be computed similarly as provided that is replaced

8 NONG et al: ANALYSIS OF NONBLOCKING ATM SWITCHES 67 with as (12) (13) (11) is replaced with Finally, we can compute the two success probabilities, 3) Applying the PIM Algorithm: We now compute the probabilities in Table I by considering each iteration of the PIM scheduling algorithm The state of the switch at the beginning of each iteration is characterized by the following parameters: number of unmatched inputs/outputs at the beginning of th iteration; or (7)

9 68 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 1, FEBRUARY 1999 number of nonempty queues in input at the beginning of th iteration, whose outputs are still unmatched; number of nonempty th queues in inputs (including input ) at the beginning of th iteration matching At the end of the iteration, the following parameters can be defined: number of inputs/outputs that get matched at the end of th iteration, number of outputs whose corresponding nonempty queues in input that get matched at the end of th iteration, number of inputs in set that get matched at the end of th iteration, For the sake of simplicity, we do not mention the iteration number in the following discussion If no iteration number is mentioned, then the current iteration is implied Let represent the state of the matching process input output of the switch, where with 0 representing that the input/output is unmatched 1 representing that the input/output is matched at the end of the current iteration The possible states of the matching process are 00, 01, 10, 11 However, the state 11 should explicitly consider if the tagged input queue at input is matched Thus, the state 11 is split into two:, respectively Given the current state of the switch the current state of the matching process the resulting state of the switch the resulting state of the matching process is controlled by the transition probabilities defined: at the end of current iteration, the HOL cell at the tagged input queue gets blocked, both input output remain unmatched given that both input output were unmatched at the beginning of current iteration at the end of current iteration, the HOL cell at the tagged input queue gets blocked, input remains unmatched output gets matched given that both input output were unmatched at the beginning of current iteration at the end of current iteration, the HOL cell at the tagged input queue gets blocked, input gets matched output remains unmatched given that both input output were unmatched at the beginning of current iteration at the end of current iteration, the HOL cell at the tagged input queue gets blocked, both input output get matched given that both input output were unmatched at the beginning of current iteration at the end of current iteration, the HOL cell at the tagged input queue gets blocked, input remains unmatched given that input was unmatched output was matched at the beginning of current iteration Fig 5 The matching process state transition diagram at the end of current iteration, the HOL cell at the tagged input queue gets blocked, input gets matched given that input was unmatched output was matched at the beginning of current iteration at the end of current iteration, the HOL cell at the tagged input queue gets blocked, output remains unmatched given that input was matched output was unmatched at the beginning of current iteration at the end of current iteration, the HOL cell at the tagged input queue gets blocked, output gets matched given that input was matched output was unmatched at the beginning of current iteration at the end of current iteration, the HOL cell at the tagged input queue gets matched with output given that input output were unmatched at the beginning of current iteration These probabilities are functions of the current state of the switch ( ) The transitions among the states of the matching process can be represented by the state transition diagram shown in Fig 5 with the state space We derive equations the transition probabilities next We define the following probabilities associated with the first stage of contention a cell: Pr{the HOL cell at th queue of an input in set succeeds in the first stage contention} Pr{the HOL cell at th queue of an input in set succeeds in the first stage contention} Pr{the HOL cell at th queue of an input in set succeeds in the first stage contention} Here,, are functions of, are computed as

10 NONG et al: ANALYSIS OF NONBLOCKING ATM SWITCHES 69 get matched is Knowing the above probabilities, computed as can be easily Fig 6 P blo 11j00 (a) (b) Diagram deriving P blo 00j00, P blo 01j00, P blo 10j00, Let be the number of queues excluding the queue from input that succeed in the first stage of contention, is the number of outputs contended by the inputs There are three subproblems to be considered in computing the transition probabilities in th iteration given 1) What is the probability that inputs contend outputs? 2) What is the probability that inputs in set (whose cardinality is ) get matched? 3) What is the probability that out of outputs whose corresponding queues in input are nonempty get matched? The equations below consider each of the subproblems in computing the transition probabilities We first consider the situation where both input output are unmatched at the beginning of the current iteration Fig 6 shows the possible scenarios that can arise in this case Case a) represents the situation where output remains unmatched at the end of the current iteration, case b) represents the situation where output gets matched a) Computing : In this case both input output remain unmatched From Fig 6(a) given, the probability that the queue that succeeds in the first stage of contention at input gets blocked at its corresponding output is b) Computing : In this case, input gets matched while output remains unmatched Hence, we compute only the aggregated probability over the set of all possible The probability that the queue that succeeds in the first stage of contention at input succeeds in getting matched in the second stage of contention is The probability that inputs which are elements of set get matched is Theree, is given by Among the outputs that get matched, of them will see their corresponding queues in input being nonempty The number of combinations satisfying this condition is (14) Given that input is blocked, it is clear that each combination of out of inputs gets matched with dual probability The probability that inputs which are elements of the set c) Computing : In this case, output gets matched while input remains unmatched We compute only the aggregated probability over the set of all possible There are two cases to be considered here: (i) fails the first stage of contention, (ii) survives the first stage of contention Theree is the sum of two probabilities where are probabilities the two cases (i) (ii), respectively

11 70 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 1, FEBRUARY 1999 Case (i): fails in the first stage of contention f) Computing : In this case, input remains unmatched, while output is already matched Then where where g) Computing : In this case input gets matched while output has already been matched at the beginning of the iteration is successful in the first stage of con- Case (ii): tention where Next we consider the cases where input is already matched, while output is still unmatched Once input has been matched, the iterations thereafter, we are interested only in the state of output, ie, whether it is matched or unmatched h) Computing : In this case input is already matched, while output remains unmatched at the end of the iteration Then where d) Computing : Recalling that in the matching process Markov chain, state is an absorbing state, so this transition probability is computed without consideration on e) Computing : Then, is computed from the boundary condition as i) Computing : In this case, output gets matched at the end of the iteration This is feasible only if at least one of th queues of the inputs in set succeed in the first stage of contention at their respective inputs Now we consider the cases where output has already been matched, while input is still unmatched Note that in this case the tagged input queue is no longer under consideration matching because output is already matched The states of the switch at the end of each iteration can be viewed as a weighted tree with the nodes of the tree corresponding to the switch states The root of the tree is the initial state of the switch All states in level of the tree correspond to

12 NONG et al: ANALYSIS OF NONBLOCKING ATM SWITCHES 71 the states of the switch at the end of the th iteration of the PIM algorithm Weights are assigned to the arcs between the states are equal to the transition probabilities or Each state is assigned a probability equal to the product of the transition probabilities along the arcs from the root to the state The probabilities,,, at the end of iterations of the PIM algorithm can be computed as C Solving the Markov Chain As can be seen from the above equations, must be known in advance in order to compute the steady-state probabilities In the Appendix, we give detailed procedures to derive the computation mulas these parameters The steady-state probabilities are given by Fig 7 The throughput of a PIM switch, as a function of offered load, with a buffer size b i = 10 (15) (16) where Recalling the definitions of the matrice appear in, the elements of this matrice are functions of This naturally suggests an iterative solution [16] Initially, is set to, which corresponds to the case that there is no new arriving cell at the tagged input queue at the beginning of a time slot, is approximated by Then the next is obtained by using (15) compute the new by (16) This iterating process continues until the converge to a fixed point Finally, the values of steady-state probabilities ( ) are computed by (16) Fig 8 The throughput of a PIM switch, as a function of offered load, with a buffer size b i =10 respectively, then Using Little s theorem [21] which holds a queueing system in steady-states, the mean cell delay, the mean queue length, the queue s throughput are related together as follows: D Computing the Permance Metrics Once the steady-state probabilities are known, then interesting permance parameters, such as throughput, mean queue length mean cell loss probability can be computed directly by using the known parameters Let,, be throughput, mean queue length, mean cell loss probability, V NUMERICAL RESULTS Both mathematical analysis simulation results are presented in this section in order to investigate the accuracy of the above queueing model Figs 7 9 show the switch throughput as a function of offered load PIM switch sizes 4, 8, 16, with various PIM scheduling iteration numbers 1, 2,

13 72 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 1, FEBRUARY 1999 Fig 9 The throughput of a PIM switch, as a function of offered load, with a buffer size b i = 10 Fig 11 The mean cell delay of a PIM switch, as a function of offered load, with a buffer size b i =10 Fig 10 The mean cell delay of a PIM switch, as a function of offered load, with a buffer size b i =10 3, respectively It can be seen that when the switch size increases, the throughput of the switch decreases under high offered load (greater than 60% when maximum iteration is 1) Also from this figure, we can see that the saturation throughput will increase as the PIM scheduling iteration increases It is expected that with more iterations, more HOL cells get matched during a scheduling iteration The curves show that three iterations are enough to get a high throughput 90% Comparing Figs 7 9 with Fig 2, we can see that even under saturated traffic loads, our queueing model approximates the original system quite well Figs show the mean cell delay as a function of offered load the different PIM switch sizes 4, 8, 16 with various PIM iteration numbers one, two, three The figures indicate that the mean cell delay increases as the switch size increases also as the offered load increases But when the number of PIM scheduling iterations is increased, even from one to two, the mean delay increased slowly with the traffic load as compared with just one iteration For single iteration PIM scheduling, the mean cell delay increases dramatically when the offered load exceeds 60%, Fig 12 The mean cell delay of a PIM switch, as a function of offered load, with a buffer size b i =10 which indicates that PIM switches with single iteration PIM scheduling will be overloaded when the traffic load is greater than 60% However, two three iteration PIM, this overloaded traffic point is about 08 This phenomenon can also be observed in Figs 7 9 Notice that when the traffic load is extremely low, such as 01, all curves cluster into a single point It is not difficult to underst that, under low traffic load, the opportunity that more than one HOL cell contends a common input/output is small That is, single iteration PIM scheduling is typically enough to find a maximal matching When the traffic load grows, the chances of conflicts increase more iterations are needed using PIM scheduling to achieve a maximal matching In Fig 13, the mean cell loss probabilities of PIM switches with queue size of ten cells are given as a function of offered load It can be seen that, a medium size PIM switch with three iterations PIM scheduling (such as 16 16) with traffic load less than 60%, a buffer size of 10 cells per queue is sufficient to guarantee a cell loss probability 10 As mentioned in the introduction of this paper, we are extending these results to more realistic traffic patterns This

14 NONG et al: ANALYSIS OF NONBLOCKING ATM SWITCHES 73 by where every element is a row vector of size, is a scalar From the definition of the transition probability matrix, we know that By exping (17), we have (17) (18) (19) (20) (21) (22) Fig 13 The mean cell loss probability of a PIM switch, as a function of offered load, with a buffer size b i = 10 complicates the mathematical analysis, but would also lead to more practical result VI CONCLUSION A queueing model the permance analysis of a multiple input queued ATM switch with PIM scheduling under rom traffic loads has been presented The queueing model provides a rather general method in analyzing such ATM switches in terms of throughput, mean queue length, mean cell delay, mean cell loss probability given the switch size, queues buffer size, offered load As seen from Section V, the analytical results of the queueing model is able to approximate the simulation results satisfactorily The contribution of this paper is twofold First, the throughput of an ATM switch with multiple iteration PIM scheduling in case of saturated traffic load is analyzed mathematically Second, a theoretical analysis various permance parameters including throughput, mean cell delay, mean cell loss probability of an ATM switch using a PIM scheduling scheme is presented Such theoretical analysis is lacking in existing literature on ATM switches with PIM or variations of PIM scheduling [7], [9] [12] Several assumptions were made in order to make the original switch model tractable analysis The most important is the unim traffic assumption, ie, cells arrive at each input according to an iid Bernoulli process, the output destinations of arriving cells are unimly distributed over all outputs We are currently working on extending the model ATM switches with bursty correlated traffic APPENDIX COMPUTATIONS OF THE STEADY-STATE PROBABILITIES Here we give the procedures to compute the steady-state probabilities of the Markov chain Given that is the steady-state probability of the state, where is the length of the tagged input queue, is the length of the virtual HOL input queue, is the length of the virtual HOL output queue The steady-state probability vector of the Markov chain is given In order to solve the linear equations above, we note that once are known, the remaining ( ) can be solved by substitute the known ones into (20) (22) step by step The key problem in solving these linear equations becomes how to find the values of Fortunately, the special structure of facilitates our solving of these equations As mentioned in Section IV-A, is a QBD process which holds an important attribute that in moving from a state to a higher-level state, the chain must visit all intermediate levels at least once More detail attributes in our case are: 1) any ( ), it appears in three equations; 2), which we notate as boundary probabilities, however, they appear in two equations Utilize the attribute of the boundary probabilities, we can express as function of from (22) Substitute (23) into (21), of (23) can be expressed as function (24) Similarly, ( ) can be expressed as function of by further the operations recursively Let ( )bea matrix defined as Now To replace have can be written as (25) (26) in (19) by (26) rearrange the equation, we (27) To be consistent with the denotation of ( ), we define as

15 74 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL 7, NO 1, FEBRUARY 1999 Note that is a row vector of length of at this time Now we can express all ( ) as function of By utilizing the condition that (28),we get (29) [22] M Abramowitz I A Stegun, Eds, Hbook of Mathematical Functions with Formulas, Graphs, Mathematical Tables New York: Wiley, 1972 [23] L Jacob A Kumar, Saturated throughput analysis of an input queueing ATM switch with multiclass bursty traffic, IEEE Trans Commun, vol 43, pp , Apr 1995 [24] X R Cao D Towsley, A permance model ATM switches with general packet length distributions, IEEE/ACM Trans Networking, vol 3, pp , June 1995 [25] N McKeown, V Anantharam, J Walr, Achieving 100% throughput in an input-queued switch, in Proc IEEE INFOCOM 96, 1996, vol 1, pp Once is known, all other state probabilities can be computed by (28) REFERENCES [1] R Rooholamini V Cherkassky, Finding the right ATM switch the market, IEEE Trans Comput, vol 27, pp 16 28, Apr 1994 [2] R Y Awdeh H T Mouftah, Survey of ATM switch architectures, Computer Networks ISDN Systems, vol 27, pp , 1995 [3] M Hamdi J Muppala, Permance evaluation of nonblocking ATM switches under various traffic buffering schemes, Int J Commun Syst, vol 9, pp 59 79, 1996 [4] M Karol, M Hluchyj, S Morgan, Input versus output queueing on a space division packet switch, IEEE Trans Commun, vol 35, pp , Dec 1987 [5] A Pattavina G Bruzzi, Analysis of input output queueing nonblocking ATM switches, IEEE/ACM Trans Networking, vol 1, pp , June 1993 [6] P Achille B Giacomo, Analysis of input output queueing nonblocking ATM switches, ACM Trans Networking, vol 1, June 1993 [7] T E Anderson, S S Owicki, J B Saxe, C P Thacker, Highspeed switch scheduling local-area networks, ACM Trans Comput Syst, vol 11, no 4, pp , Nov 1993 [8] N McKeown, M Izzard, A Mekkittikul, B Ellersick, M Horowitz, Tiny tera: A packet switch core, IEEE Micro, vol 17, pp 26 33, Jan 1997 [9] N W McKeown, Scheduling algorithms input-queued cell switches, PhD dissertation, Univ Calinia at Berkeley, 1994 [10] N Mckeown, P Varaiya, J Walr, Scheduling cells in an input-queued switch, Electron Lett, vol 29, no 25, pp , 1993 [11] B Prabhakar, N Mckeown, R Ahuja, Multicast scheduling input-queued switches, IEEE J Select Areas Commun, vol 15, pp , June 1997 [12] R O LaMaire D N Serpanos, Two-dimentional round-robin schedulers packet switches with multiple input queues, IEEE/ACM Trans Networking, vol 2, pp , Oct 1994 [13] J A Bondy U S R Murty, Graph Theory with Applications Amsterdam, The Netherls: Elsevier, 1976 [14] M Hamdi, J Wang, K Ben Letaief, Efficient estimation of cell loss cell delay on nonblocking ATM switches using importance sampling, presented at GLOBECOM 97 [15] Y C Jung C K Un, Analysis of backpressure-type packet switches with input output buffering, Proc Inst Elect Eng, vol 140, Aug 1993 [16], Permance analysis of packet switches with input output buffers, Computer Networks ISDN Systems, vol 26, pp , 1994 [17] M J Lee D S Ahn, Cell loss analysis design trade-offs of nonblocking ATM switches, IEEE/ACM Trans Networking, vol 3, pp , Apr 1995 [18] M K Mehmet-Ali, M Youssefi, H T Nguyen, The permance analysis implementation of an input access scheme in a high-speed packet switch, IEEE Trans Commun, vol 42, pp , Dec 1994 [19] M F Neuts, Matrix-Geometric Solutions in Stochastic Models Baltimore, MD: The Johns Hopkins Press, 1981 [20] E Del Re R Fantacci, Permance evaluation of input output queueing techniques in ATM switching systems, IEEE Trans Commun, vol 41, pp , Oct 1993 [21] J Medhi, Stochastic Models in Queueing Theory New York: Academic, 1991 Ge Nong (S 97) received the BE degree from Nanling Aeronautical Institute, JiangShu, China, in 1992 the ME degree from South China University of Science Technology, GuangDong, China, in 1995, all in computer engineering He is currently working toward the PhD degree in the Department of Computer Science, The Hong Kong University of Science Technology (HKUST), Kowloon, Hong Kong His current research interests include permance modeling of ATM switches, architectures of highspeed packet switches, providing QoS guarantees on high-speed packet switching networks Jogesh K Muppala (S 86 M 87) received the PhD degree in electrical engineering from Duke University, Durham, NC, in 1991 He is currently an Associate Professor in the Department of Computer Science, The Hong Kong University of Science Technology (HKUST), Kowloon, Hong Kong He was previously with Software Productivity Consortium, Herndon, VA His research interests include permance dependability modeling, high speed networking, distributed systems, stochastic Petri nets He has published more than 30 refereed journal conference papers in these areas He is the program cochair the 1999 Pacific Rim International Symposium on Dependable Computing He has also served on program committees of international conferences Dr Muppala was recently given the Teaching Excellence Appreciation Award by the Dean of Engineering at HKUST Mounir Hamdi (S 89 M 91) received the BSc degree with distinction in electrical engineering (computer engineering) from the University of Southwestern Louisiana, in 1985, the MSc PhD degrees in electrical engineering from the University of Pittsburgh in , respectively While at the University of Pittsburgh, he was a Research Fellow involved with various research projects on interconnection networks, high-speed communication, parallel algorithms, switching theory, computer vision In 1991, he joined the Computer Science Department at The Hong Kong University of Science Technology as an Assistant Professor He is now an Associate Professor of Computer Science the Director of the Computer Engineering Programme In 1999, he has been named one of the Ten Best Lecturers by the University s students His main areas of research are ATM packet switching architectures, high-speed networks, wireless networking, parallel computing He has published more than 80 papers on these areas in various journals conference proceedings He cofounded cochairs the International Workshop on High-Speed Network Computing Dr Hamdi is on the editorial board of the IEEE Communications Magazine Parallel Computing, has been on the Program Committee of various International Conferences He received the Best Paper Award at the 12th International Conference on Inmation Networking