Parallel Packet Switching using Multiplexors with Virtual Input Queues

Transcription

1 Parallel Packet Switching using Multiplexors with Virtual Input Queues Ahmed Aslam Kenneth J. Christensen Department of Computer Science and Engineering University of South Florida Tampa, Florida {aaslam, AA/KJC00 (lcn02_2.ppt - 0/8/02) Topics Introduction Previous work in parallel packet switches (PPS) The cell switch Simulation evaluation Summary and future work eferences AA/KJC002

2 Introduction Output Queued switches (OQ) limited by memory bandwidth Memory bandwidth must be N times link speed» N = number of ports Input Queued (IQ) switches offer a solution Memory bandwidth is link speed Scalability limited by scheduling Scalability limited by memory speed (very fast links) Parallel Packet Switches (PPS) is the next step - Multiple switching planes» K internal planes operate at link speed r = S/K» = external link speed, S = internal speed-up» S < K and r < AA/KJC003 Introduction continued A generic Parallel Packet Switch (PPS) Demultiplexor r N x N switch plane Multiplexor r N K N AA/KJC004 DEMUX distributes packets to switch planes MUX collects packets and transmit them (usually in order) 2

3 Introduction continued Key requirements of PPS design NO or small high speed buffers at Demultiplexor(DEMUX) and Multiplexor(MUX) NO centralized scheduler NO or minimal information exchange between components Should be stable for any schedulable traffic arrival pattern Should try to use existing switches as internal switch planes AA/KJC005 Previous work in Parallel Packet Switches Various PPS Traffic Distribution Buffering at DEMUX, MUX Scheduler Emulating FCFS-OQ Stable QoS Chiussi Flow level Yes Distributed Iyer00 Packet level No Centralized Yes if S>2K/(K+2) Yes if S>3K/(K+3) Iyer0 Packet level Yes Distributed Yes but within a delay bound Khotimsky Mneimneh Packet level Packet level No at DEMUX No Distributed Centralized Yes if K 2 /r S K/ K/2 Yes but r = AA/KJC006 3

4 The Cell Switch Traffic Distribution Buffering at DEMUX, MUX Scheduler Emulating FCFS-OQ Stable QoS Packet level Yes Distributed No Yes No AA/KJC007 The Cell Switch continued Demultiplexor Architecture for K = 3, N =4 r = S/K Algorithm r = S/K K buffers of size N cells each r = S/K AA/KJC008 4

5 The Cell Switch continued Demultiplexor Algorithm WHILE (true) DO eceive a cell Find destination port for cell Increment sequence # of inport-outport flow Append sequence # to cell Find next buffer (plane) using round robin by flow Queue cell at tail of buffer AA/KJC009 The Cell Switch continued Multiplexor Architecture for K = 3, N =4 New r = S/K r = S/K Algorithm K buffer blocks, each block has N VIQs of size 2N cells each r = S/K AA/KJC00 5

6 The Cell Switch continued Multiplexor Algorithm WHILE (true) DO FO (i = to N) FO (j = to K) Find minimum sequence # in HOL cells of buffer[i][j] min_seq_index = j IF (minimum sequence # == expected next seq.# of flow i) Transmit HOL cell from buffer[i][min_seq_index] Increment expected next sequence # of flow i AA/KJC0 The Cell Switch continued Buffering at a Demultiplexor = KN cells For 64 bytes cells, K = 0, N = 32, it is 20 Kbytes Buffering at a Multiplexor = 2KN 2 cells For 64 bytes cells, K = 0, N = 32, it is.25 Mbytes Seems feasible using current SAM technology AA/KJC02 6

7 The Cell Switch continued [Khotimsky02]: PPS is stable for a flow arrival process bounded in time scale T by a sustained rate X if Load balancing algorithm at DEMUX is stable e-assembler at MUX serves cells of a flow in correct order e-assembler does not do unnecessary waits e-assembler servers a flow at rate U X All above properties are satisfied by AA/KJC03 Simulation Evaluation Simulation models built of OQ, islip, and using CSIM8 Traffic models Bernoulli and Interrupted Bernoulli (IBP) arrivals of cells Packet trace collected on USF Gigabit backbone» Near 20 million packets, Mean packet length = 902.6B For Bernoulli and IBP experiments, N = 6, K = 0 For Packet trace experiment, N = 4, K = 0 Infinite size buffers in OQ, islip, switch planes of islip used 4 iterations AA/KJC04 7

8 Simulation Evaluation continued High degree balanced Bernoulli experiment Each input and output has N flows All inputs and outputs have same offered load Mean delay (cells) islip OQ Load (%) islip and OQ results are validated ([M99]) AA/KJC05 Simulation Evaluation continued Low degree balanced Bernoulli experiment Each input and output has r flows (r = 2) All inputs and outputs have same offered load Mean delay (cells) islip OQ islip is unstable beyond 87% Load Load (%) AA/KJC06 8

9 Simulation Evaluation continued Low degree unbalanced Bernoulli experiment Some inputs have r flows, other have 2r flows (r =2) All inputs and outputs do not have same offered load Mean delay (cells) islip OQ islip is unstable beyond 86% Load Load (%) AA/KJC07 Simulation Evaluation continued High degree balanced IBP experiment Burstiness makes all switches the same 000 islip Mean delay (cells) 00 0 OQ Load (%) AA/KJC08 9

10 Simulation Evaluation continued Packet trace experiment External link speed is 0-Gbps 64-bytes internal cells for islip and Mean delay (microsec) islip OQ Load (%) AA/KJC09 Summary and future work A new PPS architecture Uses virtual input queues (VIQs) in multiplexor equires distributed scheduling easonable performance Future work Buffering in MUX may cause scaling to large N difficult Performance comparison with other PPS architectures Hardware implementation of DEMUX and MUX algorithms Analytical modeling AA/KJC020 0

11 eferences [CKK98] F. Chiussi, D. Khotimsky, and S. Krishnan, Generalized Inverse Multiplexing of Switched ATM Connections, GLOBECOM, 998. [IAM00] S. Iyer, A. Awadallah, and N. McKeown, Analysis of a Packet Switch with Memories unning Slower than the Line ate, INFOCOM, [IM0] S. Iyer and N. McKeown, Making Parallel Packet Switches Practical, INFOCOM, 200. [KK0] D. Khotimsky and S. Krishnan, Stability Analysis of a Parallel Packet Switch with Bufferless Input Demultiplexors, ICC, 200. [KK02] D. Khotimsky and S. Krishnan, Evaluation of Open-Loop Sequence Control Schemes for Multi-path Switches, ICC, [M99] N. McKeown, The islip Scheduling Algorithm for Input- Queued Switches, IEEE/ACM Transactions on Networking, 999. [MSS0] S. Mneimneh, V. Sharma, and K. Siu, On Scheduling Using Parallel Input- Output Queued Crossbar Switches With no Speedup, HPS, 200. AA/KJC02